From: Sasha Levin Date: Sun, 26 Mar 2023 23:04:16 +0000 (-0400) Subject: Fixes for 4.19 X-Git-Tag: v5.15.105~71 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=25668c5863e2323c7cad6f4de01683d571e3c7c5;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 4.19 Signed-off-by: Sasha Levin --- diff --git a/queue-4.19/atm-idt77252-fix-kmemleak-when-rmmod-idt77252.patch b/queue-4.19/atm-idt77252-fix-kmemleak-when-rmmod-idt77252.patch new file mode 100644 index 00000000000..5df8143cac6 --- /dev/null +++ b/queue-4.19/atm-idt77252-fix-kmemleak-when-rmmod-idt77252.patch @@ -0,0 +1,92 @@ +From 70b301b3dd0f1432c46b8ff8a53b9aa1102fd184 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 14:33:18 +0000 +Subject: atm: idt77252: fix kmemleak when rmmod idt77252 + +From: Li Zetao + +[ Upstream commit 4fe3c88552a3fbe1944426a4506a18cdeb457b5a ] + +There are memory leaks reported by kmemleak: + + unreferenced object 0xffff888106500800 (size 128): + comm "modprobe", pid 1017, jiffies 4297787785 (age 67.152s) + hex dump (first 32 bytes): + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + backtrace: + [<00000000970ce626>] __kmem_cache_alloc_node+0x20c/0x380 + [<00000000fb5f78d9>] kmalloc_trace+0x2f/0xb0 + [<000000000e947e2a>] idt77252_init_one+0x2847/0x3c90 [idt77252] + [<000000006efb048e>] local_pci_probe+0xeb/0x1a0 + ... + + unreferenced object 0xffff888106500b00 (size 128): + comm "modprobe", pid 1017, jiffies 4297787785 (age 67.152s) + hex dump (first 32 bytes): + 00 20 3d 01 80 88 ff ff 00 20 3d 01 80 88 ff ff . =...... =..... + f0 23 3d 01 80 88 ff ff 00 20 3d 01 00 00 00 00 .#=...... =..... + backtrace: + [<00000000970ce626>] __kmem_cache_alloc_node+0x20c/0x380 + [<00000000fb5f78d9>] kmalloc_trace+0x2f/0xb0 + [<00000000f451c5be>] alloc_scq.constprop.0+0x4a/0x400 [idt77252] + [<00000000e6313849>] idt77252_init_one+0x28cf/0x3c90 [idt77252] + +The root cause is traced to the vc_maps which alloced in open_card_oam() +are not freed in close_card_oam(). The vc_maps are used to record +open connections, so when close a vc_map in close_card_oam(), the memory +should be freed. Moreover, the ubr0 is not closed when close a idt77252 +device, leading to the memory leak of vc_map and scq_info. + +Fix them by adding kfree in close_card_oam() and implementing new +close_card_ubr0() to close ubr0. + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Signed-off-by: Li Zetao +Reviewed-by: Francois Romieu +Link: https://lore.kernel.org/r/20230320143318.2644630-1-lizetao1@huawei.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/atm/idt77252.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c +index bc06f5919839c..3380322df98e0 100644 +--- a/drivers/atm/idt77252.c ++++ b/drivers/atm/idt77252.c +@@ -2915,6 +2915,7 @@ close_card_oam(struct idt77252_dev *card) + + recycle_rx_pool_skb(card, &vc->rcv.rx_pool); + } ++ kfree(vc); + } + } + } +@@ -2958,6 +2959,15 @@ open_card_ubr0(struct idt77252_dev *card) + return 0; + } + ++static void ++close_card_ubr0(struct idt77252_dev *card) ++{ ++ struct vc_map *vc = card->vcs[0]; ++ ++ free_scq(card, vc->scq); ++ kfree(vc); ++} ++ + static int + idt77252_dev_open(struct idt77252_dev *card) + { +@@ -3007,6 +3017,7 @@ static void idt77252_dev_close(struct atm_dev *dev) + struct idt77252_dev *card = dev->dev_data; + u32 conf; + ++ close_card_ubr0(card); + close_card_oam(card); + + conf = SAR_CFG_RXPTH | /* enable receive path */ +-- +2.39.2 + diff --git a/queue-4.19/bluetooth-btqcomsmd-fix-command-timeout-after-settin.patch b/queue-4.19/bluetooth-btqcomsmd-fix-command-timeout-after-settin.patch new file mode 100644 index 00000000000..ad8a37225a4 --- /dev/null +++ b/queue-4.19/bluetooth-btqcomsmd-fix-command-timeout-after-settin.patch @@ -0,0 +1,74 @@ +From 1270624549133ac75c055b30615e44a1cc760a7d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Mar 2023 14:31:55 +0100 +Subject: Bluetooth: btqcomsmd: Fix command timeout after setting BD address + +From: Stephan Gerhold + +[ Upstream commit 5d44ab9e204200a78ad55cdf185aa2bb109b5950 ] + +On most devices using the btqcomsmd driver (e.g. the DragonBoard 410c +and other devices based on the Qualcomm MSM8916/MSM8909/... SoCs) +the Bluetooth firmware seems to become unresponsive for a while after +setting the BD address. On recent kernel versions (at least 5.17+) +this often causes timeouts for subsequent commands, e.g. the HCI reset +sent by the Bluetooth core during initialization: + + Bluetooth: hci0: Opcode 0x c03 failed: -110 + +Unfortunately this behavior does not seem to be documented anywhere. +Experimentation suggests that the minimum necessary delay to avoid +the problem is ~150us. However, to be sure add a sleep for > 1ms +in case it is a bit longer on other firmware versions. + +Older kernel versions are likely also affected, although perhaps with +slightly different errors or less probability. Side effects can easily +hide the issue in most cases, e.g. unrelated incoming interrupts that +cause the necessary delay. + +Fixes: 1511cc750c3d ("Bluetooth: Introduce Qualcomm WCNSS SMD based HCI driver") +Signed-off-by: Stephan Gerhold +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btqcomsmd.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/bluetooth/btqcomsmd.c b/drivers/bluetooth/btqcomsmd.c +index 874172aa8e417..a698b1f6394b2 100644 +--- a/drivers/bluetooth/btqcomsmd.c ++++ b/drivers/bluetooth/btqcomsmd.c +@@ -146,6 +146,21 @@ static int btqcomsmd_setup(struct hci_dev *hdev) + return 0; + } + ++static int btqcomsmd_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) ++{ ++ int ret; ++ ++ ret = qca_set_bdaddr_rome(hdev, bdaddr); ++ if (ret) ++ return ret; ++ ++ /* The firmware stops responding for a while after setting the bdaddr, ++ * causing timeouts for subsequent commands. Sleep a bit to avoid this. ++ */ ++ usleep_range(1000, 10000); ++ return 0; ++} ++ + static int btqcomsmd_probe(struct platform_device *pdev) + { + struct btqcomsmd *btq; +@@ -195,7 +210,7 @@ static int btqcomsmd_probe(struct platform_device *pdev) + hdev->close = btqcomsmd_close; + hdev->send = btqcomsmd_send; + hdev->setup = btqcomsmd_setup; +- hdev->set_bdaddr = qca_set_bdaddr_rome; ++ hdev->set_bdaddr = btqcomsmd_set_bdaddr; + + ret = hci_register_dev(hdev); + if (ret < 0) +-- +2.39.2 + diff --git a/queue-4.19/bluetooth-btsdio-fix-use-after-free-bug-in-btsdio_re.patch b/queue-4.19/bluetooth-btsdio-fix-use-after-free-bug-in-btsdio_re.patch new file mode 100644 index 00000000000..11dff35d11e --- /dev/null +++ b/queue-4.19/bluetooth-btsdio-fix-use-after-free-bug-in-btsdio_re.patch @@ -0,0 +1,39 @@ +From d58ee6bbc800511f5936c066631b89339e7a979f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Mar 2023 16:07:39 +0800 +Subject: Bluetooth: btsdio: fix use after free bug in btsdio_remove due to + unfinished work + +From: Zheng Wang + +[ Upstream commit 1e9ac114c4428fdb7ff4635b45d4f46017e8916f ] + +In btsdio_probe, &data->work was bound with btsdio_work.In +btsdio_send_frame, it was started by schedule_work. + +If we call btsdio_remove with an unfinished job, there may +be a race condition and cause UAF bug on hdev. + +Fixes: ddbaf13e3609 ("[Bluetooth] Add generic driver for Bluetooth SDIO devices") +Signed-off-by: Zheng Wang +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btsdio.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c +index 20142bc77554c..bd55bf7a9914c 100644 +--- a/drivers/bluetooth/btsdio.c ++++ b/drivers/bluetooth/btsdio.c +@@ -353,6 +353,7 @@ static void btsdio_remove(struct sdio_func *func) + + BT_DBG("func %p", func); + ++ cancel_work_sync(&data->work); + if (!data) + return; + +-- +2.39.2 + diff --git a/queue-4.19/bpf-adjust-insufficient-default-bpf_jit_limit.patch b/queue-4.19/bpf-adjust-insufficient-default-bpf_jit_limit.patch new file mode 100644 index 00000000000..42fd20a2ce1 --- /dev/null +++ b/queue-4.19/bpf-adjust-insufficient-default-bpf_jit_limit.patch @@ -0,0 +1,78 @@ +From ec66a4beeebc1489124e0c37dbdb69547e3e206c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 15:37:25 +0100 +Subject: bpf: Adjust insufficient default bpf_jit_limit + +From: Daniel Borkmann + +[ Upstream commit 10ec8ca8ec1a2f04c4ed90897225231c58c124a7 ] + +We've seen recent AWS EKS (Kubernetes) user reports like the following: + + After upgrading EKS nodes from v20230203 to v20230217 on our 1.24 EKS + clusters after a few days a number of the nodes have containers stuck + in ContainerCreating state or liveness/readiness probes reporting the + following error: + + Readiness probe errored: rpc error: code = Unknown desc = failed to + exec in container: failed to start exec "4a11039f730203ffc003b7[...]": + OCI runtime exec failed: exec failed: unable to start container process: + unable to init seccomp: error loading seccomp filter into kernel: + error loading seccomp filter: errno 524: unknown + + However, we had not been seeing this issue on previous AMIs and it only + started to occur on v20230217 (following the upgrade from kernel 5.4 to + 5.10) with no other changes to the underlying cluster or workloads. + + We tried the suggestions from that issue (sysctl net.core.bpf_jit_limit=452534528) + which helped to immediately allow containers to be created and probes to + execute but after approximately a day the issue returned and the value + returned by cat /proc/vmallocinfo | grep bpf_jit | awk '{s+=$2} END {print s}' + was steadily increasing. + +I tested bpf tree to observe bpf_jit_charge_modmem, bpf_jit_uncharge_modmem +their sizes passed in as well as bpf_jit_current under tcpdump BPF filter, +seccomp BPF and native (e)BPF programs, and the behavior all looks sane +and expected, that is nothing "leaking" from an upstream perspective. + +The bpf_jit_limit knob was originally added in order to avoid a situation +where unprivileged applications loading BPF programs (e.g. seccomp BPF +policies) consuming all the module memory space via BPF JIT such that loading +of kernel modules would be prevented. The default limit was defined back in +2018 and while good enough back then, we are generally seeing far more BPF +consumers today. + +Adjust the limit for the BPF JIT pool from originally 1/4 to now 1/2 of the +module memory space to better reflect today's needs and avoid more users +running into potentially hard to debug issues. + +Fixes: fdadd04931c2 ("bpf: fix bpf_jit_limit knob for PAGE_SIZE >= 64K") +Reported-by: Stephen Haynes +Reported-by: Lefteris Alexakis +Signed-off-by: Daniel Borkmann +Link: https://github.com/awslabs/amazon-eks-ami/issues/1179 +Link: https://github.com/awslabs/amazon-eks-ami/issues/1219 +Reviewed-by: Kuniyuki Iwashima +Link: https://lore.kernel.org/r/20230320143725.8394-1-daniel@iogearbox.net +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c +index 24e16538e4d71..285101772c755 100644 +--- a/kernel/bpf/core.c ++++ b/kernel/bpf/core.c +@@ -603,7 +603,7 @@ static int __init bpf_jit_charge_init(void) + { + /* Only used as heuristic here to derive limit. */ + bpf_jit_limit_max = bpf_jit_alloc_exec_limit(); +- bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 2, ++ bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 1, + PAGE_SIZE), LONG_MAX); + return 0; + } +-- +2.39.2 + diff --git a/queue-4.19/erspan-do-not-use-skb_mac_header-in-ndo_start_xmit.patch b/queue-4.19/erspan-do-not-use-skb_mac_header-in-ndo_start_xmit.patch new file mode 100644 index 00000000000..69bc918fa8c --- /dev/null +++ b/queue-4.19/erspan-do-not-use-skb_mac_header-in-ndo_start_xmit.patch @@ -0,0 +1,122 @@ +From 9d32bb6ab612d3de3a0f156f3147e3d43b9739d4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 16:34:27 +0000 +Subject: erspan: do not use skb_mac_header() in ndo_start_xmit() + +From: Eric Dumazet + +[ Upstream commit 8e50ed774554f93d55426039b27b1e38d7fa64d8 ] + +Drivers should not assume skb_mac_header(skb) == skb->data in their +ndo_start_xmit(). + +Use skb_network_offset() and skb_transport_offset() which +better describe what is needed in erspan_fb_xmit() and +ip6erspan_tunnel_xmit() + +syzbot reported: +WARNING: CPU: 0 PID: 5083 at include/linux/skbuff.h:2873 skb_mac_header include/linux/skbuff.h:2873 [inline] +WARNING: CPU: 0 PID: 5083 at include/linux/skbuff.h:2873 ip6erspan_tunnel_xmit+0x1d9c/0x2d90 net/ipv6/ip6_gre.c:962 +Modules linked in: +CPU: 0 PID: 5083 Comm: syz-executor406 Not tainted 6.3.0-rc2-syzkaller-00866-gd4671cb96fa3 #0 +Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/02/2023 +RIP: 0010:skb_mac_header include/linux/skbuff.h:2873 [inline] +RIP: 0010:ip6erspan_tunnel_xmit+0x1d9c/0x2d90 net/ipv6/ip6_gre.c:962 +Code: 04 02 41 01 de 84 c0 74 08 3c 03 0f 8e 1c 0a 00 00 45 89 b4 24 c8 00 00 00 c6 85 77 fe ff ff 01 e9 33 e7 ff ff e8 b4 27 a1 f8 <0f> 0b e9 b6 e7 ff ff e8 a8 27 a1 f8 49 8d bf f0 0c 00 00 48 b8 00 +RSP: 0018:ffffc90003b2f830 EFLAGS: 00010293 +RAX: 0000000000000000 RBX: 000000000000ffff RCX: 0000000000000000 +RDX: ffff888021273a80 RSI: ffffffff88e1bd4c RDI: 0000000000000003 +RBP: ffffc90003b2f9d8 R08: 0000000000000003 R09: 000000000000ffff +R10: 000000000000ffff R11: 0000000000000000 R12: ffff88802b28da00 +R13: 00000000000000d0 R14: ffff88807e25b6d0 R15: ffff888023408000 +FS: 0000555556a61300(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 +CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +CR2: 000055e5b11eb6e8 CR3: 0000000027c1b000 CR4: 00000000003506f0 +DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +Call Trace: + +__netdev_start_xmit include/linux/netdevice.h:4900 [inline] +netdev_start_xmit include/linux/netdevice.h:4914 [inline] +__dev_direct_xmit+0x504/0x730 net/core/dev.c:4300 +dev_direct_xmit include/linux/netdevice.h:3088 [inline] +packet_xmit+0x20a/0x390 net/packet/af_packet.c:285 +packet_snd net/packet/af_packet.c:3075 [inline] +packet_sendmsg+0x31a0/0x5150 net/packet/af_packet.c:3107 +sock_sendmsg_nosec net/socket.c:724 [inline] +sock_sendmsg+0xde/0x190 net/socket.c:747 +__sys_sendto+0x23a/0x340 net/socket.c:2142 +__do_sys_sendto net/socket.c:2154 [inline] +__se_sys_sendto net/socket.c:2150 [inline] +__x64_sys_sendto+0xe1/0x1b0 net/socket.c:2150 +do_syscall_x64 arch/x86/entry/common.c:50 [inline] +do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 +entry_SYSCALL_64_after_hwframe+0x63/0xcd +RIP: 0033:0x7f123aaa1039 +Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 b1 14 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 +RSP: 002b:00007ffc15d12058 EFLAGS: 00000246 ORIG_RAX: 000000000000002c +RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f123aaa1039 +RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000003 +RBP: 0000000000000000 R08: 0000000020000040 R09: 0000000000000014 +R10: 0000000000000000 R11: 0000000000000246 R12: 00007f123aa648c0 +R13: 431bde82d7b634db R14: 0000000000000000 R15: 0000000000000000 + +Fixes: 1baf5ebf8954 ("erspan: auto detect truncated packets.") +Reported-by: syzbot +Signed-off-by: Eric Dumazet +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/20230320163427.8096-1-edumazet@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + net/ipv4/ip_gre.c | 4 ++-- + net/ipv6/ip6_gre.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c +index c72432ce9bf50..898753328c171 100644 +--- a/net/ipv4/ip_gre.c ++++ b/net/ipv4/ip_gre.c +@@ -603,7 +603,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) + truncate = true; + } + +- nhoff = skb_network_header(skb) - skb_mac_header(skb); ++ nhoff = skb_network_offset(skb); + if (skb->protocol == htons(ETH_P_IP) && + (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) + truncate = true; +@@ -612,7 +612,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) + int thoff; + + if (skb_transport_header_was_set(skb)) +- thoff = skb_transport_header(skb) - skb_mac_header(skb); ++ thoff = skb_transport_offset(skb); + else + thoff = nhoff + sizeof(struct ipv6hdr); + if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) +diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c +index 00601bc4fdfa3..166b7544e54a4 100644 +--- a/net/ipv6/ip6_gre.c ++++ b/net/ipv6/ip6_gre.c +@@ -961,7 +961,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, + truncate = true; + } + +- nhoff = skb_network_header(skb) - skb_mac_header(skb); ++ nhoff = skb_network_offset(skb); + if (skb->protocol == htons(ETH_P_IP) && + (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) + truncate = true; +@@ -970,7 +970,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, + int thoff; + + if (skb_transport_header_was_set(skb)) +- thoff = skb_transport_header(skb) - skb_mac_header(skb); ++ thoff = skb_transport_offset(skb); + else + thoff = nhoff + sizeof(struct ipv6hdr); + if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) +-- +2.39.2 + diff --git a/queue-4.19/hvc-xen-prevent-concurrent-accesses-to-the-shared-ri.patch b/queue-4.19/hvc-xen-prevent-concurrent-accesses-to-the-shared-ri.patch new file mode 100644 index 00000000000..8ac6c9710f1 --- /dev/null +++ b/queue-4.19/hvc-xen-prevent-concurrent-accesses-to-the-shared-ri.patch @@ -0,0 +1,147 @@ +From 8b228db2ea4f5b93b22fa02256193dada090fab8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 30 Nov 2022 16:09:11 +0100 +Subject: hvc/xen: prevent concurrent accesses to the shared ring +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Roger Pau Monne + +[ Upstream commit 6214894f49a967c749ee6c07cb00f9cede748df4 ] + +The hvc machinery registers both a console and a tty device based on +the hv ops provided by the specific implementation. Those two +interfaces however have different locks, and there's no single locks +that's shared between the tty and the console implementations, hence +the driver needs to protect itself against concurrent accesses. +Otherwise concurrent calls using the split interfaces are likely to +corrupt the ring indexes, leaving the console unusable. + +Introduce a lock to xencons_info to serialize accesses to the shared +ring. This is only required when using the shared memory console, +concurrent accesses to the hypercall based console implementation are +not an issue. + +Note the conditional logic in domU_read_console() is slightly modified +so the notify_daemon() call can be done outside of the locked region: +it's an hypercall and there's no need for it to be done with the lock +held. + +Fixes: b536b4b96230 ('xen: use the hvc console infrastructure for Xen console') +Signed-off-by: Roger Pau Monné +Reviewed-by: Juergen Gross +Link: https://lore.kernel.org/r/20221130150919.13935-1-roger.pau@citrix.com +Signed-off-by: Juergen Gross +Signed-off-by: Sasha Levin +--- + drivers/tty/hvc/hvc_xen.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c +index 47ffb485ff34c..59d85bdd132bd 100644 +--- a/drivers/tty/hvc/hvc_xen.c ++++ b/drivers/tty/hvc/hvc_xen.c +@@ -43,6 +43,7 @@ struct xencons_info { + int irq; + int vtermno; + grant_ref_t gntref; ++ spinlock_t ring_lock; + }; + + static LIST_HEAD(xenconsoles); +@@ -89,12 +90,15 @@ static int __write_console(struct xencons_info *xencons, + XENCONS_RING_IDX cons, prod; + struct xencons_interface *intf = xencons->intf; + int sent = 0; ++ unsigned long flags; + ++ spin_lock_irqsave(&xencons->ring_lock, flags); + cons = intf->out_cons; + prod = intf->out_prod; + mb(); /* update queue values before going on */ + + if ((prod - cons) > sizeof(intf->out)) { ++ spin_unlock_irqrestore(&xencons->ring_lock, flags); + pr_err_once("xencons: Illegal ring page indices"); + return -EINVAL; + } +@@ -104,6 +108,7 @@ static int __write_console(struct xencons_info *xencons, + + wmb(); /* write ring before updating pointer */ + intf->out_prod = prod; ++ spin_unlock_irqrestore(&xencons->ring_lock, flags); + + if (sent) + notify_daemon(xencons); +@@ -146,16 +151,19 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) + int recv = 0; + struct xencons_info *xencons = vtermno_to_xencons(vtermno); + unsigned int eoiflag = 0; ++ unsigned long flags; + + if (xencons == NULL) + return -EINVAL; + intf = xencons->intf; + ++ spin_lock_irqsave(&xencons->ring_lock, flags); + cons = intf->in_cons; + prod = intf->in_prod; + mb(); /* get pointers before reading ring */ + + if ((prod - cons) > sizeof(intf->in)) { ++ spin_unlock_irqrestore(&xencons->ring_lock, flags); + pr_err_once("xencons: Illegal ring page indices"); + return -EINVAL; + } +@@ -179,10 +187,13 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) + xencons->out_cons = intf->out_cons; + xencons->out_cons_same = 0; + } ++ if (!recv && xencons->out_cons_same++ > 1) { ++ eoiflag = XEN_EOI_FLAG_SPURIOUS; ++ } ++ spin_unlock_irqrestore(&xencons->ring_lock, flags); ++ + if (recv) { + notify_daemon(xencons); +- } else if (xencons->out_cons_same++ > 1) { +- eoiflag = XEN_EOI_FLAG_SPURIOUS; + } + + xen_irq_lateeoi(xencons->irq, eoiflag); +@@ -239,6 +250,7 @@ static int xen_hvm_console_init(void) + info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); + if (!info) + return -ENOMEM; ++ spin_lock_init(&info->ring_lock); + } else if (info->intf != NULL) { + /* already configured */ + return 0; +@@ -275,6 +287,7 @@ static int xen_hvm_console_init(void) + + static int xencons_info_pv_init(struct xencons_info *info, int vtermno) + { ++ spin_lock_init(&info->ring_lock); + info->evtchn = xen_start_info->console.domU.evtchn; + /* GFN == MFN for PV guest */ + info->intf = gfn_to_virt(xen_start_info->console.domU.mfn); +@@ -325,6 +338,7 @@ static int xen_initial_domain_console_init(void) + info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); + if (!info) + return -ENOMEM; ++ spin_lock_init(&info->ring_lock); + } + + info->irq = bind_virq_to_irq(VIRQ_CONSOLE, 0, false); +@@ -482,6 +496,7 @@ static int xencons_probe(struct xenbus_device *dev, + info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); + if (!info) + return -ENOMEM; ++ spin_lock_init(&info->ring_lock); + dev_set_drvdata(&dev->dev, info); + info->xbdev = dev; + info->vtermno = xenbus_devid_to_vtermno(devid); +-- +2.39.2 + diff --git a/queue-4.19/i2c-imx-lpi2c-check-only-for-enabled-interrupt-flags.patch b/queue-4.19/i2c-imx-lpi2c-check-only-for-enabled-interrupt-flags.patch new file mode 100644 index 00000000000..365a0848fa0 --- /dev/null +++ b/queue-4.19/i2c-imx-lpi2c-check-only-for-enabled-interrupt-flags.patch @@ -0,0 +1,47 @@ +From 205d4fbd5a2d60677f7fe08b9a2d687982d7fbdb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Jan 2023 16:32:47 +0100 +Subject: i2c: imx-lpi2c: check only for enabled interrupt flags + +From: Alexander Stein + +[ Upstream commit 1c7885004567e8951d65a983be095f254dd20bef ] + +When reading from I2C, the Tx watermark is set to 0. Unfortunately the +TDF (transmit data flag) is enabled when Tx FIFO entries is equal or less +than watermark. So it is set in every case, hence the reset default of 1. +This results in the MSR_RDF _and_ MSR_TDF flags to be set thus trying +to send Tx data on a read message. +Mask the IRQ status to filter for wanted flags only. + +Fixes: a55fa9d0e42e ("i2c: imx-lpi2c: add low power i2c bus driver") +Signed-off-by: Alexander Stein +Tested-by: Emanuele Ghidoli +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-imx-lpi2c.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c +index 06c4c767af322..90c510d166516 100644 +--- a/drivers/i2c/busses/i2c-imx-lpi2c.c ++++ b/drivers/i2c/busses/i2c-imx-lpi2c.c +@@ -508,10 +508,14 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, + static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) + { + struct lpi2c_imx_struct *lpi2c_imx = dev_id; ++ unsigned int enabled; + unsigned int temp; + ++ enabled = readl(lpi2c_imx->base + LPI2C_MIER); ++ + lpi2c_imx_intctrl(lpi2c_imx, 0); + temp = readl(lpi2c_imx->base + LPI2C_MSR); ++ temp &= enabled; + + if (temp & MSR_RDF) + lpi2c_imx_read_rxfifo(lpi2c_imx); +-- +2.39.2 + diff --git a/queue-4.19/i40evf-change-a-vf-mac-without-reloading-the-vf-driv.patch b/queue-4.19/i40evf-change-a-vf-mac-without-reloading-the-vf-driv.patch new file mode 100644 index 00000000000..d9f304e8e63 --- /dev/null +++ b/queue-4.19/i40evf-change-a-vf-mac-without-reloading-the-vf-driv.patch @@ -0,0 +1,81 @@ +From 4d4db5f56cf61a79117444173603b2eec91fd0dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Aug 2018 08:12:26 -0700 +Subject: i40evf: Change a VF mac without reloading the VF driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Paweł Jabłoński + +[ Upstream commit ae1e29f671b467f3e9e9aa2b82ee40e4300ea810 ] + +Add possibility to change a VF mac address from host side +without reloading the VF driver on the guest side. Without +this patch it is not possible to change the VF mac because +executing i40evf_virtchnl_completion function with +VIRTCHNL_OP_GET_VF_RESOURCES opcode resets the VF mac +address to previous value. + +Signed-off-by: Paweł Jabłoński +Tested-by: Andrew Bowers +Signed-off-by: Jeff Kirsher +Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 8 +++++--- + drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c | 11 +++++++++-- + 2 files changed, 14 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +index 240083201dbf4..1527c67b487b2 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +@@ -2595,7 +2595,7 @@ static inline int i40e_check_vf_permission(struct i40e_vf *vf, + !is_multicast_ether_addr(addr) && vf->pf_set_mac && + !ether_addr_equal(addr, vf->default_lan_addr.addr)) { + dev_err(&pf->pdev->dev, +- "VF attempting to override administratively set MAC address, reload the VF driver to resume normal operation\n"); ++ "VF attempting to override administratively set MAC address, bring down and up the VF interface to resume normal operation\n"); + return -EPERM; + } + } +@@ -4019,9 +4019,11 @@ int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) + mac, vf_id); + } + +- /* Force the VF driver stop so it has to reload with new MAC address */ ++ /* Force the VF interface down so it has to bring up with new MAC ++ * address ++ */ + i40e_vc_disable_vf(vf); +- dev_info(&pf->pdev->dev, "Reload the VF driver to make this change effective.\n"); ++ dev_info(&pf->pdev->dev, "Bring down and up the VF interface to make this change effective.\n"); + + error_param: + return ret; +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c +index 94dabc9d89f73..6579dabab78cf 100644 +--- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c ++++ b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c +@@ -1362,8 +1362,15 @@ void i40evf_virtchnl_completion(struct i40evf_adapter *adapter, + memcpy(adapter->vf_res, msg, min(msglen, len)); + i40evf_validate_num_queues(adapter); + i40e_vf_parse_hw_config(&adapter->hw, adapter->vf_res); +- /* restore current mac address */ +- ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); ++ if (is_zero_ether_addr(adapter->hw.mac.addr)) { ++ /* restore current mac address */ ++ ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); ++ } else { ++ /* refresh current mac address if changed */ ++ ether_addr_copy(netdev->dev_addr, adapter->hw.mac.addr); ++ ether_addr_copy(netdev->perm_addr, ++ adapter->hw.mac.addr); ++ } + i40evf_process_config(adapter); + } + break; +-- +2.39.2 + diff --git a/queue-4.19/iavf-diet-and-reformat.patch b/queue-4.19/iavf-diet-and-reformat.patch new file mode 100644 index 00000000000..c14103d5c80 --- /dev/null +++ b/queue-4.19/iavf-diet-and-reformat.patch @@ -0,0 +1,4438 @@ +From 1d80041926d9a9fc1bb4faa7b712466d3d5960ae Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 14 Sep 2018 17:37:45 -0700 +Subject: iavf: diet and reformat + +From: Jesse Brandeburg + +[ Upstream commit ee61022acfffcd4468bc3c31f4fd61503f725999 ] + +Remove a bunch of unused code and reformat a few lines. Also +remove some now un-necessary files. + +Signed-off-by: Jesse Brandeburg +Tested-by: Andrew Bowers +Signed-off-by: Jeff Kirsher +Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/iavf/i40e_adminq.c | 27 - + .../net/ethernet/intel/iavf/i40e_adminq_cmd.h | 2277 +---------------- + drivers/net/ethernet/intel/iavf/i40e_common.c | 338 --- + drivers/net/ethernet/intel/iavf/i40e_hmc.h | 215 -- + .../net/ethernet/intel/iavf/i40e_lan_hmc.h | 158 -- + .../net/ethernet/intel/iavf/i40e_prototype.h | 65 +- + .../net/ethernet/intel/iavf/i40e_register.h | 245 -- + drivers/net/ethernet/intel/iavf/i40e_type.h | 783 +----- + 8 files changed, 50 insertions(+), 4058 deletions(-) + delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_hmc.h + delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h + +diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c +index 21a0dbf6ccf61..32e0e2d9cdc53 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_adminq.c ++++ b/drivers/net/ethernet/intel/iavf/i40e_adminq.c +@@ -7,16 +7,6 @@ + #include "i40e_adminq.h" + #include "i40e_prototype.h" + +-/** +- * i40e_is_nvm_update_op - return true if this is an NVM update operation +- * @desc: API request descriptor +- **/ +-static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) +-{ +- return (desc->opcode == i40e_aqc_opc_nvm_erase) || +- (desc->opcode == i40e_aqc_opc_nvm_update); +-} +- + /** + * i40e_adminq_init_regs - Initialize AdminQ registers + * @hw: pointer to the hardware structure +@@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw) + i40e_shutdown_asq(hw); + i40e_shutdown_arq(hw); + +- if (hw->nvm_buff.va) +- i40e_free_virt_mem(hw, &hw->nvm_buff); +- + return ret_code; + } + +@@ -951,17 +938,3 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, + + return ret_code; + } +- +-void i40evf_resume_aq(struct i40e_hw *hw) +-{ +- /* Registers are reset after PF reset */ +- hw->aq.asq.next_to_use = 0; +- hw->aq.asq.next_to_clean = 0; +- +- i40e_config_asq_regs(hw); +- +- hw->aq.arq.next_to_use = 0; +- hw->aq.arq.next_to_clean = 0; +- +- i40e_config_arq_regs(hw); +-} +diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h +index 5fd8529465d48..493bdc5331f7b 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h ++++ b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h +@@ -307,33 +307,6 @@ enum i40e_admin_queue_opc { + */ + #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) + +-/* internal (0x00XX) commands */ +- +-/* Get version (direct 0x0001) */ +-struct i40e_aqc_get_version { +- __le32 rom_ver; +- __le32 fw_build; +- __le16 fw_major; +- __le16 fw_minor; +- __le16 api_major; +- __le16 api_minor; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); +- +-/* Send driver version (indirect 0x0002) */ +-struct i40e_aqc_driver_version { +- u8 driver_major_ver; +- u8 driver_minor_ver; +- u8 driver_build_ver; +- u8 driver_subbuild_ver; +- u8 reserved[4]; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); +- + /* Queue Shutdown (direct 0x0003) */ + struct i40e_aqc_queue_shutdown { + __le32 driver_unloading; +@@ -343,490 +316,6 @@ struct i40e_aqc_queue_shutdown { + + I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); + +-/* Set PF context (0x0004, direct) */ +-struct i40e_aqc_set_pf_context { +- u8 pf_id; +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); +- +-/* Request resource ownership (direct 0x0008) +- * Release resource ownership (direct 0x0009) +- */ +-#define I40E_AQ_RESOURCE_NVM 1 +-#define I40E_AQ_RESOURCE_SDP 2 +-#define I40E_AQ_RESOURCE_ACCESS_READ 1 +-#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 +-#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 +-#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 +- +-struct i40e_aqc_request_resource { +- __le16 resource_id; +- __le16 access_type; +- __le32 timeout; +- __le32 resource_number; +- u8 reserved[4]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); +- +-/* Get function capabilities (indirect 0x000A) +- * Get device capabilities (indirect 0x000B) +- */ +-struct i40e_aqc_list_capabilites { +- u8 command_flags; +-#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 +- u8 pf_index; +- u8 reserved[2]; +- __le32 count; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); +- +-struct i40e_aqc_list_capabilities_element_resp { +- __le16 id; +- u8 major_rev; +- u8 minor_rev; +- __le32 number; +- __le32 logical_id; +- __le32 phys_id; +- u8 reserved[16]; +-}; +- +-/* list of caps */ +- +-#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 +-#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 +-#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 +-#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 +-#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 +-#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 +-#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 +-#define I40E_AQ_CAP_ID_SRIOV 0x0012 +-#define I40E_AQ_CAP_ID_VF 0x0013 +-#define I40E_AQ_CAP_ID_VMDQ 0x0014 +-#define I40E_AQ_CAP_ID_8021QBG 0x0015 +-#define I40E_AQ_CAP_ID_8021QBR 0x0016 +-#define I40E_AQ_CAP_ID_VSI 0x0017 +-#define I40E_AQ_CAP_ID_DCB 0x0018 +-#define I40E_AQ_CAP_ID_FCOE 0x0021 +-#define I40E_AQ_CAP_ID_ISCSI 0x0022 +-#define I40E_AQ_CAP_ID_RSS 0x0040 +-#define I40E_AQ_CAP_ID_RXQ 0x0041 +-#define I40E_AQ_CAP_ID_TXQ 0x0042 +-#define I40E_AQ_CAP_ID_MSIX 0x0043 +-#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 +-#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 +-#define I40E_AQ_CAP_ID_1588 0x0046 +-#define I40E_AQ_CAP_ID_IWARP 0x0051 +-#define I40E_AQ_CAP_ID_LED 0x0061 +-#define I40E_AQ_CAP_ID_SDP 0x0062 +-#define I40E_AQ_CAP_ID_MDIO 0x0063 +-#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 +-#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 +-#define I40E_AQ_CAP_ID_FLEX10 0x00F1 +-#define I40E_AQ_CAP_ID_CEM 0x00F2 +- +-/* Set CPPM Configuration (direct 0x0103) */ +-struct i40e_aqc_cppm_configuration { +- __le16 command_flags; +-#define I40E_AQ_CPPM_EN_LTRC 0x0800 +-#define I40E_AQ_CPPM_EN_DMCTH 0x1000 +-#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 +-#define I40E_AQ_CPPM_EN_HPTC 0x4000 +-#define I40E_AQ_CPPM_EN_DMARC 0x8000 +- __le16 ttlx; +- __le32 dmacr; +- __le16 dmcth; +- u8 hptc; +- u8 reserved; +- __le32 pfltrc; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); +- +-/* Set ARP Proxy command / response (indirect 0x0104) */ +-struct i40e_aqc_arp_proxy_data { +- __le16 command_flags; +-#define I40E_AQ_ARP_INIT_IPV4 0x0800 +-#define I40E_AQ_ARP_UNSUP_CTL 0x1000 +-#define I40E_AQ_ARP_ENA 0x2000 +-#define I40E_AQ_ARP_ADD_IPV4 0x4000 +-#define I40E_AQ_ARP_DEL_IPV4 0x8000 +- __le16 table_id; +- __le32 enabled_offloads; +-#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 +-#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 +- __le32 ip_addr; +- u8 mac_addr[6]; +- u8 reserved[2]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); +- +-/* Set NS Proxy Table Entry Command (indirect 0x0105) */ +-struct i40e_aqc_ns_proxy_data { +- __le16 table_idx_mac_addr_0; +- __le16 table_idx_mac_addr_1; +- __le16 table_idx_ipv6_0; +- __le16 table_idx_ipv6_1; +- __le16 control; +-#define I40E_AQ_NS_PROXY_ADD_0 0x0001 +-#define I40E_AQ_NS_PROXY_DEL_0 0x0002 +-#define I40E_AQ_NS_PROXY_ADD_1 0x0004 +-#define I40E_AQ_NS_PROXY_DEL_1 0x0008 +-#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 +-#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 +-#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 +-#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 +-#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 +-#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 +-#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 +-#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 +-#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 +- u8 mac_addr_0[6]; +- u8 mac_addr_1[6]; +- u8 local_mac_addr[6]; +- u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ +- u8 ipv6_addr_1[16]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); +- +-/* Manage LAA Command (0x0106) - obsolete */ +-struct i40e_aqc_mng_laa { +- __le16 command_flags; +-#define I40E_AQ_LAA_FLAG_WR 0x8000 +- u8 reserved[2]; +- __le32 sal; +- __le16 sah; +- u8 reserved2[6]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); +- +-/* Manage MAC Address Read Command (indirect 0x0107) */ +-struct i40e_aqc_mac_address_read { +- __le16 command_flags; +-#define I40E_AQC_LAN_ADDR_VALID 0x10 +-#define I40E_AQC_SAN_ADDR_VALID 0x20 +-#define I40E_AQC_PORT_ADDR_VALID 0x40 +-#define I40E_AQC_WOL_ADDR_VALID 0x80 +-#define I40E_AQC_MC_MAG_EN_VALID 0x100 +-#define I40E_AQC_ADDR_VALID_MASK 0x3F0 +- u8 reserved[6]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); +- +-struct i40e_aqc_mac_address_read_data { +- u8 pf_lan_mac[6]; +- u8 pf_san_mac[6]; +- u8 port_mac[6]; +- u8 pf_wol_mac[6]; +-}; +- +-I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); +- +-/* Manage MAC Address Write Command (0x0108) */ +-struct i40e_aqc_mac_address_write { +- __le16 command_flags; +-#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 +-#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 +-#define I40E_AQC_WRITE_TYPE_PORT 0x8000 +-#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 +-#define I40E_AQC_WRITE_TYPE_MASK 0xC000 +- +- __le16 mac_sah; +- __le32 mac_sal; +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); +- +-/* PXE commands (0x011x) */ +- +-/* Clear PXE Command and response (direct 0x0110) */ +-struct i40e_aqc_clear_pxe { +- u8 rx_cnt; +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); +- +-/* Set WoL Filter (0x0120) */ +- +-struct i40e_aqc_set_wol_filter { +- __le16 filter_index; +-#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 +-#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 +-#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ +- I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) +- +-#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 +-#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ +- I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) +- __le16 cmd_flags; +-#define I40E_AQC_SET_WOL_FILTER 0x8000 +-#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 +-#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 +-#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 +-#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 +- __le16 valid_flags; +-#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 +-#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 +- u8 reserved[2]; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); +- +-struct i40e_aqc_set_wol_filter_data { +- u8 filter[128]; +- u8 mask[16]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); +- +-/* Get Wake Reason (0x0121) */ +- +-struct i40e_aqc_get_wake_reason_completion { +- u8 reserved_1[2]; +- __le16 wake_reason; +-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 +-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ +- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) +-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 +-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ +- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) +- u8 reserved_2[12]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); +- +-/* Switch configuration commands (0x02xx) */ +- +-/* Used by many indirect commands that only pass an seid and a buffer in the +- * command +- */ +-struct i40e_aqc_switch_seid { +- __le16 seid; +- u8 reserved[6]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); +- +-/* Get Switch Configuration command (indirect 0x0200) +- * uses i40e_aqc_switch_seid for the descriptor +- */ +-struct i40e_aqc_get_switch_config_header_resp { +- __le16 num_reported; +- __le16 num_total; +- u8 reserved[12]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); +- +-struct i40e_aqc_switch_config_element_resp { +- u8 element_type; +-#define I40E_AQ_SW_ELEM_TYPE_MAC 1 +-#define I40E_AQ_SW_ELEM_TYPE_PF 2 +-#define I40E_AQ_SW_ELEM_TYPE_VF 3 +-#define I40E_AQ_SW_ELEM_TYPE_EMP 4 +-#define I40E_AQ_SW_ELEM_TYPE_BMC 5 +-#define I40E_AQ_SW_ELEM_TYPE_PV 16 +-#define I40E_AQ_SW_ELEM_TYPE_VEB 17 +-#define I40E_AQ_SW_ELEM_TYPE_PA 18 +-#define I40E_AQ_SW_ELEM_TYPE_VSI 19 +- u8 revision; +-#define I40E_AQ_SW_ELEM_REV_1 1 +- __le16 seid; +- __le16 uplink_seid; +- __le16 downlink_seid; +- u8 reserved[3]; +- u8 connection_type; +-#define I40E_AQ_CONN_TYPE_REGULAR 0x1 +-#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 +-#define I40E_AQ_CONN_TYPE_CASCADED 0x3 +- __le16 scheduler_id; +- __le16 element_info; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); +- +-/* Get Switch Configuration (indirect 0x0200) +- * an array of elements are returned in the response buffer +- * the first in the array is the header, remainder are elements +- */ +-struct i40e_aqc_get_switch_config_resp { +- struct i40e_aqc_get_switch_config_header_resp header; +- struct i40e_aqc_switch_config_element_resp element[1]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); +- +-/* Add Statistics (direct 0x0201) +- * Remove Statistics (direct 0x0202) +- */ +-struct i40e_aqc_add_remove_statistics { +- __le16 seid; +- __le16 vlan; +- __le16 stat_index; +- u8 reserved[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); +- +-/* Set Port Parameters command (direct 0x0203) */ +-struct i40e_aqc_set_port_parameters { +- __le16 command_flags; +-#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 +-#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ +-#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 +- __le16 bad_frame_vsi; +-#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 +-#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF +- __le16 default_seid; /* reserved for command */ +- u8 reserved[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); +- +-/* Get Switch Resource Allocation (indirect 0x0204) */ +-struct i40e_aqc_get_switch_resource_alloc { +- u8 num_entries; /* reserved for command */ +- u8 reserved[7]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); +- +-/* expect an array of these structs in the response buffer */ +-struct i40e_aqc_switch_resource_alloc_element_resp { +- u8 resource_type; +-#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 +-#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 +-#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 +-#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 +-#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 +-#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 +-#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 +-#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 +-#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 +-#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 +-#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA +-#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB +-#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC +-#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD +-#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF +-#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 +-#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 +-#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 +-#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 +- u8 reserved1; +- __le16 guaranteed; +- __le16 total; +- __le16 used; +- __le16 total_unalloced; +- u8 reserved2[6]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); +- +-/* Set Switch Configuration (direct 0x0205) */ +-struct i40e_aqc_set_switch_config { +- __le16 flags; +-/* flags used for both fields below */ +-#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 +-#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 +- __le16 valid_flags; +- /* The ethertype in switch_tag is dropped on ingress and used +- * internally by the switch. Set this to zero for the default +- * of 0x88a8 (802.1ad). Should be zero for firmware API +- * versions lower than 1.7. +- */ +- __le16 switch_tag; +- /* The ethertypes in first_tag and second_tag are used to +- * match the outer and inner VLAN tags (respectively) when HW +- * double VLAN tagging is enabled via the set port parameters +- * AQ command. Otherwise these are both ignored. Set them to +- * zero for their defaults of 0x8100 (802.1Q). Should be zero +- * for firmware API versions lower than 1.7. +- */ +- __le16 first_tag; +- __le16 second_tag; +- u8 reserved[6]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); +- +-/* Read Receive control registers (direct 0x0206) +- * Write Receive control registers (direct 0x0207) +- * used for accessing Rx control registers that can be +- * slow and need special handling when under high Rx load +- */ +-struct i40e_aqc_rx_ctl_reg_read_write { +- __le32 reserved1; +- __le32 address; +- __le32 reserved2; +- __le32 value; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); +- +-/* Add VSI (indirect 0x0210) +- * this indirect command uses struct i40e_aqc_vsi_properties_data +- * as the indirect buffer (128 bytes) +- * +- * Update VSI (indirect 0x211) +- * uses the same data structure as Add VSI +- * +- * Get VSI (indirect 0x0212) +- * uses the same completion and data structure as Add VSI +- */ +-struct i40e_aqc_add_get_update_vsi { +- __le16 uplink_seid; +- u8 connection_type; +-#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 +-#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 +-#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 +- u8 reserved1; +- u8 vf_id; +- u8 reserved2; +- __le16 vsi_flags; +-#define I40E_AQ_VSI_TYPE_SHIFT 0x0 +-#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) +-#define I40E_AQ_VSI_TYPE_VF 0x0 +-#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 +-#define I40E_AQ_VSI_TYPE_PF 0x2 +-#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 +-#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); +- +-struct i40e_aqc_add_get_update_vsi_completion { +- __le16 seid; +- __le16 vsi_number; +- __le16 vsi_used; +- __le16 vsi_free; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); +- + struct i40e_aqc_vsi_properties_data { + /* first 96 byte are written by SW */ + __le16 valid_sections; +@@ -952,87 +441,6 @@ struct i40e_aqc_vsi_properties_data { + + I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); + +-/* Add Port Virtualizer (direct 0x0220) +- * also used for update PV (direct 0x0221) but only flags are used +- * (IS_CTRL_PORT only works on add PV) +- */ +-struct i40e_aqc_add_update_pv { +- __le16 command_flags; +-#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 +-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 +-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 +-#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 +- __le16 uplink_seid; +- __le16 connected_seid; +- u8 reserved[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); +- +-struct i40e_aqc_add_update_pv_completion { +- /* reserved for update; for add also encodes error if rc == ENOSPC */ +- __le16 pv_seid; +-#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 +-#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 +-#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 +-#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); +- +-/* Get PV Params (direct 0x0222) +- * uses i40e_aqc_switch_seid for the descriptor +- */ +- +-struct i40e_aqc_get_pv_params_completion { +- __le16 seid; +- __le16 default_stag; +- __le16 pv_flags; /* same flags as add_pv */ +-#define I40E_AQC_GET_PV_PV_TYPE 0x1 +-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 +-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 +- u8 reserved[8]; +- __le16 default_port_seid; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); +- +-/* Add VEB (direct 0x0230) */ +-struct i40e_aqc_add_veb { +- __le16 uplink_seid; +- __le16 downlink_seid; +- __le16 veb_flags; +-#define I40E_AQC_ADD_VEB_FLOATING 0x1 +-#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 +-#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ +- I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) +-#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 +-#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 +-#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ +-#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 +- u8 enable_tcs; +- u8 reserved[9]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); +- +-struct i40e_aqc_add_veb_completion { +- u8 reserved[6]; +- __le16 switch_seid; +- /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ +- __le16 veb_seid; +-#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 +-#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 +-#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 +-#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 +- __le16 statistic_index; +- __le16 vebs_used; +- __le16 vebs_free; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); +- + /* Get VEB Parameters (direct 0x0232) + * uses i40e_aqc_switch_seid for the descriptor + */ +@@ -1048,1670 +456,73 @@ struct i40e_aqc_get_veb_parameters_completion { + + I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); + +-/* Delete Element (direct 0x0243) +- * uses the generic i40e_aqc_switch_seid +- */ +- +-/* Add MAC-VLAN (indirect 0x0250) */ +- +-/* used for the command for most vlan commands */ +-struct i40e_aqc_macvlan { +- __le16 num_addresses; +- __le16 seid[3]; +-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) +-#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); +- +-/* indirect data for command and response */ +-struct i40e_aqc_add_macvlan_element_data { +- u8 mac_addr[6]; +- __le16 vlan_tag; +- __le16 flags; +-#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 +-#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 +-#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 +-#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 +-#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 +- __le16 queue_number; +-#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 +-#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ +- I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) +- /* response section */ +- u8 match_method; +-#define I40E_AQC_MM_PERFECT_MATCH 0x01 +-#define I40E_AQC_MM_HASH_MATCH 0x02 +-#define I40E_AQC_MM_ERR_NO_RES 0xFF +- u8 reserved1[3]; +-}; +- +-struct i40e_aqc_add_remove_macvlan_completion { +- __le16 perfect_mac_used; +- __le16 perfect_mac_free; +- __le16 unicast_hash_free; +- __le16 multicast_hash_free; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); +- +-/* Remove MAC-VLAN (indirect 0x0251) +- * uses i40e_aqc_macvlan for the descriptor +- * data points to an array of num_addresses of elements +- */ ++#define I40E_LINK_SPEED_100MB_SHIFT 0x1 ++#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 ++#define I40E_LINK_SPEED_10GB_SHIFT 0x3 ++#define I40E_LINK_SPEED_40GB_SHIFT 0x4 ++#define I40E_LINK_SPEED_20GB_SHIFT 0x5 ++#define I40E_LINK_SPEED_25GB_SHIFT 0x6 + +-struct i40e_aqc_remove_macvlan_element_data { +- u8 mac_addr[6]; +- __le16 vlan_tag; +- u8 flags; +-#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 +-#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 +-#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 +-#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 +- u8 reserved[3]; +- /* reply section */ +- u8 error_code; +-#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 +-#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF +- u8 reply_reserved[3]; ++enum i40e_aq_link_speed { ++ I40E_LINK_SPEED_UNKNOWN = 0, ++ I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), ++ I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), ++ I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), ++ I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), ++ I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), ++ I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), + }; + +-/* Add VLAN (indirect 0x0252) +- * Remove VLAN (indirect 0x0253) +- * use the generic i40e_aqc_macvlan for the command ++/* Send to PF command (indirect 0x0801) id is only used by PF ++ * Send to VF command (indirect 0x0802) id is only used by PF ++ * Send to Peer PF command (indirect 0x0803) + */ +-struct i40e_aqc_add_remove_vlan_element_data { +- __le16 vlan_tag; +- u8 vlan_flags; +-/* flags for add VLAN */ +-#define I40E_AQC_ADD_VLAN_LOCAL 0x1 +-#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 +-#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) +-#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 +-#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 +-#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 +-#define I40E_AQC_VLAN_PTYPE_SHIFT 3 +-#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) +-#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 +-#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 +-#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 +-#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 +-/* flags for remove VLAN */ +-#define I40E_AQC_REMOVE_VLAN_ALL 0x1 +- u8 reserved; +- u8 result; +-/* flags for add VLAN */ +-#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 +-#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE +-#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF +-/* flags for remove VLAN */ +-#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 +-#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF +- u8 reserved1[3]; +-}; +- +-struct i40e_aqc_add_remove_vlan_completion { ++struct i40e_aqc_pf_vf_message { ++ __le32 id; + u8 reserved[4]; +- __le16 vlans_used; +- __le16 vlans_free; + __le32 addr_high; + __le32 addr_low; + }; + +-/* Set VSI Promiscuous Modes (direct 0x0254) */ +-struct i40e_aqc_set_vsi_promiscuous_modes { +- __le16 promiscuous_flags; +- __le16 valid_flags; +-/* flags used for both fields above */ +-#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 +-#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 +-#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 +-#define I40E_AQC_SET_VSI_DEFAULT 0x08 +-#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 +-#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 +- __le16 seid; +-#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF +- __le16 vlan_tag; +-#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF +-#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); +- +-/* Add S/E-tag command (direct 0x0255) +- * Uses generic i40e_aqc_add_remove_tag_completion for completion +- */ +-struct i40e_aqc_add_tag { +- __le16 flags; +-#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 +- __le16 seid; +-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) +- __le16 tag; +- __le16 queue_number; +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); +- +-struct i40e_aqc_add_remove_tag_completion { +- u8 reserved[12]; +- __le16 tags_used; +- __le16 tags_free; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); +- +-/* Remove S/E-tag command (direct 0x0256) +- * Uses generic i40e_aqc_add_remove_tag_completion for completion +- */ +-struct i40e_aqc_remove_tag { +- __le16 seid; +-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) +- __le16 tag; +- u8 reserved[12]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); +- +-/* Add multicast E-Tag (direct 0x0257) +- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields +- * and no external data +- */ +-struct i40e_aqc_add_remove_mcast_etag { +- __le16 pv_seid; +- __le16 etag; +- u8 num_unicast_etags; +- u8 reserved[3]; +- __le32 addr_high; /* address of array of 2-byte s-tags */ +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); ++I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); + +-struct i40e_aqc_add_remove_mcast_etag_completion { +- u8 reserved[4]; +- __le16 mcast_etags_used; +- __le16 mcast_etags_free; ++struct i40e_aqc_get_set_rss_key { ++#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) ++#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 ++#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ ++ I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) ++ __le16 vsi_id; ++ u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +- + }; + +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); ++I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); + +-/* Update S/E-Tag (direct 0x0259) */ +-struct i40e_aqc_update_tag { +- __le16 seid; +-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) +- __le16 old_tag; +- __le16 new_tag; +- u8 reserved[10]; ++struct i40e_aqc_get_set_rss_key_data { ++ u8 standard_rss_key[0x28]; ++ u8 extended_hash_key[0xc]; + }; + +-I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); +- +-struct i40e_aqc_update_tag_completion { +- u8 reserved[12]; +- __le16 tags_used; +- __le16 tags_free; +-}; ++I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); + +-I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); ++struct i40e_aqc_get_set_rss_lut { ++#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) ++#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 ++#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ ++ I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) ++ __le16 vsi_id; ++#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 ++#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ ++ BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) + +-/* Add Control Packet filter (direct 0x025A) +- * Remove Control Packet filter (direct 0x025B) +- * uses the i40e_aqc_add_oveb_cloud, +- * and the generic direct completion structure +- */ +-struct i40e_aqc_add_remove_control_packet_filter { +- u8 mac[6]; +- __le16 etype; ++#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 ++#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 + __le16 flags; +-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 +-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 +-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 +-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 +-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 +- __le16 seid; +-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) +- __le16 queue; +- u8 reserved[2]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); +- +-struct i40e_aqc_add_remove_control_packet_filter_completion { +- __le16 mac_etype_used; +- __le16 etype_used; +- __le16 mac_etype_free; +- __le16 etype_free; +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); +- +-/* Add Cloud filters (indirect 0x025C) +- * Remove Cloud filters (indirect 0x025D) +- * uses the i40e_aqc_add_remove_cloud_filters, +- * and the generic indirect completion structure +- */ +-struct i40e_aqc_add_remove_cloud_filters { +- u8 num_filters; +- u8 reserved; +- __le16 seid; +-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 +-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ +- I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) +- u8 big_buffer_flag; +-#define I40E_AQC_ADD_CLOUD_CMD_BB 1 +- u8 reserved2[3]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); +- +-struct i40e_aqc_cloud_filters_element_data { +- u8 outer_mac[6]; +- u8 inner_mac[6]; +- __le16 inner_vlan; +- union { +- struct { +- u8 reserved[12]; +- u8 data[4]; +- } v4; +- struct { +- u8 data[16]; +- } v6; +- struct { +- __le16 data[8]; +- } raw_v6; +- } ipaddr; +- __le16 flags; +-#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 +-#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ +- I40E_AQC_ADD_CLOUD_FILTER_SHIFT) +-/* 0x0000 reserved */ +-#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 +-/* 0x0002 reserved */ +-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 +-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 +-/* 0x0005 reserved */ +-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 +-/* 0x0007 reserved */ +-/* 0x0008 reserved */ +-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 +-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A +-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B +-#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C +-/* 0x0010 to 0x0017 is for custom filters */ +-#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ +-#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ +-#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ +- +-#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 +-#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 +-#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 +-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 +-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 +- +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 +-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 +- +-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 +-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 +-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 +- +- __le32 tenant_id; +- u8 reserved[4]; +- __le16 queue_number; +-#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 +-#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ +- I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) +- u8 reserved2[14]; +- /* response section */ +- u8 allocation_result; +-#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 +-#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF +- u8 response_reserved[7]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); +- +-/* i40e_aqc_cloud_filters_element_bb is used when +- * I40E_AQC_ADD_CLOUD_CMD_BB flag is set. +- */ +-struct i40e_aqc_cloud_filters_element_bb { +- struct i40e_aqc_cloud_filters_element_data element; +- u16 general_fields[32]; +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 +-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 +-}; +- +-I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); +- +-struct i40e_aqc_remove_cloud_filters_completion { +- __le16 perfect_ovlan_used; +- __le16 perfect_ovlan_free; +- __le16 vlan_used; +- __le16 vlan_free; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); +- +-/* Replace filter Command 0x025F +- * uses the i40e_aqc_replace_cloud_filters, +- * and the generic indirect completion structure +- */ +-struct i40e_filter_data { +- u8 filter_type; +- u8 input[3]; +-}; +- +-I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); +- +-struct i40e_aqc_replace_cloud_filters_cmd { +- u8 valid_flags; +-#define I40E_AQC_REPLACE_L1_FILTER 0x0 +-#define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 +-#define I40E_AQC_GET_CLOUD_FILTERS 0x2 +-#define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 +-#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 +- u8 old_filter_type; +- u8 new_filter_type; +- u8 tr_bit; +- u8 reserved[4]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); +- +-struct i40e_aqc_replace_cloud_filters_cmd_buf { +- u8 data[32]; +-/* Filter type INPUT codes*/ +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) +- +-/* Field Vector offsets */ +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 +-/* big FLU */ +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 +-/* big FLU */ +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 +- +-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 +- struct i40e_filter_data filters[8]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); +- +-/* Add Mirror Rule (indirect or direct 0x0260) +- * Delete Mirror Rule (indirect or direct 0x0261) +- * note: some rule types (4,5) do not use an external buffer. +- * take care to set the flags correctly. +- */ +-struct i40e_aqc_add_delete_mirror_rule { +- __le16 seid; +- __le16 rule_type; +-#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 +-#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ +- I40E_AQC_MIRROR_RULE_TYPE_SHIFT) +-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 +-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 +-#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 +-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 +-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 +- __le16 num_entries; +- __le16 destination; /* VSI for add, rule id for delete */ +- __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); +- +-struct i40e_aqc_add_delete_mirror_rule_completion { +- u8 reserved[2]; +- __le16 rule_id; /* only used on add */ +- __le16 mirror_rules_used; +- __le16 mirror_rules_free; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); +- +-/* Dynamic Device Personalization */ +-struct i40e_aqc_write_personalization_profile { +- u8 flags; +- u8 reserved[3]; +- __le32 profile_track_id; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); +- +-struct i40e_aqc_write_ddp_resp { +- __le32 error_offset; +- __le32 error_info; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-struct i40e_aqc_get_applied_profiles { +- u8 flags; +-#define I40E_AQC_GET_DDP_GET_CONF 0x1 +-#define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 +- u8 rsv[3]; +- __le32 reserved; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); +- +-/* DCB 0x03xx*/ +- +-/* PFC Ignore (direct 0x0301) +- * the command and response use the same descriptor structure +- */ +-struct i40e_aqc_pfc_ignore { +- u8 tc_bitmap; +- u8 command_flags; /* unused on response */ +-#define I40E_AQC_PFC_IGNORE_SET 0x80 +-#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); +- +-/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure +- * with no parameters +- */ +- +-/* TX scheduler 0x04xx */ +- +-/* Almost all the indirect commands use +- * this generic struct to pass the SEID in param0 +- */ +-struct i40e_aqc_tx_sched_ind { +- __le16 vsi_seid; +- u8 reserved[6]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); +- +-/* Several commands respond with a set of queue set handles */ +-struct i40e_aqc_qs_handles_resp { +- __le16 qs_handles[8]; +-}; +- +-/* Configure VSI BW limits (direct 0x0400) */ +-struct i40e_aqc_configure_vsi_bw_limit { +- __le16 vsi_seid; +- u8 reserved[2]; +- __le16 credit; +- u8 reserved1[2]; +- u8 max_credit; /* 0-3, limit = 2^max */ +- u8 reserved2[7]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); +- +-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) +- * responds with i40e_aqc_qs_handles_resp +- */ +-struct i40e_aqc_configure_vsi_ets_sla_bw_data { +- u8 tc_valid_bits; +- u8 reserved[15]; +- __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ +- +- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ +- __le16 tc_bw_max[2]; +- u8 reserved1[28]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); +- +-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) +- * responds with i40e_aqc_qs_handles_resp +- */ +-struct i40e_aqc_configure_vsi_tc_bw_data { +- u8 tc_valid_bits; +- u8 reserved[3]; +- u8 tc_bw_credits[8]; +- u8 reserved1[4]; +- __le16 qs_handles[8]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); +- +-/* Query vsi bw configuration (indirect 0x0408) */ +-struct i40e_aqc_query_vsi_bw_config_resp { +- u8 tc_valid_bits; +- u8 tc_suspended_bits; +- u8 reserved[14]; +- __le16 qs_handles[8]; +- u8 reserved1[4]; +- __le16 port_bw_limit; +- u8 reserved2[2]; +- u8 max_bw; /* 0-3, limit = 2^max */ +- u8 reserved3[23]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); +- +-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ +-struct i40e_aqc_query_vsi_ets_sla_config_resp { +- u8 tc_valid_bits; +- u8 reserved[3]; +- u8 share_credits[8]; +- __le16 credits[8]; +- +- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ +- __le16 tc_bw_max[2]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); +- +-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ +-struct i40e_aqc_configure_switching_comp_bw_limit { +- __le16 seid; +- u8 reserved[2]; +- __le16 credit; +- u8 reserved1[2]; +- u8 max_bw; /* 0-3, limit = 2^max */ +- u8 reserved2[7]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); +- +-/* Enable Physical Port ETS (indirect 0x0413) +- * Modify Physical Port ETS (indirect 0x0414) +- * Disable Physical Port ETS (indirect 0x0415) +- */ +-struct i40e_aqc_configure_switching_comp_ets_data { +- u8 reserved[4]; +- u8 tc_valid_bits; +- u8 seepage; +-#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 +- u8 tc_strict_priority_flags; +- u8 reserved1[17]; +- u8 tc_bw_share_credits[8]; +- u8 reserved2[96]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); +- +-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ +-struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { +- u8 tc_valid_bits; +- u8 reserved[15]; +- __le16 tc_bw_credit[8]; +- +- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ +- __le16 tc_bw_max[2]; +- u8 reserved1[28]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, +- i40e_aqc_configure_switching_comp_ets_bw_limit_data); +- +-/* Configure Switching Component Bandwidth Allocation per Tc +- * (indirect 0x0417) +- */ +-struct i40e_aqc_configure_switching_comp_bw_config_data { +- u8 tc_valid_bits; +- u8 reserved[2]; +- u8 absolute_credits; /* bool */ +- u8 tc_bw_share_credits[8]; +- u8 reserved1[20]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); +- +-/* Query Switching Component Configuration (indirect 0x0418) */ +-struct i40e_aqc_query_switching_comp_ets_config_resp { +- u8 tc_valid_bits; +- u8 reserved[35]; +- __le16 port_bw_limit; +- u8 reserved1[2]; +- u8 tc_bw_max; /* 0-3, limit = 2^max */ +- u8 reserved2[23]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); +- +-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ +-struct i40e_aqc_query_port_ets_config_resp { +- u8 reserved[4]; +- u8 tc_valid_bits; +- u8 reserved1; +- u8 tc_strict_priority_bits; +- u8 reserved2; +- u8 tc_bw_share_credits[8]; +- __le16 tc_bw_limits[8]; +- +- /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ +- __le16 tc_bw_max[2]; +- u8 reserved3[32]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); +- +-/* Query Switching Component Bandwidth Allocation per Traffic Type +- * (indirect 0x041A) +- */ +-struct i40e_aqc_query_switching_comp_bw_config_resp { +- u8 tc_valid_bits; +- u8 reserved[2]; +- u8 absolute_credits_enable; /* bool */ +- u8 tc_bw_share_credits[8]; +- __le16 tc_bw_limits[8]; +- +- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ +- __le16 tc_bw_max[2]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); +- +-/* Suspend/resume port TX traffic +- * (direct 0x041B and 0x041C) uses the generic SEID struct +- */ +- +-/* Configure partition BW +- * (indirect 0x041D) +- */ +-struct i40e_aqc_configure_partition_bw_data { +- __le16 pf_valid_bits; +- u8 min_bw[16]; /* guaranteed bandwidth */ +- u8 max_bw[16]; /* bandwidth limit */ +-}; +- +-I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); +- +-/* Get and set the active HMC resource profile and status. +- * (direct 0x0500) and (direct 0x0501) +- */ +-struct i40e_aq_get_set_hmc_resource_profile { +- u8 pm_profile; +- u8 pe_vf_enabled; +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); +- +-enum i40e_aq_hmc_profile { +- /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ +- I40E_HMC_PROFILE_DEFAULT = 1, +- I40E_HMC_PROFILE_FAVOR_VF = 2, +- I40E_HMC_PROFILE_EQUAL = 3, +-}; +- +-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ +- +-/* set in param0 for get phy abilities to report qualified modules */ +-#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 +-#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 +- +-enum i40e_aq_phy_type { +- I40E_PHY_TYPE_SGMII = 0x0, +- I40E_PHY_TYPE_1000BASE_KX = 0x1, +- I40E_PHY_TYPE_10GBASE_KX4 = 0x2, +- I40E_PHY_TYPE_10GBASE_KR = 0x3, +- I40E_PHY_TYPE_40GBASE_KR4 = 0x4, +- I40E_PHY_TYPE_XAUI = 0x5, +- I40E_PHY_TYPE_XFI = 0x6, +- I40E_PHY_TYPE_SFI = 0x7, +- I40E_PHY_TYPE_XLAUI = 0x8, +- I40E_PHY_TYPE_XLPPI = 0x9, +- I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, +- I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, +- I40E_PHY_TYPE_10GBASE_AOC = 0xC, +- I40E_PHY_TYPE_40GBASE_AOC = 0xD, +- I40E_PHY_TYPE_UNRECOGNIZED = 0xE, +- I40E_PHY_TYPE_UNSUPPORTED = 0xF, +- I40E_PHY_TYPE_100BASE_TX = 0x11, +- I40E_PHY_TYPE_1000BASE_T = 0x12, +- I40E_PHY_TYPE_10GBASE_T = 0x13, +- I40E_PHY_TYPE_10GBASE_SR = 0x14, +- I40E_PHY_TYPE_10GBASE_LR = 0x15, +- I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, +- I40E_PHY_TYPE_10GBASE_CR1 = 0x17, +- I40E_PHY_TYPE_40GBASE_CR4 = 0x18, +- I40E_PHY_TYPE_40GBASE_SR4 = 0x19, +- I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, +- I40E_PHY_TYPE_1000BASE_SX = 0x1B, +- I40E_PHY_TYPE_1000BASE_LX = 0x1C, +- I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, +- I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, +- I40E_PHY_TYPE_25GBASE_KR = 0x1F, +- I40E_PHY_TYPE_25GBASE_CR = 0x20, +- I40E_PHY_TYPE_25GBASE_SR = 0x21, +- I40E_PHY_TYPE_25GBASE_LR = 0x22, +- I40E_PHY_TYPE_25GBASE_AOC = 0x23, +- I40E_PHY_TYPE_25GBASE_ACC = 0x24, +- I40E_PHY_TYPE_MAX, +- I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, +- I40E_PHY_TYPE_EMPTY = 0xFE, +- I40E_PHY_TYPE_DEFAULT = 0xFF, +-}; +- +-#define I40E_LINK_SPEED_100MB_SHIFT 0x1 +-#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 +-#define I40E_LINK_SPEED_10GB_SHIFT 0x3 +-#define I40E_LINK_SPEED_40GB_SHIFT 0x4 +-#define I40E_LINK_SPEED_20GB_SHIFT 0x5 +-#define I40E_LINK_SPEED_25GB_SHIFT 0x6 +- +-enum i40e_aq_link_speed { +- I40E_LINK_SPEED_UNKNOWN = 0, +- I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), +- I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), +- I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), +- I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), +- I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), +- I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), +-}; +- +-struct i40e_aqc_module_desc { +- u8 oui[3]; +- u8 reserved1; +- u8 part_number[16]; +- u8 revision[4]; +- u8 reserved2[8]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); +- +-struct i40e_aq_get_phy_abilities_resp { +- __le32 phy_type; /* bitmap using the above enum for offsets */ +- u8 link_speed; /* bitmap using the above enum bit patterns */ +- u8 abilities; +-#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 +-#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 +-#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 +-#define I40E_AQ_PHY_LINK_ENABLED 0x08 +-#define I40E_AQ_PHY_AN_ENABLED 0x10 +-#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 +-#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 +-#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 +- __le16 eee_capability; +-#define I40E_AQ_EEE_100BASE_TX 0x0002 +-#define I40E_AQ_EEE_1000BASE_T 0x0004 +-#define I40E_AQ_EEE_10GBASE_T 0x0008 +-#define I40E_AQ_EEE_1000BASE_KX 0x0010 +-#define I40E_AQ_EEE_10GBASE_KX4 0x0020 +-#define I40E_AQ_EEE_10GBASE_KR 0x0040 +- __le32 eeer_val; +- u8 d3_lpan; +-#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 +- u8 phy_type_ext; +-#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 +-#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 +-#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 +-#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 +-#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 +-#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 +- u8 fec_cfg_curr_mod_ext_info; +-#define I40E_AQ_ENABLE_FEC_KR 0x01 +-#define I40E_AQ_ENABLE_FEC_RS 0x02 +-#define I40E_AQ_REQUEST_FEC_KR 0x04 +-#define I40E_AQ_REQUEST_FEC_RS 0x08 +-#define I40E_AQ_ENABLE_FEC_AUTO 0x10 +-#define I40E_AQ_FEC +-#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 +-#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 +- +- u8 ext_comp_code; +- u8 phy_id[4]; +- u8 module_type[3]; +- u8 qualified_module_count; +-#define I40E_AQ_PHY_MAX_QMS 16 +- struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); +- +-/* Set PHY Config (direct 0x0601) */ +-struct i40e_aq_set_phy_config { /* same bits as above in all */ +- __le32 phy_type; +- u8 link_speed; +- u8 abilities; +-/* bits 0-2 use the values from get_phy_abilities_resp */ +-#define I40E_AQ_PHY_ENABLE_LINK 0x08 +-#define I40E_AQ_PHY_ENABLE_AN 0x10 +-#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 +- __le16 eee_capability; +- __le32 eeer; +- u8 low_power_ctrl; +- u8 phy_type_ext; +-#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 +-#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 +-#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 +-#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 +- u8 fec_config; +-#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) +-#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) +-#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) +-#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) +-#define I40E_AQ_SET_FEC_AUTO BIT(4) +-#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 +-#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) +- u8 reserved; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); +- +-/* Set MAC Config command data structure (direct 0x0603) */ +-struct i40e_aq_set_mac_config { +- __le16 max_frame_size; +- u8 params; +-#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF +-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 +-#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 +- u8 tx_timer_priority; /* bitmap */ +- __le16 tx_timer_value; +- __le16 fc_refresh_threshold; +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); +- +-/* Restart Auto-Negotiation (direct 0x605) */ +-struct i40e_aqc_set_link_restart_an { +- u8 command; +-#define I40E_AQ_PHY_RESTART_AN 0x02 +-#define I40E_AQ_PHY_LINK_ENABLE 0x04 +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); +- +-/* Get Link Status cmd & response data structure (direct 0x0607) */ +-struct i40e_aqc_get_link_status { +- __le16 command_flags; /* only field set on command */ +-#define I40E_AQ_LSE_MASK 0x3 +-#define I40E_AQ_LSE_NOP 0x0 +-#define I40E_AQ_LSE_DISABLE 0x2 +-#define I40E_AQ_LSE_ENABLE 0x3 +-/* only response uses this flag */ +-#define I40E_AQ_LSE_IS_ENABLED 0x1 +- u8 phy_type; /* i40e_aq_phy_type */ +- u8 link_speed; /* i40e_aq_link_speed */ +- u8 link_info; +-#define I40E_AQ_LINK_UP 0x01 /* obsolete */ +-#define I40E_AQ_LINK_UP_FUNCTION 0x01 +-#define I40E_AQ_LINK_FAULT 0x02 +-#define I40E_AQ_LINK_FAULT_TX 0x04 +-#define I40E_AQ_LINK_FAULT_RX 0x08 +-#define I40E_AQ_LINK_FAULT_REMOTE 0x10 +-#define I40E_AQ_LINK_UP_PORT 0x20 +-#define I40E_AQ_MEDIA_AVAILABLE 0x40 +-#define I40E_AQ_SIGNAL_DETECT 0x80 +- u8 an_info; +-#define I40E_AQ_AN_COMPLETED 0x01 +-#define I40E_AQ_LP_AN_ABILITY 0x02 +-#define I40E_AQ_PD_FAULT 0x04 +-#define I40E_AQ_FEC_EN 0x08 +-#define I40E_AQ_PHY_LOW_POWER 0x10 +-#define I40E_AQ_LINK_PAUSE_TX 0x20 +-#define I40E_AQ_LINK_PAUSE_RX 0x40 +-#define I40E_AQ_QUALIFIED_MODULE 0x80 +- u8 ext_info; +-#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 +-#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 +-#define I40E_AQ_LINK_TX_SHIFT 0x02 +-#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) +-#define I40E_AQ_LINK_TX_ACTIVE 0x00 +-#define I40E_AQ_LINK_TX_DRAINED 0x01 +-#define I40E_AQ_LINK_TX_FLUSHED 0x03 +-#define I40E_AQ_LINK_FORCED_40G 0x10 +-/* 25G Error Codes */ +-#define I40E_AQ_25G_NO_ERR 0X00 +-#define I40E_AQ_25G_NOT_PRESENT 0X01 +-#define I40E_AQ_25G_NVM_CRC_ERR 0X02 +-#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 +-#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 +-#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 +- u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ +-/* Since firmware API 1.7 loopback field keeps power class info as well */ +-#define I40E_AQ_LOOPBACK_MASK 0x07 +-#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 +-#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) +- __le16 max_frame_size; +- u8 config; +-#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 +-#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 +-#define I40E_AQ_CONFIG_CRC_ENA 0x04 +-#define I40E_AQ_CONFIG_PACING_MASK 0x78 +- union { +- struct { +- u8 power_desc; +-#define I40E_AQ_LINK_POWER_CLASS_1 0x00 +-#define I40E_AQ_LINK_POWER_CLASS_2 0x01 +-#define I40E_AQ_LINK_POWER_CLASS_3 0x02 +-#define I40E_AQ_LINK_POWER_CLASS_4 0x03 +-#define I40E_AQ_PWR_CLASS_MASK 0x03 +- u8 reserved[4]; +- }; +- struct { +- u8 link_type[4]; +- u8 link_type_ext; +- }; +- }; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); +- +-/* Set event mask command (direct 0x613) */ +-struct i40e_aqc_set_phy_int_mask { +- u8 reserved[8]; +- __le16 event_mask; +-#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 +-#define I40E_AQ_EVENT_MEDIA_NA 0x0004 +-#define I40E_AQ_EVENT_LINK_FAULT 0x0008 +-#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 +-#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 +-#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 +-#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 +-#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 +-#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 +- u8 reserved1[6]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); +- +-/* Get Local AN advt register (direct 0x0614) +- * Set Local AN advt register (direct 0x0615) +- * Get Link Partner AN advt register (direct 0x0616) +- */ +-struct i40e_aqc_an_advt_reg { +- __le32 local_an_reg0; +- __le16 local_an_reg1; +- u8 reserved[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); +- +-/* Set Loopback mode (0x0618) */ +-struct i40e_aqc_set_lb_mode { +- __le16 lb_mode; +-#define I40E_AQ_LB_PHY_LOCAL 0x01 +-#define I40E_AQ_LB_PHY_REMOTE 0x02 +-#define I40E_AQ_LB_MAC_LOCAL 0x04 +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); +- +-/* Set PHY Debug command (0x0622) */ +-struct i40e_aqc_set_phy_debug { +- u8 command_flags; +-#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 +-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 +-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ +- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) +-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 +-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 +-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 +-#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); +- +-enum i40e_aq_phy_reg_type { +- I40E_AQC_PHY_REG_INTERNAL = 0x1, +- I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, +- I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 +-}; +- +-/* Run PHY Activity (0x0626) */ +-struct i40e_aqc_run_phy_activity { +- __le16 activity_id; +- u8 flags; +- u8 reserved1; +- __le32 control; +- __le32 data; +- u8 reserved2[4]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); +- +-/* Set PHY Register command (0x0628) */ +-/* Get PHY Register command (0x0629) */ +-struct i40e_aqc_phy_register_access { +- u8 phy_interface; +-#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 +-#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 +-#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 +- u8 dev_address; +- u8 reserved1[2]; +- __le32 reg_address; +- __le32 reg_value; +- u8 reserved2[4]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); +- +-/* NVM Read command (indirect 0x0701) +- * NVM Erase commands (direct 0x0702) +- * NVM Update commands (indirect 0x0703) +- */ +-struct i40e_aqc_nvm_update { +- u8 command_flags; +-#define I40E_AQ_NVM_LAST_CMD 0x01 +-#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 +-#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 +-#define I40E_AQ_NVM_FLASH_ONLY 0x80 +-#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 +-#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 +-#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 +-#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 +- u8 module_pointer; +- __le16 length; +- __le32 offset; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); +- +-/* NVM Config Read (indirect 0x0704) */ +-struct i40e_aqc_nvm_config_read { +- __le16 cmd_flags; +-#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 +-#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 +-#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 +- __le16 element_count; +- __le16 element_id; /* Feature/field ID */ +- __le16 element_id_msw; /* MSWord of field ID */ +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); +- +-/* NVM Config Write (indirect 0x0705) */ +-struct i40e_aqc_nvm_config_write { +- __le16 cmd_flags; +- __le16 element_count; +- u8 reserved[4]; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); +- +-/* Used for 0x0704 as well as for 0x0705 commands */ +-#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 +-#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ +- BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) +-#define I40E_AQ_ANVM_FEATURE 0 +-#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) +-struct i40e_aqc_nvm_config_data_feature { +- __le16 feature_id; +-#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 +-#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 +-#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 +- __le16 feature_options; +- __le16 feature_selection; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); +- +-struct i40e_aqc_nvm_config_data_immediate_field { +- __le32 field_id; +- __le32 field_value; +- __le16 field_options; +- __le16 reserved; +-}; +- +-I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); +- +-/* OEM Post Update (indirect 0x0720) +- * no command data struct used +- */ +- struct i40e_aqc_nvm_oem_post_update { +-#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 +- u8 sel_data; +- u8 reserved[7]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); +- +-struct i40e_aqc_nvm_oem_post_update_buffer { +- u8 str_len; +- u8 dev_addr; +- __le16 eeprom_addr; +- u8 data[36]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); +- +-/* Thermal Sensor (indirect 0x0721) +- * read or set thermal sensor configs and values +- * takes a sensor and command specific data buffer, not detailed here +- */ +-struct i40e_aqc_thermal_sensor { +- u8 sensor_action; +-#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 +-#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 +-#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 +- u8 reserved[7]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); +- +-/* Send to PF command (indirect 0x0801) id is only used by PF +- * Send to VF command (indirect 0x0802) id is only used by PF +- * Send to Peer PF command (indirect 0x0803) +- */ +-struct i40e_aqc_pf_vf_message { +- __le32 id; +- u8 reserved[4]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); +- +-/* Alternate structure */ +- +-/* Direct write (direct 0x0900) +- * Direct read (direct 0x0902) +- */ +-struct i40e_aqc_alternate_write { +- __le32 address0; +- __le32 data0; +- __le32 address1; +- __le32 data1; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); +- +-/* Indirect write (indirect 0x0901) +- * Indirect read (indirect 0x0903) +- */ +- +-struct i40e_aqc_alternate_ind_write { +- __le32 address; +- __le32 length; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); +- +-/* Done alternate write (direct 0x0904) +- * uses i40e_aq_desc +- */ +-struct i40e_aqc_alternate_write_done { +- __le16 cmd_flags; +-#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 +-#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 +-#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 +-#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); +- +-/* Set OEM mode (direct 0x0905) */ +-struct i40e_aqc_alternate_set_mode { +- __le32 mode; +-#define I40E_AQ_ALTERNATE_MODE_NONE 0 +-#define I40E_AQ_ALTERNATE_MODE_OEM 1 +- u8 reserved[12]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); +- +-/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ +- +-/* async events 0x10xx */ +- +-/* Lan Queue Overflow Event (direct, 0x1001) */ +-struct i40e_aqc_lan_overflow { +- __le32 prtdcb_rupto; +- __le32 otx_ctl; +- u8 reserved[8]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); +- +-/* Get LLDP MIB (indirect 0x0A00) */ +-struct i40e_aqc_lldp_get_mib { +- u8 type; +- u8 reserved1; +-#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 +-#define I40E_AQ_LLDP_MIB_LOCAL 0x0 +-#define I40E_AQ_LLDP_MIB_REMOTE 0x1 +-#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 +-#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC +-#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 +-#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 +-#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 +-#define I40E_AQ_LLDP_TX_SHIFT 0x4 +-#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) +-/* TX pause flags use I40E_AQ_LINK_TX_* above */ +- __le16 local_len; +- __le16 remote_len; +- u8 reserved2[2]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); +- +-/* Configure LLDP MIB Change Event (direct 0x0A01) +- * also used for the event (with type in the command field) +- */ +-struct i40e_aqc_lldp_update_mib { +- u8 command; +-#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 +-#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 +- u8 reserved[7]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); +- +-/* Add LLDP TLV (indirect 0x0A02) +- * Delete LLDP TLV (indirect 0x0A04) +- */ +-struct i40e_aqc_lldp_add_tlv { +- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ +- u8 reserved1[1]; +- __le16 len; +- u8 reserved2[4]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); +- +-/* Update LLDP TLV (indirect 0x0A03) */ +-struct i40e_aqc_lldp_update_tlv { +- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ +- u8 reserved; +- __le16 old_len; +- __le16 new_offset; +- __le16 new_len; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); +- +-/* Stop LLDP (direct 0x0A05) */ +-struct i40e_aqc_lldp_stop { +- u8 command; +-#define I40E_AQ_LLDP_AGENT_STOP 0x0 +-#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); +- +-/* Start LLDP (direct 0x0A06) */ +- +-struct i40e_aqc_lldp_start { +- u8 command; +-#define I40E_AQ_LLDP_AGENT_START 0x1 +- u8 reserved[15]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); +- +-/* Set DCB (direct 0x0303) */ +-struct i40e_aqc_set_dcb_parameters { +- u8 command; +-#define I40E_AQ_DCB_SET_AGENT 0x1 +-#define I40E_DCB_VALID 0x1 +- u8 valid_flags; +- u8 reserved[14]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); +- +-/* Apply MIB changes (0x0A07) +- * uses the generic struc as it contains no data +- */ +- +-/* Add Udp Tunnel command and completion (direct 0x0B00) */ +-struct i40e_aqc_add_udp_tunnel { +- __le16 udp_port; +- u8 reserved0[3]; +- u8 protocol_type; +-#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 +-#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 +-#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 +-#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 +- u8 reserved1[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); +- +-struct i40e_aqc_add_udp_tunnel_completion { +- __le16 udp_port; +- u8 filter_entry_index; +- u8 multiple_pfs; +-#define I40E_AQC_SINGLE_PF 0x0 +-#define I40E_AQC_MULTIPLE_PFS 0x1 +- u8 total_filters; +- u8 reserved[11]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); +- +-/* remove UDP Tunnel command (0x0B01) */ +-struct i40e_aqc_remove_udp_tunnel { +- u8 reserved[2]; +- u8 index; /* 0 to 15 */ +- u8 reserved2[13]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); +- +-struct i40e_aqc_del_udp_tunnel_completion { +- __le16 udp_port; +- u8 index; /* 0 to 15 */ +- u8 multiple_pfs; +- u8 total_filters_used; +- u8 reserved1[11]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); +- +-struct i40e_aqc_get_set_rss_key { +-#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) +-#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 +-#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ +- I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) +- __le16 vsi_id; +- u8 reserved[6]; +- __le32 addr_high; +- __le32 addr_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); +- +-struct i40e_aqc_get_set_rss_key_data { +- u8 standard_rss_key[0x28]; +- u8 extended_hash_key[0xc]; +-}; +- +-I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); +- +-struct i40e_aqc_get_set_rss_lut { +-#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) +-#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 +-#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ +- I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) +- __le16 vsi_id; +-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 +-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ +- BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) +- +-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 +-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 +- __le16 flags; +- u8 reserved[4]; ++ u8 reserved[4]; + __le32 addr_high; + __le32 addr_low; + }; + + I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); +- +-/* tunnel key structure 0x0B10 */ +- +-struct i40e_aqc_tunnel_key_structure_A0 { +- __le16 key1_off; +- __le16 key1_len; +- __le16 key2_off; +- __le16 key2_len; +- __le16 flags; +-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 +-/* response flags */ +-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 +-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 +-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 +- u8 resreved[6]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); +- +-struct i40e_aqc_tunnel_key_structure { +- u8 key1_off; +- u8 key2_off; +- u8 key1_len; /* 0 to 15 */ +- u8 key2_len; /* 0 to 15 */ +- u8 flags; +-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 +-/* response flags */ +-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 +-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 +-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 +- u8 network_key_index; +-#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 +-#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 +-#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 +-#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 +- u8 reserved[10]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); +- +-/* OEM mode commands (direct 0xFE0x) */ +-struct i40e_aqc_oem_param_change { +- __le32 param_type; +-#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 +-#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 +-#define I40E_AQ_OEM_PARAM_MAC 2 +- __le32 param_value1; +- __le16 param_value2; +- u8 reserved[6]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); +- +-struct i40e_aqc_oem_state_change { +- __le32 state; +-#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 +-#define I40E_AQ_OEM_STATE_LINK_UP 0x1 +- u8 reserved[12]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); +- +-/* Initialize OCSD (0xFE02, direct) */ +-struct i40e_aqc_opc_oem_ocsd_initialize { +- u8 type_status; +- u8 reserved1[3]; +- __le32 ocsd_memory_block_addr_high; +- __le32 ocsd_memory_block_addr_low; +- __le32 requested_update_interval; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); +- +-/* Initialize OCBB (0xFE03, direct) */ +-struct i40e_aqc_opc_oem_ocbb_initialize { +- u8 type_status; +- u8 reserved1[3]; +- __le32 ocbb_memory_block_addr_high; +- __le32 ocbb_memory_block_addr_low; +- u8 reserved2[4]; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); +- +-/* debug commands */ +- +-/* get device id (0xFF00) uses the generic structure */ +- +-/* set test more (0xFF01, internal) */ +- +-struct i40e_acq_set_test_mode { +- u8 mode; +-#define I40E_AQ_TEST_PARTIAL 0 +-#define I40E_AQ_TEST_FULL 1 +-#define I40E_AQ_TEST_NVM 2 +- u8 reserved[3]; +- u8 command; +-#define I40E_AQ_TEST_OPEN 0 +-#define I40E_AQ_TEST_CLOSE 1 +-#define I40E_AQ_TEST_INC 2 +- u8 reserved2[3]; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); +- +-/* Debug Read Register command (0xFF03) +- * Debug Write Register command (0xFF04) +- */ +-struct i40e_aqc_debug_reg_read_write { +- __le32 reserved; +- __le32 address; +- __le32 value_high; +- __le32 value_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); +- +-/* Scatter/gather Reg Read (indirect 0xFF05) +- * Scatter/gather Reg Write (indirect 0xFF06) +- */ +- +-/* i40e_aq_desc is used for the command */ +-struct i40e_aqc_debug_reg_sg_element_data { +- __le32 address; +- __le32 value; +-}; +- +-/* Debug Modify register (direct 0xFF07) */ +-struct i40e_aqc_debug_modify_reg { +- __le32 address; +- __le32 value; +- __le32 clear_mask; +- __le32 set_mask; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); +- +-/* dump internal data (0xFF08, indirect) */ +- +-#define I40E_AQ_CLUSTER_ID_AUX 0 +-#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 +-#define I40E_AQ_CLUSTER_ID_TXSCHED 2 +-#define I40E_AQ_CLUSTER_ID_HMC 3 +-#define I40E_AQ_CLUSTER_ID_MAC0 4 +-#define I40E_AQ_CLUSTER_ID_MAC1 5 +-#define I40E_AQ_CLUSTER_ID_MAC2 6 +-#define I40E_AQ_CLUSTER_ID_MAC3 7 +-#define I40E_AQ_CLUSTER_ID_DCB 8 +-#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 +-#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 +-#define I40E_AQ_CLUSTER_ID_ALTRAM 11 +- +-struct i40e_aqc_debug_dump_internals { +- u8 cluster_id; +- u8 table_id; +- __le16 data_size; +- __le32 idx; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); +- +-struct i40e_aqc_debug_modify_internals { +- u8 cluster_id; +- u8 cluster_specific_params[7]; +- __le32 address_high; +- __le32 address_low; +-}; +- +-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); +- + #endif /* _I40E_ADMINQ_CMD_H_ */ +diff --git a/drivers/net/ethernet/intel/iavf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c +index eea280ba411ee..f34091d96f490 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_common.c ++++ b/drivers/net/ethernet/intel/iavf/i40e_common.c +@@ -525,7 +525,6 @@ i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw, + return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); + } + +- + /* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the + * hardware to a bit-field that can be used by SW to more easily determine the + * packet type. +@@ -891,135 +890,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = { + I40E_PTT_UNUSED_ENTRY(255) + }; + +-/** +- * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register +- * @hw: pointer to the hw struct +- * @reg_addr: register address +- * @reg_val: ptr to register value +- * @cmd_details: pointer to command details structure or NULL +- * +- * Use the firmware to read the Rx control register, +- * especially useful if the Rx unit is under heavy pressure +- **/ +-i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, +- u32 reg_addr, u32 *reg_val, +- struct i40e_asq_cmd_details *cmd_details) +-{ +- struct i40e_aq_desc desc; +- struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = +- (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; +- i40e_status status; +- +- if (!reg_val) +- return I40E_ERR_PARAM; +- +- i40evf_fill_default_direct_cmd_desc(&desc, +- i40e_aqc_opc_rx_ctl_reg_read); +- +- cmd_resp->address = cpu_to_le32(reg_addr); +- +- status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); +- +- if (status == 0) +- *reg_val = le32_to_cpu(cmd_resp->value); +- +- return status; +-} +- +-/** +- * i40evf_read_rx_ctl - read from an Rx control register +- * @hw: pointer to the hw struct +- * @reg_addr: register address +- **/ +-u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) +-{ +- i40e_status status = 0; +- bool use_register; +- int retry = 5; +- u32 val = 0; +- +- use_register = (((hw->aq.api_maj_ver == 1) && +- (hw->aq.api_min_ver < 5)) || +- (hw->mac.type == I40E_MAC_X722)); +- if (!use_register) { +-do_retry: +- status = i40evf_aq_rx_ctl_read_register(hw, reg_addr, +- &val, NULL); +- if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { +- usleep_range(1000, 2000); +- retry--; +- goto do_retry; +- } +- } +- +- /* if the AQ access failed, try the old-fashioned way */ +- if (status || use_register) +- val = rd32(hw, reg_addr); +- +- return val; +-} +- +-/** +- * i40evf_aq_rx_ctl_write_register +- * @hw: pointer to the hw struct +- * @reg_addr: register address +- * @reg_val: register value +- * @cmd_details: pointer to command details structure or NULL +- * +- * Use the firmware to write to an Rx control register, +- * especially useful if the Rx unit is under heavy pressure +- **/ +-i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, +- u32 reg_addr, u32 reg_val, +- struct i40e_asq_cmd_details *cmd_details) +-{ +- struct i40e_aq_desc desc; +- struct i40e_aqc_rx_ctl_reg_read_write *cmd = +- (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; +- i40e_status status; +- +- i40evf_fill_default_direct_cmd_desc(&desc, +- i40e_aqc_opc_rx_ctl_reg_write); +- +- cmd->address = cpu_to_le32(reg_addr); +- cmd->value = cpu_to_le32(reg_val); +- +- status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); +- +- return status; +-} +- +-/** +- * i40evf_write_rx_ctl - write to an Rx control register +- * @hw: pointer to the hw struct +- * @reg_addr: register address +- * @reg_val: register value +- **/ +-void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) +-{ +- i40e_status status = 0; +- bool use_register; +- int retry = 5; +- +- use_register = (((hw->aq.api_maj_ver == 1) && +- (hw->aq.api_min_ver < 5)) || +- (hw->mac.type == I40E_MAC_X722)); +- if (!use_register) { +-do_retry: +- status = i40evf_aq_rx_ctl_write_register(hw, reg_addr, +- reg_val, NULL); +- if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { +- usleep_range(1000, 2000); +- retry--; +- goto do_retry; +- } +- } +- +- /* if the AQ access failed, try the old-fashioned way */ +- if (status || use_register) +- wr32(hw, reg_addr, reg_val); +-} +- + /** + * i40e_aq_send_msg_to_pf + * @hw: pointer to the hardware structure +@@ -1110,211 +980,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw) + return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, + 0, NULL, 0, NULL); + } +- +-/** +- * i40evf_aq_write_ddp - Write dynamic device personalization (ddp) +- * @hw: pointer to the hw struct +- * @buff: command buffer (size in bytes = buff_size) +- * @buff_size: buffer size in bytes +- * @track_id: package tracking id +- * @error_offset: returns error offset +- * @error_info: returns error information +- * @cmd_details: pointer to command details structure or NULL +- **/ +-enum +-i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, +- u16 buff_size, u32 track_id, +- u32 *error_offset, u32 *error_info, +- struct i40e_asq_cmd_details *cmd_details) +-{ +- struct i40e_aq_desc desc; +- struct i40e_aqc_write_personalization_profile *cmd = +- (struct i40e_aqc_write_personalization_profile *) +- &desc.params.raw; +- struct i40e_aqc_write_ddp_resp *resp; +- i40e_status status; +- +- i40evf_fill_default_direct_cmd_desc(&desc, +- i40e_aqc_opc_write_personalization_profile); +- +- desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); +- if (buff_size > I40E_AQ_LARGE_BUF) +- desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); +- +- desc.datalen = cpu_to_le16(buff_size); +- +- cmd->profile_track_id = cpu_to_le32(track_id); +- +- status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); +- if (!status) { +- resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; +- if (error_offset) +- *error_offset = le32_to_cpu(resp->error_offset); +- if (error_info) +- *error_info = le32_to_cpu(resp->error_info); +- } +- +- return status; +-} +- +-/** +- * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp) +- * @hw: pointer to the hw struct +- * @buff: command buffer (size in bytes = buff_size) +- * @buff_size: buffer size in bytes +- * @flags: AdminQ command flags +- * @cmd_details: pointer to command details structure or NULL +- **/ +-enum +-i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, +- u16 buff_size, u8 flags, +- struct i40e_asq_cmd_details *cmd_details) +-{ +- struct i40e_aq_desc desc; +- struct i40e_aqc_get_applied_profiles *cmd = +- (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; +- i40e_status status; +- +- i40evf_fill_default_direct_cmd_desc(&desc, +- i40e_aqc_opc_get_personalization_profile_list); +- +- desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); +- if (buff_size > I40E_AQ_LARGE_BUF) +- desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); +- desc.datalen = cpu_to_le16(buff_size); +- +- cmd->flags = flags; +- +- status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); +- +- return status; +-} +- +-/** +- * i40evf_find_segment_in_package +- * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) +- * @pkg_hdr: pointer to the package header to be searched +- * +- * This function searches a package file for a particular segment type. On +- * success it returns a pointer to the segment header, otherwise it will +- * return NULL. +- **/ +-struct i40e_generic_seg_header * +-i40evf_find_segment_in_package(u32 segment_type, +- struct i40e_package_header *pkg_hdr) +-{ +- struct i40e_generic_seg_header *segment; +- u32 i; +- +- /* Search all package segments for the requested segment type */ +- for (i = 0; i < pkg_hdr->segment_count; i++) { +- segment = +- (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + +- pkg_hdr->segment_offset[i]); +- +- if (segment->type == segment_type) +- return segment; +- } +- +- return NULL; +-} +- +-/** +- * i40evf_write_profile +- * @hw: pointer to the hardware structure +- * @profile: pointer to the profile segment of the package to be downloaded +- * @track_id: package tracking id +- * +- * Handles the download of a complete package. +- */ +-enum i40e_status_code +-i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, +- u32 track_id) +-{ +- i40e_status status = 0; +- struct i40e_section_table *sec_tbl; +- struct i40e_profile_section_header *sec = NULL; +- u32 dev_cnt; +- u32 vendor_dev_id; +- u32 *nvm; +- u32 section_size = 0; +- u32 offset = 0, info = 0; +- u32 i; +- +- dev_cnt = profile->device_table_count; +- +- for (i = 0; i < dev_cnt; i++) { +- vendor_dev_id = profile->device_table[i].vendor_dev_id; +- if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) +- if (hw->device_id == (vendor_dev_id & 0xFFFF)) +- break; +- } +- if (i == dev_cnt) { +- i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP"); +- return I40E_ERR_DEVICE_NOT_SUPPORTED; +- } +- +- nvm = (u32 *)&profile->device_table[dev_cnt]; +- sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; +- +- for (i = 0; i < sec_tbl->section_count; i++) { +- sec = (struct i40e_profile_section_header *)((u8 *)profile + +- sec_tbl->section_offset[i]); +- +- /* Skip 'AQ', 'note' and 'name' sections */ +- if (sec->section.type != SECTION_TYPE_MMIO) +- continue; +- +- section_size = sec->section.size + +- sizeof(struct i40e_profile_section_header); +- +- /* Write profile */ +- status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size, +- track_id, &offset, &info, NULL); +- if (status) { +- i40e_debug(hw, I40E_DEBUG_PACKAGE, +- "Failed to write profile: offset %d, info %d", +- offset, info); +- break; +- } +- } +- return status; +-} +- +-/** +- * i40evf_add_pinfo_to_list +- * @hw: pointer to the hardware structure +- * @profile: pointer to the profile segment of the package +- * @profile_info_sec: buffer for information section +- * @track_id: package tracking id +- * +- * Register a profile to the list of loaded profiles. +- */ +-enum i40e_status_code +-i40evf_add_pinfo_to_list(struct i40e_hw *hw, +- struct i40e_profile_segment *profile, +- u8 *profile_info_sec, u32 track_id) +-{ +- i40e_status status = 0; +- struct i40e_profile_section_header *sec = NULL; +- struct i40e_profile_info *pinfo; +- u32 offset = 0, info = 0; +- +- sec = (struct i40e_profile_section_header *)profile_info_sec; +- sec->tbl_size = 1; +- sec->data_end = sizeof(struct i40e_profile_section_header) + +- sizeof(struct i40e_profile_info); +- sec->section.type = SECTION_TYPE_INFO; +- sec->section.offset = sizeof(struct i40e_profile_section_header); +- sec->section.size = sizeof(struct i40e_profile_info); +- pinfo = (struct i40e_profile_info *)(profile_info_sec + +- sec->section.offset); +- pinfo->track_id = track_id; +- pinfo->version = profile->version; +- pinfo->op = I40E_DDP_ADD_TRACKID; +- memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); +- +- status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end, +- track_id, &offset, &info, NULL); +- return status; +-} +diff --git a/drivers/net/ethernet/intel/iavf/i40e_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_hmc.h +deleted file mode 100644 +index 1c78de838857b..0000000000000 +--- a/drivers/net/ethernet/intel/iavf/i40e_hmc.h ++++ /dev/null +@@ -1,215 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright(c) 2013 - 2018 Intel Corporation. */ +- +-#ifndef _I40E_HMC_H_ +-#define _I40E_HMC_H_ +- +-#define I40E_HMC_MAX_BP_COUNT 512 +- +-/* forward-declare the HW struct for the compiler */ +-struct i40e_hw; +- +-#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */ +-#define I40E_HMC_PD_CNT_IN_SD 512 +-#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */ +-#define I40E_HMC_PAGED_BP_SIZE 4096 +-#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096 +-#define I40E_FIRST_VF_FPM_ID 16 +- +-struct i40e_hmc_obj_info { +- u64 base; /* base addr in FPM */ +- u32 max_cnt; /* max count available for this hmc func */ +- u32 cnt; /* count of objects driver actually wants to create */ +- u64 size; /* size in bytes of one object */ +-}; +- +-enum i40e_sd_entry_type { +- I40E_SD_TYPE_INVALID = 0, +- I40E_SD_TYPE_PAGED = 1, +- I40E_SD_TYPE_DIRECT = 2 +-}; +- +-struct i40e_hmc_bp { +- enum i40e_sd_entry_type entry_type; +- struct i40e_dma_mem addr; /* populate to be used by hw */ +- u32 sd_pd_index; +- u32 ref_cnt; +-}; +- +-struct i40e_hmc_pd_entry { +- struct i40e_hmc_bp bp; +- u32 sd_index; +- bool rsrc_pg; +- bool valid; +-}; +- +-struct i40e_hmc_pd_table { +- struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */ +- struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */ +- struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */ +- +- u32 ref_cnt; +- u32 sd_index; +-}; +- +-struct i40e_hmc_sd_entry { +- enum i40e_sd_entry_type entry_type; +- bool valid; +- +- union { +- struct i40e_hmc_pd_table pd_table; +- struct i40e_hmc_bp bp; +- } u; +-}; +- +-struct i40e_hmc_sd_table { +- struct i40e_virt_mem addr; /* used to track sd_entry allocations */ +- u32 sd_cnt; +- u32 ref_cnt; +- struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */ +-}; +- +-struct i40e_hmc_info { +- u32 signature; +- /* equals to pci func num for PF and dynamically allocated for VFs */ +- u8 hmc_fn_id; +- u16 first_sd_index; /* index of the first available SD */ +- +- /* hmc objects */ +- struct i40e_hmc_obj_info *hmc_obj; +- struct i40e_virt_mem hmc_obj_virt_mem; +- struct i40e_hmc_sd_table sd_table; +-}; +- +-#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++) +-#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++) +-#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++) +- +-#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--) +-#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--) +-#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--) +- +-/** +- * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware +- * @hw: pointer to our hw struct +- * @pa: pointer to physical address +- * @sd_index: segment descriptor index +- * @type: if sd entry is direct or paged +- **/ +-#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \ +-{ \ +- u32 val1, val2, val3; \ +- val1 = (u32)(upper_32_bits(pa)); \ +- val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \ +- I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ +- ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ +- I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \ +- BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \ +- val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ +- wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \ +- wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ +- wr32((hw), I40E_PFHMC_SDCMD, val3); \ +-} +- +-/** +- * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware +- * @hw: pointer to our hw struct +- * @sd_index: segment descriptor index +- * @type: if sd entry is direct or paged +- **/ +-#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \ +-{ \ +- u32 val2, val3; \ +- val2 = (I40E_HMC_MAX_BP_COUNT << \ +- I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ +- ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ +- I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \ +- val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ +- wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \ +- wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ +- wr32((hw), I40E_PFHMC_SDCMD, val3); \ +-} +- +-/** +- * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware +- * @hw: pointer to our hw struct +- * @sd_idx: segment descriptor index +- * @pd_idx: page descriptor index +- **/ +-#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \ +- wr32((hw), I40E_PFHMC_PDINV, \ +- (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \ +- ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT))) +- +-/** +- * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit +- * @hmc_info: pointer to the HMC configuration information structure +- * @type: type of HMC resources we're searching +- * @index: starting index for the object +- * @cnt: number of objects we're trying to create +- * @sd_idx: pointer to return index of the segment descriptor in question +- * @sd_limit: pointer to return the maximum number of segment descriptors +- * +- * This function calculates the segment descriptor index and index limit +- * for the resource defined by i40e_hmc_rsrc_type. +- **/ +-#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\ +-{ \ +- u64 fpm_addr, fpm_limit; \ +- fpm_addr = (hmc_info)->hmc_obj[(type)].base + \ +- (hmc_info)->hmc_obj[(type)].size * (index); \ +- fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\ +- *(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \ +- *(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \ +- /* add one more to the limit to correct our range */ \ +- *(sd_limit) += 1; \ +-} +- +-/** +- * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit +- * @hmc_info: pointer to the HMC configuration information struct +- * @type: HMC resource type we're examining +- * @idx: starting index for the object +- * @cnt: number of objects we're trying to create +- * @pd_index: pointer to return page descriptor index +- * @pd_limit: pointer to return page descriptor index limit +- * +- * Calculates the page descriptor index and index limit for the resource +- * defined by i40e_hmc_rsrc_type. +- **/ +-#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\ +-{ \ +- u64 fpm_adr, fpm_limit; \ +- fpm_adr = (hmc_info)->hmc_obj[(type)].base + \ +- (hmc_info)->hmc_obj[(type)].size * (idx); \ +- fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \ +- *(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \ +- *(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \ +- /* add one more to the limit to correct our range */ \ +- *(pd_limit) += 1; \ +-} +-i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw, +- struct i40e_hmc_info *hmc_info, +- u32 sd_index, +- enum i40e_sd_entry_type type, +- u64 direct_mode_sz); +- +-i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw, +- struct i40e_hmc_info *hmc_info, +- u32 pd_index, +- struct i40e_dma_mem *rsrc_pg); +-i40e_status i40e_remove_pd_bp(struct i40e_hw *hw, +- struct i40e_hmc_info *hmc_info, +- u32 idx); +-i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info, +- u32 idx); +-i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw, +- struct i40e_hmc_info *hmc_info, +- u32 idx, bool is_pf); +-i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info, +- u32 idx); +-i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw, +- struct i40e_hmc_info *hmc_info, +- u32 idx, bool is_pf); +- +-#endif /* _I40E_HMC_H_ */ +diff --git a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h +deleted file mode 100644 +index 82b00f70a6320..0000000000000 +--- a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h ++++ /dev/null +@@ -1,158 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright(c) 2013 - 2018 Intel Corporation. */ +- +-#ifndef _I40E_LAN_HMC_H_ +-#define _I40E_LAN_HMC_H_ +- +-/* forward-declare the HW struct for the compiler */ +-struct i40e_hw; +- +-/* HMC element context information */ +- +-/* Rx queue context data +- * +- * The sizes of the variables may be larger than needed due to crossing byte +- * boundaries. If we do not have the width of the variable set to the correct +- * size then we could end up shifting bits off the top of the variable when the +- * variable is at the top of a byte and crosses over into the next byte. +- */ +-struct i40e_hmc_obj_rxq { +- u16 head; +- u16 cpuid; /* bigger than needed, see above for reason */ +- u64 base; +- u16 qlen; +-#define I40E_RXQ_CTX_DBUFF_SHIFT 7 +- u16 dbuff; /* bigger than needed, see above for reason */ +-#define I40E_RXQ_CTX_HBUFF_SHIFT 6 +- u16 hbuff; /* bigger than needed, see above for reason */ +- u8 dtype; +- u8 dsize; +- u8 crcstrip; +- u8 fc_ena; +- u8 l2tsel; +- u8 hsplit_0; +- u8 hsplit_1; +- u8 showiv; +- u32 rxmax; /* bigger than needed, see above for reason */ +- u8 tphrdesc_ena; +- u8 tphwdesc_ena; +- u8 tphdata_ena; +- u8 tphhead_ena; +- u16 lrxqthresh; /* bigger than needed, see above for reason */ +- u8 prefena; /* NOTE: normally must be set to 1 at init */ +-}; +- +-/* Tx queue context data +-* +-* The sizes of the variables may be larger than needed due to crossing byte +-* boundaries. If we do not have the width of the variable set to the correct +-* size then we could end up shifting bits off the top of the variable when the +-* variable is at the top of a byte and crosses over into the next byte. +-*/ +-struct i40e_hmc_obj_txq { +- u16 head; +- u8 new_context; +- u64 base; +- u8 fc_ena; +- u8 timesync_ena; +- u8 fd_ena; +- u8 alt_vlan_ena; +- u16 thead_wb; +- u8 cpuid; +- u8 head_wb_ena; +- u16 qlen; +- u8 tphrdesc_ena; +- u8 tphrpacket_ena; +- u8 tphwdesc_ena; +- u64 head_wb_addr; +- u32 crc; +- u16 rdylist; +- u8 rdylist_act; +-}; +- +-/* for hsplit_0 field of Rx HMC context */ +-enum i40e_hmc_obj_rx_hsplit_0 { +- I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0, +- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1, +- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2, +- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, +- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8, +-}; +- +-/* fcoe_cntx and fcoe_filt are for debugging purpose only */ +-struct i40e_hmc_obj_fcoe_cntx { +- u32 rsv[32]; +-}; +- +-struct i40e_hmc_obj_fcoe_filt { +- u32 rsv[8]; +-}; +- +-/* Context sizes for LAN objects */ +-enum i40e_hmc_lan_object_size { +- I40E_HMC_LAN_OBJ_SZ_8 = 0x3, +- I40E_HMC_LAN_OBJ_SZ_16 = 0x4, +- I40E_HMC_LAN_OBJ_SZ_32 = 0x5, +- I40E_HMC_LAN_OBJ_SZ_64 = 0x6, +- I40E_HMC_LAN_OBJ_SZ_128 = 0x7, +- I40E_HMC_LAN_OBJ_SZ_256 = 0x8, +- I40E_HMC_LAN_OBJ_SZ_512 = 0x9, +-}; +- +-#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512 +-#define I40E_HMC_OBJ_SIZE_TXQ 128 +-#define I40E_HMC_OBJ_SIZE_RXQ 32 +-#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128 +-#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64 +- +-enum i40e_hmc_lan_rsrc_type { +- I40E_HMC_LAN_FULL = 0, +- I40E_HMC_LAN_TX = 1, +- I40E_HMC_LAN_RX = 2, +- I40E_HMC_FCOE_CTX = 3, +- I40E_HMC_FCOE_FILT = 4, +- I40E_HMC_LAN_MAX = 5 +-}; +- +-enum i40e_hmc_model { +- I40E_HMC_MODEL_DIRECT_PREFERRED = 0, +- I40E_HMC_MODEL_DIRECT_ONLY = 1, +- I40E_HMC_MODEL_PAGED_ONLY = 2, +- I40E_HMC_MODEL_UNKNOWN, +-}; +- +-struct i40e_hmc_lan_create_obj_info { +- struct i40e_hmc_info *hmc_info; +- u32 rsrc_type; +- u32 start_idx; +- u32 count; +- enum i40e_sd_entry_type entry_type; +- u64 direct_mode_sz; +-}; +- +-struct i40e_hmc_lan_delete_obj_info { +- struct i40e_hmc_info *hmc_info; +- u32 rsrc_type; +- u32 start_idx; +- u32 count; +-}; +- +-i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num, +- u32 rxq_num, u32 fcoe_cntx_num, +- u32 fcoe_filt_num); +-i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw, +- enum i40e_hmc_model model); +-i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw); +- +-i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw, +- u16 queue); +-i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw, +- u16 queue, +- struct i40e_hmc_obj_txq *s); +-i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw, +- u16 queue); +-i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw, +- u16 queue, +- struct i40e_hmc_obj_rxq *s); +- +-#endif /* _I40E_LAN_HMC_H_ */ +diff --git a/drivers/net/ethernet/intel/iavf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h +index a358f4b9d5aa6..ef7f74489bfc0 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_prototype.h ++++ b/drivers/net/ethernet/intel/iavf/i40e_prototype.h +@@ -60,71 +60,12 @@ static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype) + return i40evf_ptype_lookup[ptype]; + } + +-/* prototype for functions used for SW locks */ +- + /* i40e_common for VF drivers*/ + void i40e_vf_parse_hw_config(struct i40e_hw *hw, + struct virtchnl_vf_resource *msg); + i40e_status i40e_vf_reset(struct i40e_hw *hw); + i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw, +- enum virtchnl_ops v_opcode, +- i40e_status v_retval, +- u8 *msg, u16 msglen, +- struct i40e_asq_cmd_details *cmd_details); +-i40e_status i40e_set_filter_control(struct i40e_hw *hw, +- struct i40e_filter_control_settings *settings); +-i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, +- u8 *mac_addr, u16 ethtype, u16 flags, +- u16 vsi_seid, u16 queue, bool is_add, +- struct i40e_control_filter_stats *stats, +- struct i40e_asq_cmd_details *cmd_details); +-void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, +- u16 vsi_seid); +-i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, +- u32 reg_addr, u32 *reg_val, +- struct i40e_asq_cmd_details *cmd_details); +-u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr); +-i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, +- u32 reg_addr, u32 reg_val, +- struct i40e_asq_cmd_details *cmd_details); +-void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val); +-i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, +- u8 phy_select, u8 dev_addr, +- u32 reg_addr, u32 reg_val, +- struct i40e_asq_cmd_details *cmd_details); +-i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, +- u8 phy_select, u8 dev_addr, +- u32 reg_addr, u32 *reg_val, +- struct i40e_asq_cmd_details *cmd_details); +- +-i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, +- u16 reg, u8 phy_addr, u16 *value); +-i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, +- u16 reg, u8 phy_addr, u16 value); +-i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg, +- u8 phy_addr, u16 *value); +-i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg, +- u8 phy_addr, u16 value); +-u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num); +-i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, +- u32 time, u32 interval); +-i40e_status i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, +- u16 buff_size, u32 track_id, +- u32 *error_offset, u32 *error_info, +- struct i40e_asq_cmd_details * +- cmd_details); +-i40e_status i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, +- u16 buff_size, u8 flags, +- struct i40e_asq_cmd_details * +- cmd_details); +-struct i40e_generic_seg_header * +-i40evf_find_segment_in_package(u32 segment_type, +- struct i40e_package_header *pkg_header); +-enum i40e_status_code +-i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg, +- u32 track_id); +-enum i40e_status_code +-i40evf_add_pinfo_to_list(struct i40e_hw *hw, +- struct i40e_profile_segment *profile, +- u8 *profile_info_sec, u32 track_id); ++ enum virtchnl_ops v_opcode, ++ i40e_status v_retval, u8 *msg, u16 msglen, ++ struct i40e_asq_cmd_details *cmd_details); + #endif /* _I40E_PROTOTYPE_H_ */ +diff --git a/drivers/net/ethernet/intel/iavf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h +index 49e1f57d99cc6..20b464ac15420 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_register.h ++++ b/drivers/net/ethernet/intel/iavf/i40e_register.h +@@ -4,40 +4,12 @@ + #ifndef _I40E_REGISTER_H_ + #define _I40E_REGISTER_H_ + +-#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_PBA1_MAX_INDEX 19 +-#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 +-#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) +-#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TADD1_MAX_INDEX 639 +-#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 +-#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) +-#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 +-#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) +-#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 +-#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 +-#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) +-#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 +-#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 +-#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) +-#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 +-#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 +-#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) + #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ +-#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 +-#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) + #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ +-#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 +-#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) + #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ + #define I40E_VF_ARQH1_ARQH_SHIFT 0 + #define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) + #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ +-#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 +-#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) + #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 + #define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) + #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 +@@ -47,20 +19,10 @@ + #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 + #define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) + #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ +-#define I40E_VF_ARQT1_ARQT_SHIFT 0 +-#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) + #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ +-#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 +-#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) + #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ +-#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 +-#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) + #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ +-#define I40E_VF_ATQH1_ATQH_SHIFT 0 +-#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) + #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ +-#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 +-#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) + #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 + #define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) + #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 +@@ -70,244 +32,37 @@ + #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 + #define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) + #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ +-#define I40E_VF_ATQT1_ATQT_SHIFT 0 +-#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) + #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ + #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 + #define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) + #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ + #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 + #define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) +-#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 +-#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) +-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 +-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) + #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 + #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) +-#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 +-#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) +-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 +-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) +-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 +-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) +-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 +-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) + #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ +-#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 + #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 + #define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) +-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 +-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) + #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 + #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) + #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 + #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) + #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 +-#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) + #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 + #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) +-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 +-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) +-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 +-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) + #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ +-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 +-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) + #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 + #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) + #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 +-#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) + #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ +-#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 +-#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) +-#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 +-#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) +-#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 +-#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) +-#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 +-#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) +-#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 +-#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) +-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 +-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) +-#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 +-#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) +-#define I40E_VFINT_ICR01_SWINT_SHIFT 31 +-#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) +-#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ +-#define I40E_VFINT_ITR01_MAX_INDEX 2 +-#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 +-#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) + #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ +-#define I40E_VFINT_ITRN1_MAX_INDEX 2 +-#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 +-#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) +-#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ +-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 +-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) + #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ +-#define I40E_QRX_TAIL1_MAX_INDEX 15 +-#define I40E_QRX_TAIL1_TAIL_SHIFT 0 +-#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) + #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ +-#define I40E_QTX_TAIL1_MAX_INDEX 15 +-#define I40E_QTX_TAIL1_TAIL_SHIFT 0 +-#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) +-#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ +-#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 +-#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) +-#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TADD_MAX_INDEX 16 +-#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 +-#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) +-#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 +-#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) +-#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TMSG_MAX_INDEX 16 +-#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 +-#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) +-#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TUADD_MAX_INDEX 16 +-#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 +-#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) +-#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ +-#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 +-#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 +-#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) +-#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ +-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 +-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) +-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 +-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) +-#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 +-#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) +-#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ +-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 +-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) +-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 +-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) +-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 +-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) +-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 +-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) +-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 +-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) + #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ +-#define I40E_VFQF_HENA_MAX_INDEX 1 +-#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 +-#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) + #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ + #define I40E_VFQF_HKEY_MAX_INDEX 12 +-#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 +-#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) +-#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 +-#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) +-#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 +-#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) +-#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 +-#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) + #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ + #define I40E_VFQF_HLUT_MAX_INDEX 15 +-#define I40E_VFQF_HLUT_LUT0_SHIFT 0 +-#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) +-#define I40E_VFQF_HLUT_LUT1_SHIFT 8 +-#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) +-#define I40E_VFQF_HLUT_LUT2_SHIFT 16 +-#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) +-#define I40E_VFQF_HLUT_LUT3_SHIFT 24 +-#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) +-#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ +-#define I40E_VFQF_HREGION_MAX_INDEX 7 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) +-#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 +-#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) +-#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 +-#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) +-#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 +-#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) +-#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 +-#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) +-#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 +-#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) +-#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 +-#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) +-#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 +-#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 +-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) +-#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 +-#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) +-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 +-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) + #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 + #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) +-#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ +-#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 +-#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) +-#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ +-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 +-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) +-#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ +-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 +-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) +-#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ +-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 +-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) +-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 +-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) +-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 +-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) +-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 +-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) +-#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ +-#define I40E_VFPE_CQACK1_PECQID_SHIFT 0 +-#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) +-#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ +-#define I40E_VFPE_CQARM1_PECQID_SHIFT 0 +-#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) +-#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ +-#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 +-#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) +-#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ +-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 +-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) +-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 +-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) +-#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ +-#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 +-#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) +-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 +-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) +-#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ +-#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 +-#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) +-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 +-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) +-#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ +-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 +-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) +-#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ +-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 +-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) +-#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ +-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 +-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) +-#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ +-#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 +-#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) +-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 +-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) + #endif /* _I40E_REGISTER_H_ */ +diff --git a/drivers/net/ethernet/intel/iavf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h +index 094387db3c110..8f1344094bc93 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_type.h ++++ b/drivers/net/ethernet/intel/iavf/i40e_type.h +@@ -8,26 +8,16 @@ + #include "i40e_osdep.h" + #include "i40e_register.h" + #include "i40e_adminq.h" +-#include "i40e_hmc.h" +-#include "i40e_lan_hmc.h" + #include "i40e_devids.h" + ++#define I40E_RXQ_CTX_DBUFF_SHIFT 7 ++ + /* I40E_MASK is a macro used on 32 bit registers */ + #define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) + + #define I40E_MAX_VSI_QP 16 + #define I40E_MAX_VF_VSI 3 + #define I40E_MAX_CHAINED_RX_BUFFERS 5 +-#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 +- +-/* Max default timeout in ms, */ +-#define I40E_MAX_NVM_TIMEOUT 18000 +- +-/* Max timeout in ms for the phy to respond */ +-#define I40E_MAX_PHY_TIMEOUT 500 +- +-/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ +-#define I40E_MS_TO_GTIME(time) ((time) * 1000) + + /* forward declaration */ + struct i40e_hw; +@@ -88,33 +78,6 @@ enum i40e_mac_type { + I40E_MAC_GENERIC, + }; + +-enum i40e_media_type { +- I40E_MEDIA_TYPE_UNKNOWN = 0, +- I40E_MEDIA_TYPE_FIBER, +- I40E_MEDIA_TYPE_BASET, +- I40E_MEDIA_TYPE_BACKPLANE, +- I40E_MEDIA_TYPE_CX4, +- I40E_MEDIA_TYPE_DA, +- I40E_MEDIA_TYPE_VIRTUAL +-}; +- +-enum i40e_fc_mode { +- I40E_FC_NONE = 0, +- I40E_FC_RX_PAUSE, +- I40E_FC_TX_PAUSE, +- I40E_FC_FULL, +- I40E_FC_PFC, +- I40E_FC_DEFAULT +-}; +- +-enum i40e_set_fc_aq_failures { +- I40E_SET_FC_AQ_FAIL_NONE = 0, +- I40E_SET_FC_AQ_FAIL_GET = 1, +- I40E_SET_FC_AQ_FAIL_SET = 2, +- I40E_SET_FC_AQ_FAIL_UPDATE = 4, +- I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 +-}; +- + enum i40e_vsi_type { + I40E_VSI_MAIN = 0, + I40E_VSI_VMDQ1 = 1, +@@ -134,162 +97,16 @@ enum i40e_queue_type { + I40E_QUEUE_TYPE_UNKNOWN + }; + +-struct i40e_link_status { +- enum i40e_aq_phy_type phy_type; +- enum i40e_aq_link_speed link_speed; +- u8 link_info; +- u8 an_info; +- u8 req_fec_info; +- u8 fec_info; +- u8 ext_info; +- u8 loopback; +- /* is Link Status Event notification to SW enabled */ +- bool lse_enable; +- u16 max_frame_size; +- bool crc_enable; +- u8 pacing; +- u8 requested_speeds; +- u8 module_type[3]; +- /* 1st byte: module identifier */ +-#define I40E_MODULE_TYPE_SFP 0x03 +-#define I40E_MODULE_TYPE_QSFP 0x0D +- /* 2nd byte: ethernet compliance codes for 10/40G */ +-#define I40E_MODULE_TYPE_40G_ACTIVE 0x01 +-#define I40E_MODULE_TYPE_40G_LR4 0x02 +-#define I40E_MODULE_TYPE_40G_SR4 0x04 +-#define I40E_MODULE_TYPE_40G_CR4 0x08 +-#define I40E_MODULE_TYPE_10G_BASE_SR 0x10 +-#define I40E_MODULE_TYPE_10G_BASE_LR 0x20 +-#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 +-#define I40E_MODULE_TYPE_10G_BASE_ER 0x80 +- /* 3rd byte: ethernet compliance codes for 1G */ +-#define I40E_MODULE_TYPE_1000BASE_SX 0x01 +-#define I40E_MODULE_TYPE_1000BASE_LX 0x02 +-#define I40E_MODULE_TYPE_1000BASE_CX 0x04 +-#define I40E_MODULE_TYPE_1000BASE_T 0x08 +-}; +- +-struct i40e_phy_info { +- struct i40e_link_status link_info; +- struct i40e_link_status link_info_old; +- bool get_link_info; +- enum i40e_media_type media_type; +- /* all the phy types the NVM is capable of */ +- u64 phy_types; +-}; +- +-#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) +-#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) +-#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) +-#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) +-#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) +-#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) +-#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) +-#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) +-#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) +-#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) +-#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) +-#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) +-#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) +-#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) +-#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) +-#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) +-#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) +-#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) +-#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) +-#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) +-#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) +-#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) +-#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) +-#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) +-#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) +-#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) +-#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ +- BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) +-#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) +-/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some +- * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit +- * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, +- * a shift is needed to adjust for this with values larger than 31. The +- * only affected values are I40E_PHY_TYPE_25GBASE_*. +- */ +-#define I40E_PHY_TYPE_OFFSET 1 +-#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ +- I40E_PHY_TYPE_OFFSET) +-#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ +- I40E_PHY_TYPE_OFFSET) +-#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ +- I40E_PHY_TYPE_OFFSET) +-#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ +- I40E_PHY_TYPE_OFFSET) +-#define I40E_HW_CAP_MAX_GPIO 30 ++#define I40E_HW_CAP_MAX_GPIO 30 + /* Capabilities of a PF or a VF or the whole device */ + struct i40e_hw_capabilities { +- u32 switch_mode; +-#define I40E_NVM_IMAGE_TYPE_EVB 0x0 +-#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 +-#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 +- +- u32 management_mode; +- u32 mng_protocols_over_mctp; +-#define I40E_MNG_PROTOCOL_PLDM 0x2 +-#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 +-#define I40E_MNG_PROTOCOL_NCSI 0x8 +- u32 npar_enable; +- u32 os2bmc; +- u32 valid_functions; +- bool sr_iov_1_1; +- bool vmdq; +- bool evb_802_1_qbg; /* Edge Virtual Bridging */ +- bool evb_802_1_qbh; /* Bridge Port Extension */ + bool dcb; + bool fcoe; +- bool iscsi; /* Indicates iSCSI enabled */ +- bool flex10_enable; +- bool flex10_capable; +- u32 flex10_mode; +-#define I40E_FLEX10_MODE_UNKNOWN 0x0 +-#define I40E_FLEX10_MODE_DCC 0x1 +-#define I40E_FLEX10_MODE_DCI 0x2 +- +- u32 flex10_status; +-#define I40E_FLEX10_STATUS_DCC_ERROR 0x1 +-#define I40E_FLEX10_STATUS_VC_MODE 0x2 +- +- bool sec_rev_disabled; +- bool update_disabled; +-#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 +-#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 +- +- bool mgmt_cem; +- bool ieee_1588; +- bool iwarp; +- bool fd; +- u32 fd_filters_guaranteed; +- u32 fd_filters_best_effort; +- bool rss; +- u32 rss_table_size; +- u32 rss_table_entry_width; +- bool led[I40E_HW_CAP_MAX_GPIO]; +- bool sdp[I40E_HW_CAP_MAX_GPIO]; +- u32 nvm_image_type; +- u32 num_flow_director_filters; +- u32 num_vfs; +- u32 vf_base_id; + u32 num_vsis; + u32 num_rx_qp; + u32 num_tx_qp; + u32 base_queue; +- u32 num_msix_vectors; + u32 num_msix_vectors_vf; +- u32 led_pin_num; +- u32 sdp_pin_num; +- u32 mdio_port_num; +- u32 mdio_port_mode; +- u8 rx_buf_chain_len; +- u32 enabled_tcmap; +- u32 maxtc; +- u64 wr_csr_prot; + }; + + struct i40e_mac_info { +@@ -300,106 +117,6 @@ struct i40e_mac_info { + u16 max_fcoeq; + }; + +-enum i40e_aq_resources_ids { +- I40E_NVM_RESOURCE_ID = 1 +-}; +- +-enum i40e_aq_resource_access_type { +- I40E_RESOURCE_READ = 1, +- I40E_RESOURCE_WRITE +-}; +- +-struct i40e_nvm_info { +- u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ +- u32 timeout; /* [ms] */ +- u16 sr_size; /* Shadow RAM size in words */ +- bool blank_nvm_mode; /* is NVM empty (no FW present)*/ +- u16 version; /* NVM package version */ +- u32 eetrack; /* NVM data version */ +- u32 oem_ver; /* OEM version info */ +-}; +- +-/* definitions used in NVM update support */ +- +-enum i40e_nvmupd_cmd { +- I40E_NVMUPD_INVALID, +- I40E_NVMUPD_READ_CON, +- I40E_NVMUPD_READ_SNT, +- I40E_NVMUPD_READ_LCB, +- I40E_NVMUPD_READ_SA, +- I40E_NVMUPD_WRITE_ERA, +- I40E_NVMUPD_WRITE_CON, +- I40E_NVMUPD_WRITE_SNT, +- I40E_NVMUPD_WRITE_LCB, +- I40E_NVMUPD_WRITE_SA, +- I40E_NVMUPD_CSUM_CON, +- I40E_NVMUPD_CSUM_SA, +- I40E_NVMUPD_CSUM_LCB, +- I40E_NVMUPD_STATUS, +- I40E_NVMUPD_EXEC_AQ, +- I40E_NVMUPD_GET_AQ_RESULT, +- I40E_NVMUPD_GET_AQ_EVENT, +-}; +- +-enum i40e_nvmupd_state { +- I40E_NVMUPD_STATE_INIT, +- I40E_NVMUPD_STATE_READING, +- I40E_NVMUPD_STATE_WRITING, +- I40E_NVMUPD_STATE_INIT_WAIT, +- I40E_NVMUPD_STATE_WRITE_WAIT, +- I40E_NVMUPD_STATE_ERROR +-}; +- +-/* nvm_access definition and its masks/shifts need to be accessible to +- * application, core driver, and shared code. Where is the right file? +- */ +-#define I40E_NVM_READ 0xB +-#define I40E_NVM_WRITE 0xC +- +-#define I40E_NVM_MOD_PNT_MASK 0xFF +- +-#define I40E_NVM_TRANS_SHIFT 8 +-#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) +-#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 +-#define I40E_NVM_PRESERVATION_FLAGS_MASK \ +- (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) +-#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 +-#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 +-#define I40E_NVM_CON 0x0 +-#define I40E_NVM_SNT 0x1 +-#define I40E_NVM_LCB 0x2 +-#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) +-#define I40E_NVM_ERA 0x4 +-#define I40E_NVM_CSUM 0x8 +-#define I40E_NVM_AQE 0xe +-#define I40E_NVM_EXEC 0xf +- +-#define I40E_NVM_ADAPT_SHIFT 16 +-#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) +- +-#define I40E_NVMUPD_MAX_DATA 4096 +-#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ +- +-struct i40e_nvm_access { +- u32 command; +- u32 config; +- u32 offset; /* in bytes */ +- u32 data_size; /* in bytes */ +- u8 data[1]; +-}; +- +-/* (Q)SFP module access definitions */ +-#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 +-#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 +-#define I40E_MODULE_TYPE_ADDR 0x00 +-#define I40E_MODULE_REVISION_ADDR 0x01 +-#define I40E_MODULE_SFF_8472_COMP 0x5E +-#define I40E_MODULE_SFF_8472_SWAP 0x5C +-#define I40E_MODULE_SFF_ADDR_MODE 0x04 +-#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D +-#define I40E_MODULE_TYPE_QSFP28 0x11 +-#define I40E_MODULE_QSFP_MAX_LEN 640 +- + /* PCI bus types */ + enum i40e_bus_type { + i40e_bus_type_unknown = 0, +@@ -447,69 +164,16 @@ struct i40e_bus_info { + u16 bus_id; + }; + +-/* Flow control (FC) parameters */ +-struct i40e_fc_info { +- enum i40e_fc_mode current_mode; /* FC mode in effect */ +- enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ +-}; +- + #define I40E_MAX_TRAFFIC_CLASS 8 + #define I40E_MAX_USER_PRIORITY 8 +-#define I40E_DCBX_MAX_APPS 32 +-#define I40E_LLDPDU_SIZE 1500 +- +-/* IEEE 802.1Qaz ETS Configuration data */ +-struct i40e_ieee_ets_config { +- u8 willing; +- u8 cbs; +- u8 maxtcs; +- u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; +- u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; +- u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; +-}; +- +-/* IEEE 802.1Qaz ETS Recommendation data */ +-struct i40e_ieee_ets_recommend { +- u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; +- u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; +- u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; +-}; +- +-/* IEEE 802.1Qaz PFC Configuration data */ +-struct i40e_ieee_pfc_config { +- u8 willing; +- u8 mbc; +- u8 pfccap; +- u8 pfcenable; +-}; +- +-/* IEEE 802.1Qaz Application Priority data */ +-struct i40e_ieee_app_priority_table { +- u8 priority; +- u8 selector; +- u16 protocolid; +-}; +- +-struct i40e_dcbx_config { +- u32 numapps; +- u32 tlv_status; /* CEE mode TLV status */ +- struct i40e_ieee_ets_config etscfg; +- struct i40e_ieee_ets_recommend etsrec; +- struct i40e_ieee_pfc_config pfc; +- struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; +-}; +- + /* Port hardware description */ + struct i40e_hw { + u8 __iomem *hw_addr; + void *back; + + /* subsystem structs */ +- struct i40e_phy_info phy; + struct i40e_mac_info mac; + struct i40e_bus_info bus; +- struct i40e_nvm_info nvm; +- struct i40e_fc_info fc; + + /* pci info */ + u16 device_id; +@@ -517,58 +181,13 @@ struct i40e_hw { + u16 subsystem_device_id; + u16 subsystem_vendor_id; + u8 revision_id; +- u8 port; +- bool adapter_stopped; + + /* capabilities for entire device and PCI func */ + struct i40e_hw_capabilities dev_caps; +- struct i40e_hw_capabilities func_caps; +- +- /* Flow Director shared filter space */ +- u16 fdir_shared_filter_count; +- +- /* device profile info */ +- u8 pf_id; +- u16 main_vsi_seid; +- +- /* for multi-function MACs */ +- u16 partition_id; +- u16 num_partitions; +- u16 num_ports; +- +- /* Closest numa node to the device */ +- u16 numa_node; + + /* Admin Queue info */ + struct i40e_adminq_info aq; + +- /* state of nvm update process */ +- enum i40e_nvmupd_state nvmupd_state; +- struct i40e_aq_desc nvm_wb_desc; +- struct i40e_aq_desc nvm_aq_event_desc; +- struct i40e_virt_mem nvm_buff; +- bool nvm_release_on_done; +- u16 nvm_wait_opcode; +- +- /* HMC info */ +- struct i40e_hmc_info hmc; /* HMC info struct */ +- +- /* LLDP/DCBX Status */ +- u16 dcbx_status; +- +-#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) +-#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) +- +- /* DCBX info */ +- struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ +- struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ +- struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ +- +- /* Used in set switch config AQ command */ +- u16 switch_tag; +- u16 first_tag; +- u16 second_tag; +- + /* debug mask */ + u32 debug_mask; + char err_str[16]; +@@ -962,9 +581,6 @@ struct i40e_tx_context_desc { + __le64 type_cmd_tso_mss; + }; + +-#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 +-#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) +- + #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 + #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) + +@@ -1028,21 +644,6 @@ enum i40e_tx_ctx_desc_eipt_offload { + + #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 + #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) +-struct i40e_filter_program_desc { +- __le32 qindex_flex_ptype_vsi; +- __le32 rsvd; +- __le32 dtype_cmd_cntindex; +- __le32 fd_id; +-}; +-#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 +-#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ +- I40E_TXD_FLTR_QW0_QINDEX_SHIFT) +-#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 +-#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ +- I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) +-#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 +-#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ +- I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) + + /* Packet Classifier Types for filters */ + enum i40e_filter_pctype { +@@ -1076,58 +677,6 @@ enum i40e_filter_pctype { + I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, + }; + +-enum i40e_filter_program_desc_dest { +- I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, +- I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, +- I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, +-}; +- +-enum i40e_filter_program_desc_fd_status { +- I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, +- I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, +- I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, +- I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, +-}; +- +-#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 +-#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ +- I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) +- +-#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 +-#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ +- I40E_TXD_FLTR_QW1_CMD_SHIFT) +- +-#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) +-#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) +- +-enum i40e_filter_program_desc_pcmd { +- I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, +- I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, +-}; +- +-#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) +-#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) +- +-#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) +-#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) +- +-#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ +- I40E_TXD_FLTR_QW1_CMD_SHIFT) +-#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ +- I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) +- +-#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 +-#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ +- I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) +- +-enum i40e_filter_type { +- I40E_FLOW_DIRECTOR_FLTR = 0, +- I40E_PE_QUAD_HASH_FLTR = 1, +- I40E_ETHERTYPE_FLTR, +- I40E_FCOE_CTX_FLTR, +- I40E_MAC_VLAN_FLTR, +- I40E_HASH_FLTR +-}; + + struct i40e_vsi_context { + u16 seid; +@@ -1167,330 +716,4 @@ struct i40e_eth_stats { + u64 tx_discards; /* tdpc */ + u64 tx_errors; /* tepc */ + }; +- +-/* Statistics collected per VEB per TC */ +-struct i40e_veb_tc_stats { +- u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; +- u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; +- u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; +- u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; +-}; +- +-/* Statistics collected by the MAC */ +-struct i40e_hw_port_stats { +- /* eth stats collected by the port */ +- struct i40e_eth_stats eth; +- +- /* additional port specific stats */ +- u64 tx_dropped_link_down; /* tdold */ +- u64 crc_errors; /* crcerrs */ +- u64 illegal_bytes; /* illerrc */ +- u64 error_bytes; /* errbc */ +- u64 mac_local_faults; /* mlfc */ +- u64 mac_remote_faults; /* mrfc */ +- u64 rx_length_errors; /* rlec */ +- u64 link_xon_rx; /* lxonrxc */ +- u64 link_xoff_rx; /* lxoffrxc */ +- u64 priority_xon_rx[8]; /* pxonrxc[8] */ +- u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ +- u64 link_xon_tx; /* lxontxc */ +- u64 link_xoff_tx; /* lxofftxc */ +- u64 priority_xon_tx[8]; /* pxontxc[8] */ +- u64 priority_xoff_tx[8]; /* pxofftxc[8] */ +- u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ +- u64 rx_size_64; /* prc64 */ +- u64 rx_size_127; /* prc127 */ +- u64 rx_size_255; /* prc255 */ +- u64 rx_size_511; /* prc511 */ +- u64 rx_size_1023; /* prc1023 */ +- u64 rx_size_1522; /* prc1522 */ +- u64 rx_size_big; /* prc9522 */ +- u64 rx_undersize; /* ruc */ +- u64 rx_fragments; /* rfc */ +- u64 rx_oversize; /* roc */ +- u64 rx_jabber; /* rjc */ +- u64 tx_size_64; /* ptc64 */ +- u64 tx_size_127; /* ptc127 */ +- u64 tx_size_255; /* ptc255 */ +- u64 tx_size_511; /* ptc511 */ +- u64 tx_size_1023; /* ptc1023 */ +- u64 tx_size_1522; /* ptc1522 */ +- u64 tx_size_big; /* ptc9522 */ +- u64 mac_short_packet_dropped; /* mspdc */ +- u64 checksum_error; /* xec */ +- /* flow director stats */ +- u64 fd_atr_match; +- u64 fd_sb_match; +- u64 fd_atr_tunnel_match; +- u32 fd_atr_status; +- u32 fd_sb_status; +- /* EEE LPI */ +- u32 tx_lpi_status; +- u32 rx_lpi_status; +- u64 tx_lpi_count; /* etlpic */ +- u64 rx_lpi_count; /* erlpic */ +-}; +- +-/* Checksum and Shadow RAM pointers */ +-#define I40E_SR_NVM_CONTROL_WORD 0x00 +-#define I40E_EMP_MODULE_PTR 0x0F +-#define I40E_SR_EMP_MODULE_PTR 0x48 +-#define I40E_NVM_OEM_VER_OFF 0x83 +-#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 +-#define I40E_SR_NVM_WAKE_ON_LAN 0x19 +-#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 +-#define I40E_SR_NVM_EETRACK_LO 0x2D +-#define I40E_SR_NVM_EETRACK_HI 0x2E +-#define I40E_SR_VPD_PTR 0x2F +-#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E +-#define I40E_SR_SW_CHECKSUM_WORD 0x3F +- +-/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ +-#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 +-#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 +-#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 +-#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) +-#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) +-#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) +-#define I40E_PTR_TYPE BIT(15) +- +-/* Shadow RAM related */ +-#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 +-#define I40E_SR_WORDS_IN_1KB 512 +-/* Checksum should be calculated such that after adding all the words, +- * including the checksum word itself, the sum should be 0xBABA. +- */ +-#define I40E_SR_SW_CHECKSUM_BASE 0xBABA +- +-#define I40E_SRRD_SRCTL_ATTEMPTS 100000 +- +-enum i40e_switch_element_types { +- I40E_SWITCH_ELEMENT_TYPE_MAC = 1, +- I40E_SWITCH_ELEMENT_TYPE_PF = 2, +- I40E_SWITCH_ELEMENT_TYPE_VF = 3, +- I40E_SWITCH_ELEMENT_TYPE_EMP = 4, +- I40E_SWITCH_ELEMENT_TYPE_BMC = 6, +- I40E_SWITCH_ELEMENT_TYPE_PE = 16, +- I40E_SWITCH_ELEMENT_TYPE_VEB = 17, +- I40E_SWITCH_ELEMENT_TYPE_PA = 18, +- I40E_SWITCH_ELEMENT_TYPE_VSI = 19, +-}; +- +-/* Supported EtherType filters */ +-enum i40e_ether_type_index { +- I40E_ETHER_TYPE_1588 = 0, +- I40E_ETHER_TYPE_FIP = 1, +- I40E_ETHER_TYPE_OUI_EXTENDED = 2, +- I40E_ETHER_TYPE_MAC_CONTROL = 3, +- I40E_ETHER_TYPE_LLDP = 4, +- I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, +- I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, +- I40E_ETHER_TYPE_QCN_CNM = 7, +- I40E_ETHER_TYPE_8021X = 8, +- I40E_ETHER_TYPE_ARP = 9, +- I40E_ETHER_TYPE_RSV1 = 10, +- I40E_ETHER_TYPE_RSV2 = 11, +-}; +- +-/* Filter context base size is 1K */ +-#define I40E_HASH_FILTER_BASE_SIZE 1024 +-/* Supported Hash filter values */ +-enum i40e_hash_filter_size { +- I40E_HASH_FILTER_SIZE_1K = 0, +- I40E_HASH_FILTER_SIZE_2K = 1, +- I40E_HASH_FILTER_SIZE_4K = 2, +- I40E_HASH_FILTER_SIZE_8K = 3, +- I40E_HASH_FILTER_SIZE_16K = 4, +- I40E_HASH_FILTER_SIZE_32K = 5, +- I40E_HASH_FILTER_SIZE_64K = 6, +- I40E_HASH_FILTER_SIZE_128K = 7, +- I40E_HASH_FILTER_SIZE_256K = 8, +- I40E_HASH_FILTER_SIZE_512K = 9, +- I40E_HASH_FILTER_SIZE_1M = 10, +-}; +- +-/* DMA context base size is 0.5K */ +-#define I40E_DMA_CNTX_BASE_SIZE 512 +-/* Supported DMA context values */ +-enum i40e_dma_cntx_size { +- I40E_DMA_CNTX_SIZE_512 = 0, +- I40E_DMA_CNTX_SIZE_1K = 1, +- I40E_DMA_CNTX_SIZE_2K = 2, +- I40E_DMA_CNTX_SIZE_4K = 3, +- I40E_DMA_CNTX_SIZE_8K = 4, +- I40E_DMA_CNTX_SIZE_16K = 5, +- I40E_DMA_CNTX_SIZE_32K = 6, +- I40E_DMA_CNTX_SIZE_64K = 7, +- I40E_DMA_CNTX_SIZE_128K = 8, +- I40E_DMA_CNTX_SIZE_256K = 9, +-}; +- +-/* Supported Hash look up table (LUT) sizes */ +-enum i40e_hash_lut_size { +- I40E_HASH_LUT_SIZE_128 = 0, +- I40E_HASH_LUT_SIZE_512 = 1, +-}; +- +-/* Structure to hold a per PF filter control settings */ +-struct i40e_filter_control_settings { +- /* number of PE Quad Hash filter buckets */ +- enum i40e_hash_filter_size pe_filt_num; +- /* number of PE Quad Hash contexts */ +- enum i40e_dma_cntx_size pe_cntx_num; +- /* number of FCoE filter buckets */ +- enum i40e_hash_filter_size fcoe_filt_num; +- /* number of FCoE DDP contexts */ +- enum i40e_dma_cntx_size fcoe_cntx_num; +- /* size of the Hash LUT */ +- enum i40e_hash_lut_size hash_lut_size; +- /* enable FDIR filters for PF and its VFs */ +- bool enable_fdir; +- /* enable Ethertype filters for PF and its VFs */ +- bool enable_ethtype; +- /* enable MAC/VLAN filters for PF and its VFs */ +- bool enable_macvlan; +-}; +- +-/* Structure to hold device level control filter counts */ +-struct i40e_control_filter_stats { +- u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ +- u16 etype_used; /* Used perfect EtherType filters */ +- u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ +- u16 etype_free; /* Un-used perfect EtherType filters */ +-}; +- +-enum i40e_reset_type { +- I40E_RESET_POR = 0, +- I40E_RESET_CORER = 1, +- I40E_RESET_GLOBR = 2, +- I40E_RESET_EMPR = 3, +-}; +- +-/* IEEE 802.1AB LLDP Agent Variables from NVM */ +-#define I40E_NVM_LLDP_CFG_PTR 0x06 +-#define I40E_SR_LLDP_CFG_PTR 0x31 +- +-/* RSS Hash Table Size */ +-#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 +- +-/* INPUT SET MASK for RSS, flow director and flexible payload */ +-#define I40E_FD_INSET_L3_SRC_SHIFT 47 +-#define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \ +- I40E_FD_INSET_L3_SRC_SHIFT) +-#define I40E_FD_INSET_L3_DST_SHIFT 35 +-#define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \ +- I40E_FD_INSET_L3_DST_SHIFT) +-#define I40E_FD_INSET_L4_SRC_SHIFT 34 +-#define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \ +- I40E_FD_INSET_L4_SRC_SHIFT) +-#define I40E_FD_INSET_L4_DST_SHIFT 33 +-#define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \ +- I40E_FD_INSET_L4_DST_SHIFT) +-#define I40E_FD_INSET_VERIFY_TAG_SHIFT 31 +-#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \ +- I40E_FD_INSET_VERIFY_TAG_SHIFT) +- +-#define I40E_FD_INSET_FLEX_WORD50_SHIFT 17 +-#define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD50_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD51_SHIFT 16 +-#define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD51_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD52_SHIFT 15 +-#define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD52_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD53_SHIFT 14 +-#define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD53_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD54_SHIFT 13 +-#define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD54_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD55_SHIFT 12 +-#define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD55_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD56_SHIFT 11 +-#define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD56_SHIFT) +-#define I40E_FD_INSET_FLEX_WORD57_SHIFT 10 +-#define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \ +- I40E_FD_INSET_FLEX_WORD57_SHIFT) +- +-/* Version format for Dynamic Device Personalization(DDP) */ +-struct i40e_ddp_version { +- u8 major; +- u8 minor; +- u8 update; +- u8 draft; +-}; +- +-#define I40E_DDP_NAME_SIZE 32 +- +-/* Package header */ +-struct i40e_package_header { +- struct i40e_ddp_version version; +- u32 segment_count; +- u32 segment_offset[1]; +-}; +- +-/* Generic segment header */ +-struct i40e_generic_seg_header { +-#define SEGMENT_TYPE_METADATA 0x00000001 +-#define SEGMENT_TYPE_NOTES 0x00000002 +-#define SEGMENT_TYPE_I40E 0x00000011 +-#define SEGMENT_TYPE_X722 0x00000012 +- u32 type; +- struct i40e_ddp_version version; +- u32 size; +- char name[I40E_DDP_NAME_SIZE]; +-}; +- +-struct i40e_metadata_segment { +- struct i40e_generic_seg_header header; +- struct i40e_ddp_version version; +- u32 track_id; +- char name[I40E_DDP_NAME_SIZE]; +-}; +- +-struct i40e_device_id_entry { +- u32 vendor_dev_id; +- u32 sub_vendor_dev_id; +-}; +- +-struct i40e_profile_segment { +- struct i40e_generic_seg_header header; +- struct i40e_ddp_version version; +- char name[I40E_DDP_NAME_SIZE]; +- u32 device_table_count; +- struct i40e_device_id_entry device_table[1]; +-}; +- +-struct i40e_section_table { +- u32 section_count; +- u32 section_offset[1]; +-}; +- +-struct i40e_profile_section_header { +- u16 tbl_size; +- u16 data_end; +- struct { +-#define SECTION_TYPE_INFO 0x00000010 +-#define SECTION_TYPE_MMIO 0x00000800 +-#define SECTION_TYPE_AQ 0x00000801 +-#define SECTION_TYPE_NOTE 0x80000000 +-#define SECTION_TYPE_NAME 0x80000001 +- u32 type; +- u32 offset; +- u32 size; +- } section; +-}; +- +-struct i40e_profile_info { +- u32 track_id; +- struct i40e_ddp_version version; +- u8 op; +-#define I40E_DDP_ADD_TRACKID 0x01 +-#define I40E_DDP_REMOVE_TRACKID 0x02 +- u8 reserved[7]; +- u8 name[I40E_DDP_NAME_SIZE]; +-}; + #endif /* _I40E_TYPE_H_ */ +-- +2.39.2 + diff --git a/queue-4.19/iavf-fix-inverted-rx-hash-condition-leading-to-disab.patch b/queue-4.19/iavf-fix-inverted-rx-hash-condition-leading-to-disab.patch new file mode 100644 index 00000000000..ed5d16e9683 --- /dev/null +++ b/queue-4.19/iavf-fix-inverted-rx-hash-condition-leading-to-disab.patch @@ -0,0 +1,44 @@ +From 4e075b943f859d5796743ce803d6e85281ad542f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Mar 2023 12:59:07 +0100 +Subject: iavf: fix inverted Rx hash condition leading to disabled hash + +From: Alexander Lobakin + +[ Upstream commit 32d57f667f871bc5a8babbe27ea4c5e668ee0ea8 ] + +Condition, which checks whether the netdev has hashing enabled is +inverted. Basically, the tagged commit effectively disabled passing flow +hash from descriptor to skb, unless user *disables* it via Ethtool. +Commit a876c3ba59a6 ("i40e/i40evf: properly report Rx packet hash") +fixed this problem, but only for i40e. +Invert the condition now in iavf and unblock passing hash to skbs again. + +Fixes: 857942fd1aa1 ("i40e: Fix Rx hash reported to the stack by our driver") +Reviewed-by: Larysa Zaremba +Reviewed-by: Michal Kubiak +Signed-off-by: Alexander Lobakin +Tested-by: Rafal Romanowski +Reviewed-by: Leon Romanovsky +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/iavf/i40e_txrx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/intel/iavf/i40e_txrx.c b/drivers/net/ethernet/intel/iavf/i40e_txrx.c +index 1bf9734ae9cf0..d4bd06adc1453 100644 +--- a/drivers/net/ethernet/intel/iavf/i40e_txrx.c ++++ b/drivers/net/ethernet/intel/iavf/i40e_txrx.c +@@ -1062,7 +1062,7 @@ static inline void i40e_rx_hash(struct i40e_ring *ring, + cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << + I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); + +- if (ring->netdev->features & NETIF_F_RXHASH) ++ if (!(ring->netdev->features & NETIF_F_RXHASH)) + return; + + if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { +-- +2.39.2 + diff --git a/queue-4.19/igbvf-regard-vf-reset-nack-as-success.patch b/queue-4.19/igbvf-regard-vf-reset-nack-as-success.patch new file mode 100644 index 00000000000..c73c6d9a99a --- /dev/null +++ b/queue-4.19/igbvf-regard-vf-reset-nack-as-success.patch @@ -0,0 +1,62 @@ +From d47186b46be6ef0552dbbd328d06f469efd92099 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Dec 2022 19:20:03 +0900 +Subject: igbvf: Regard vf reset nack as success + +From: Akihiko Odaki + +[ Upstream commit 02c83791ef969c6a8a150b4927193d0d0e50fb23 ] + +vf reset nack actually represents the reset operation itself is +performed but no address is assigned. Therefore, e1000_reset_hw_vf +should fill the "perm_addr" with the zero address and return success on +such an occasion. This prevents its callers in netdev.c from saying PF +still resetting, and instead allows them to correctly report that no +address is assigned. + +Fixes: 6ddbc4cf1f4d ("igb: Indicate failure on vf reset for empty mac address") +Signed-off-by: Akihiko Odaki +Reviewed-by: Leon Romanovsky +Tested-by: Marek Szlosek +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/igbvf/vf.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/intel/igbvf/vf.c b/drivers/net/ethernet/intel/igbvf/vf.c +index b8ba3f94c3632..a47a2e3e548cf 100644 +--- a/drivers/net/ethernet/intel/igbvf/vf.c ++++ b/drivers/net/ethernet/intel/igbvf/vf.c +@@ -1,6 +1,8 @@ + // SPDX-License-Identifier: GPL-2.0 + /* Copyright(c) 2009 - 2018 Intel Corporation. */ + ++#include ++ + #include "vf.h" + + static s32 e1000_check_for_link_vf(struct e1000_hw *hw); +@@ -131,11 +133,16 @@ static s32 e1000_reset_hw_vf(struct e1000_hw *hw) + /* set our "perm_addr" based on info provided by PF */ + ret_val = mbx->ops.read_posted(hw, msgbuf, 3); + if (!ret_val) { +- if (msgbuf[0] == (E1000_VF_RESET | +- E1000_VT_MSGTYPE_ACK)) ++ switch (msgbuf[0]) { ++ case E1000_VF_RESET | E1000_VT_MSGTYPE_ACK: + memcpy(hw->mac.perm_addr, addr, ETH_ALEN); +- else ++ break; ++ case E1000_VF_RESET | E1000_VT_MSGTYPE_NACK: ++ eth_zero_addr(hw->mac.perm_addr); ++ break; ++ default: + ret_val = -E1000_ERR_MAC_INIT; ++ } + } + } + +-- +2.39.2 + diff --git a/queue-4.19/intel-ethernet-rename-i40evf-to-iavf.patch b/queue-4.19/intel-ethernet-rename-i40evf-to-iavf.patch new file mode 100644 index 00000000000..3307ace41e8 --- /dev/null +++ b/queue-4.19/intel-ethernet-rename-i40evf-to-iavf.patch @@ -0,0 +1,385 @@ +From 0dba12e42d4695e058a6000f37d484979c2e78ca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 14 Sep 2018 17:37:44 -0700 +Subject: intel-ethernet: rename i40evf to iavf + +From: Jesse Brandeburg + +[ Upstream commit 8062b2263a9fc294ddeb4024b113e8e26b82d5de ] + +Rename the Intel Ethernet Adaptive Virtual Function driver +(i40evf) to a new name (iavf) that is more consistent with +the ongoing maintenance of the driver as the universal VF driver +for multiple product lines. + +This first patch fixes up the directory names and the .ko name, +intentionally ignoring the function names inside the driver +for now. Basically this is the simplest patch that gets +the rename done and will be followed by other patches that +rename the internal functions. + +This patch also addresses a couple of string/name issues +and updates the Copyright year. + +Also, made sure to add a MODULE_ALIAS to the old name. + +Signed-off-by: Jesse Brandeburg +Tested-by: Andrew Bowers +Signed-off-by: Jeff Kirsher +Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") +Signed-off-by: Sasha Levin +--- + Documentation/networking/00-INDEX | 4 ++-- + .../networking/{i40evf.txt => iavf.txt} | 16 +++++++++------- + MAINTAINERS | 2 +- + drivers/net/ethernet/intel/Kconfig | 15 +++++++++++---- + drivers/net/ethernet/intel/Makefile | 2 +- + drivers/net/ethernet/intel/i40evf/Makefile | 16 ---------------- + drivers/net/ethernet/intel/iavf/Makefile | 15 +++++++++++++++ + .../intel/{i40evf => iavf}/i40e_adminq.c | 0 + .../intel/{i40evf => iavf}/i40e_adminq.h | 0 + .../intel/{i40evf => iavf}/i40e_adminq_cmd.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_alloc.h | 0 + .../intel/{i40evf => iavf}/i40e_common.c | 0 + .../intel/{i40evf => iavf}/i40e_devids.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_hmc.h | 0 + .../intel/{i40evf => iavf}/i40e_lan_hmc.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_osdep.h | 0 + .../intel/{i40evf => iavf}/i40e_prototype.h | 0 + .../intel/{i40evf => iavf}/i40e_register.h | 0 + .../intel/{i40evf => iavf}/i40e_status.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_trace.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_txrx.c | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_txrx.h | 0 + .../ethernet/intel/{i40evf => iavf}/i40e_type.h | 0 + .../net/ethernet/intel/{i40evf => iavf}/i40evf.h | 0 + .../intel/{i40evf => iavf}/i40evf_client.c | 0 + .../intel/{i40evf => iavf}/i40evf_client.h | 0 + .../intel/{i40evf => iavf}/i40evf_ethtool.c | 0 + .../intel/{i40evf => iavf}/i40evf_main.c | 7 ++++--- + .../intel/{i40evf => iavf}/i40evf_virtchnl.c | 0 + 29 files changed, 43 insertions(+), 34 deletions(-) + rename Documentation/networking/{i40evf.txt => iavf.txt} (72%) + delete mode 100644 drivers/net/ethernet/intel/i40evf/Makefile + create mode 100644 drivers/net/ethernet/intel/iavf/Makefile + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq.c (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq_cmd.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_alloc.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_common.c (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_devids.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_hmc.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_lan_hmc.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_osdep.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_prototype.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_register.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_status.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_trace.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_txrx.c (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_txrx.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_type.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_client.c (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_client.h (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_ethtool.c (100%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_main.c (99%) + rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_virtchnl.c (100%) + +diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX +index 02a323c432612..2a9dbac38b4e9 100644 +--- a/Documentation/networking/00-INDEX ++++ b/Documentation/networking/00-INDEX +@@ -94,8 +94,8 @@ gianfar.txt + - Gianfar Ethernet Driver. + i40e.txt + - README for the Intel Ethernet Controller XL710 Driver (i40e). +-i40evf.txt +- - Short note on the Driver for the Intel(R) XL710 X710 Virtual Function ++iavf.txt ++ - README for the Intel Ethernet Adaptive Virtual Function Driver (iavf). + ieee802154.txt + - Linux IEEE 802.15.4 implementation, API and drivers + igb.txt +diff --git a/Documentation/networking/i40evf.txt b/Documentation/networking/iavf.txt +similarity index 72% +rename from Documentation/networking/i40evf.txt +rename to Documentation/networking/iavf.txt +index e9b3035b95d05..cc902a2369d69 100644 +--- a/Documentation/networking/i40evf.txt ++++ b/Documentation/networking/iavf.txt +@@ -2,7 +2,7 @@ Linux* Base Driver for Intel(R) Network Connection + ================================================== + + Intel Ethernet Adaptive Virtual Function Linux driver. +-Copyright(c) 2013-2017 Intel Corporation. ++Copyright(c) 2013-2018 Intel Corporation. + + Contents + ======== +@@ -11,20 +11,21 @@ Contents + - Known Issues/Troubleshooting + - Support + +-This file describes the i40evf Linux* Base Driver. ++This file describes the iavf Linux* Base Driver. This driver ++was formerly called i40evf. + +-The i40evf driver supports the below mentioned virtual function ++The iavf driver supports the below mentioned virtual function + devices and can only be activated on kernels running the i40e or + newer Physical Function (PF) driver compiled with CONFIG_PCI_IOV. +-The i40evf driver requires CONFIG_PCI_MSI to be enabled. ++The iavf driver requires CONFIG_PCI_MSI to be enabled. + +-The guest OS loading the i40evf driver must support MSI-X interrupts. ++The guest OS loading the iavf driver must support MSI-X interrupts. + + Supported Hardware + ================== + Intel XL710 X710 Virtual Function +-Intel Ethernet Adaptive Virtual Function + Intel X722 Virtual Function ++Intel Ethernet Adaptive Virtual Function + + Identifying Your Adapter + ======================== +@@ -32,7 +33,8 @@ Identifying Your Adapter + For more information on how to identify your adapter, go to the + Adapter & Driver ID Guide at: + +- http://support.intel.com/support/go/network/adapter/idguide.htm ++ https://www.intel.com/content/www/us/en/support/articles/000005584/network-and-i-o/ethernet-products.html ++ + + Known Issues/Troubleshooting + ============================ +diff --git a/MAINTAINERS b/MAINTAINERS +index af0f322cf2f7c..a8015db6b37eb 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7377,7 +7377,7 @@ F: Documentation/networking/ixgb.txt + F: Documentation/networking/ixgbe.txt + F: Documentation/networking/ixgbevf.txt + F: Documentation/networking/i40e.txt +-F: Documentation/networking/i40evf.txt ++F: Documentation/networking/iavf.txt + F: Documentation/networking/ice.txt + F: drivers/net/ethernet/intel/ + F: drivers/net/ethernet/intel/*/ +diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig +index 1ab613eb57964..b542aba6f0e86 100644 +--- a/drivers/net/ethernet/intel/Kconfig ++++ b/drivers/net/ethernet/intel/Kconfig +@@ -235,20 +235,27 @@ config I40E_DCB + + If unsure, say N. + ++# this is here to allow seamless migration from I40EVF --> IAVF name ++# so that CONFIG_IAVF symbol will always mirror the state of CONFIG_I40EVF ++config IAVF ++ tristate + config I40EVF + tristate "Intel(R) Ethernet Adaptive Virtual Function support" ++ select IAVF + depends on PCI_MSI + ---help--- + This driver supports virtual functions for Intel XL710, +- X710, X722, and all devices advertising support for Intel +- Ethernet Adaptive Virtual Function devices. For more ++ X710, X722, XXV710, and all devices advertising support for ++ Intel Ethernet Adaptive Virtual Function devices. For more + information on how to identify your adapter, go to the Adapter + & Driver ID Guide that can be located at: + +- ++ ++ ++ This driver was formerly named i40evf. + + To compile this driver as a module, choose M here. The module +- will be called i40evf. MSI-X interrupt support is required ++ will be called iavf. MSI-X interrupt support is required + for this driver to work correctly. + + config ICE +diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile +index 807a4f8c7e4ef..b91153df6ee8d 100644 +--- a/drivers/net/ethernet/intel/Makefile ++++ b/drivers/net/ethernet/intel/Makefile +@@ -12,6 +12,6 @@ obj-$(CONFIG_IXGBE) += ixgbe/ + obj-$(CONFIG_IXGBEVF) += ixgbevf/ + obj-$(CONFIG_I40E) += i40e/ + obj-$(CONFIG_IXGB) += ixgb/ +-obj-$(CONFIG_I40EVF) += i40evf/ ++obj-$(CONFIG_IAVF) += iavf/ + obj-$(CONFIG_FM10K) += fm10k/ + obj-$(CONFIG_ICE) += ice/ +diff --git a/drivers/net/ethernet/intel/i40evf/Makefile b/drivers/net/ethernet/intel/i40evf/Makefile +deleted file mode 100644 +index 3c5c6e9622805..0000000000000 +--- a/drivers/net/ethernet/intel/i40evf/Makefile ++++ /dev/null +@@ -1,16 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0 +-# Copyright(c) 2013 - 2018 Intel Corporation. +- +-# +-## Makefile for the Intel(R) 40GbE VF driver +-# +-# +- +-ccflags-y += -I$(src) +-subdir-ccflags-y += -I$(src) +- +-obj-$(CONFIG_I40EVF) += i40evf.o +- +-i40evf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ +- i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o +- +diff --git a/drivers/net/ethernet/intel/iavf/Makefile b/drivers/net/ethernet/intel/iavf/Makefile +new file mode 100644 +index 0000000000000..1b050d9d5f493 +--- /dev/null ++++ b/drivers/net/ethernet/intel/iavf/Makefile +@@ -0,0 +1,15 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# Copyright(c) 2013 - 2018 Intel Corporation. ++# ++# Makefile for the Intel(R) Ethernet Adaptive Virtual Function (iavf) ++# driver ++# ++# ++ ++ccflags-y += -I$(src) ++subdir-ccflags-y += -I$(src) ++ ++obj-$(CONFIG_IAVF) += iavf.o ++ ++iavf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ ++ i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.c +rename to drivers/net/ethernet/intel/iavf/i40e_adminq.c +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h b/drivers/net/ethernet/intel/iavf/i40e_adminq.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.h +rename to drivers/net/ethernet/intel/iavf/i40e_adminq.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h +rename to drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_alloc.h b/drivers/net/ethernet/intel/iavf/i40e_alloc.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_alloc.h +rename to drivers/net/ethernet/intel/iavf/i40e_alloc.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_common.c +rename to drivers/net/ethernet/intel/iavf/i40e_common.c +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_devids.h b/drivers/net/ethernet/intel/iavf/i40e_devids.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_devids.h +rename to drivers/net/ethernet/intel/iavf/i40e_devids.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_hmc.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_hmc.h +rename to drivers/net/ethernet/intel/iavf/i40e_hmc.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h +rename to drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_osdep.h b/drivers/net/ethernet/intel/iavf/i40e_osdep.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_osdep.h +rename to drivers/net/ethernet/intel/iavf/i40e_osdep.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_prototype.h +rename to drivers/net/ethernet/intel/iavf/i40e_prototype.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_register.h +rename to drivers/net/ethernet/intel/iavf/i40e_register.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_status.h b/drivers/net/ethernet/intel/iavf/i40e_status.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_status.h +rename to drivers/net/ethernet/intel/iavf/i40e_status.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_trace.h b/drivers/net/ethernet/intel/iavf/i40e_trace.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_trace.h +rename to drivers/net/ethernet/intel/iavf/i40e_trace.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/iavf/i40e_txrx.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.c +rename to drivers/net/ethernet/intel/iavf/i40e_txrx.c +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/iavf/i40e_txrx.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.h +rename to drivers/net/ethernet/intel/iavf/i40e_txrx.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40e_type.h +rename to drivers/net/ethernet/intel/iavf/i40e_type.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/iavf/i40evf.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40evf.h +rename to drivers/net/ethernet/intel/iavf/i40evf.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.c b/drivers/net/ethernet/intel/iavf/i40evf_client.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40evf_client.c +rename to drivers/net/ethernet/intel/iavf/i40evf_client.c +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.h b/drivers/net/ethernet/intel/iavf/i40evf_client.h +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40evf_client.h +rename to drivers/net/ethernet/intel/iavf/i40evf_client.h +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/iavf/i40evf_ethtool.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c +rename to drivers/net/ethernet/intel/iavf/i40evf_ethtool.c +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/iavf/i40evf_main.c +similarity index 99% +rename from drivers/net/ethernet/intel/i40evf/i40evf_main.c +rename to drivers/net/ethernet/intel/iavf/i40evf_main.c +index 5a6e579e9e653..60c2e5df58272 100644 +--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c ++++ b/drivers/net/ethernet/intel/iavf/i40evf_main.c +@@ -17,20 +17,20 @@ static int i40evf_close(struct net_device *netdev); + + char i40evf_driver_name[] = "i40evf"; + static const char i40evf_driver_string[] = +- "Intel(R) 40-10 Gigabit Virtual Function Network Driver"; ++ "Intel(R) Ethernet Adaptive Virtual Function Network Driver"; + + #define DRV_KERN "-k" + + #define DRV_VERSION_MAJOR 3 + #define DRV_VERSION_MINOR 2 +-#define DRV_VERSION_BUILD 2 ++#define DRV_VERSION_BUILD 3 + #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ + __stringify(DRV_VERSION_MINOR) "." \ + __stringify(DRV_VERSION_BUILD) \ + DRV_KERN + const char i40evf_driver_version[] = DRV_VERSION; + static const char i40evf_copyright[] = +- "Copyright (c) 2013 - 2015 Intel Corporation."; ++ "Copyright (c) 2013 - 2018 Intel Corporation."; + + /* i40evf_pci_tbl - PCI Device ID Table + * +@@ -51,6 +51,7 @@ static const struct pci_device_id i40evf_pci_tbl[] = { + + MODULE_DEVICE_TABLE(pci, i40evf_pci_tbl); + ++MODULE_ALIAS("i40evf"); + MODULE_AUTHOR("Intel Corporation, "); + MODULE_DESCRIPTION("Intel(R) XL710 X710 Virtual Function Network Driver"); + MODULE_LICENSE("GPL"); +diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c +similarity index 100% +rename from drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c +rename to drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c +-- +2.39.2 + diff --git a/queue-4.19/intel-igbvf-free-irq-on-the-error-path-in-igbvf_requ.patch b/queue-4.19/intel-igbvf-free-irq-on-the-error-path-in-igbvf_requ.patch new file mode 100644 index 00000000000..e3cf095b632 --- /dev/null +++ b/queue-4.19/intel-igbvf-free-irq-on-the-error-path-in-igbvf_requ.patch @@ -0,0 +1,54 @@ +From d43cbe18fafa239d68ee47ec6a2abe42ffa2e7ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 22 Nov 2022 10:28:52 +0800 +Subject: intel/igbvf: free irq on the error path in igbvf_request_msix() + +From: Gaosheng Cui + +[ Upstream commit 85eb39bb39cbb5c086df1e19ba67cc1366693a77 ] + +In igbvf_request_msix(), irqs have not been freed on the err path, +we need to free it. Fix it. + +Fixes: d4e0fe01a38a ("igbvf: add new driver to support 82576 virtual functions") +Signed-off-by: Gaosheng Cui +Reviewed-by: Maciej Fijalkowski +Tested-by: Marek Szlosek +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/igbvf/netdev.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c +index df827c2541628..70f5f28bfd9ed 100644 +--- a/drivers/net/ethernet/intel/igbvf/netdev.c ++++ b/drivers/net/ethernet/intel/igbvf/netdev.c +@@ -1070,7 +1070,7 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) + igbvf_intr_msix_rx, 0, adapter->rx_ring->name, + netdev); + if (err) +- goto out; ++ goto free_irq_tx; + + adapter->rx_ring->itr_register = E1000_EITR(vector); + adapter->rx_ring->itr_val = adapter->current_itr; +@@ -1079,10 +1079,14 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) + err = request_irq(adapter->msix_entries[vector].vector, + igbvf_msix_other, 0, netdev->name, netdev); + if (err) +- goto out; ++ goto free_irq_rx; + + igbvf_configure_msix(adapter); + return 0; ++free_irq_rx: ++ free_irq(adapter->msix_entries[--vector].vector, netdev); ++free_irq_tx: ++ free_irq(adapter->msix_entries[--vector].vector, netdev); + out: + return err; + } +-- +2.39.2 + diff --git a/queue-4.19/net-mdio-thunder-add-missing-fwnode_handle_put.patch b/queue-4.19/net-mdio-thunder-add-missing-fwnode_handle_put.patch new file mode 100644 index 00000000000..8ca30100a27 --- /dev/null +++ b/queue-4.19/net-mdio-thunder-add-missing-fwnode_handle_put.patch @@ -0,0 +1,36 @@ +From 56096a59dd60b0979286fffe1888933ebbe16645 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Mar 2023 14:20:57 +0800 +Subject: net: mdio: thunder: Add missing fwnode_handle_put() + +From: Liang He + +[ Upstream commit b1de5c78ebe9858ccec9d49af2f76724f1d47e3e ] + +In device_for_each_child_node(), we should add fwnode_handle_put() +when break out of the iteration device_for_each_child_node() +as it will automatically increase and decrease the refcounter. + +Fixes: 379d7ac7ca31 ("phy: mdio-thunder: Add driver for Cavium Thunder SoC MDIO buses.") +Signed-off-by: Liang He +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/phy/mdio-thunder.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/phy/mdio-thunder.c b/drivers/net/phy/mdio-thunder.c +index c0c922eff760c..959bf342133a7 100644 +--- a/drivers/net/phy/mdio-thunder.c ++++ b/drivers/net/phy/mdio-thunder.c +@@ -107,6 +107,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, + if (i >= ARRAY_SIZE(nexus->buses)) + break; + } ++ fwnode_handle_put(fwn); + return 0; + + err_release_regions: +-- +2.39.2 + diff --git a/queue-4.19/net-mlx5-read-the-tc-mapping-of-all-priorities-on-et.patch b/queue-4.19/net-mlx5-read-the-tc-mapping-of-all-priorities-on-et.patch new file mode 100644 index 00000000000..400862416b7 --- /dev/null +++ b/queue-4.19/net-mlx5-read-the-tc-mapping-of-all-priorities-on-et.patch @@ -0,0 +1,51 @@ +From 32f1f6f4205fb95a84decbf9c0daa10b08a98d53 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 15 Mar 2023 11:04:38 +0200 +Subject: net/mlx5: Read the TC mapping of all priorities on ETS query + +From: Maher Sanalla + +[ Upstream commit 44d553188c38ac74b799dfdcebafef2f7bb70942 ] + +When ETS configurations are queried by the user to get the mapping +assignment between packet priority and traffic class, only priorities up +to maximum TCs are queried from QTCT register in FW to retrieve their +assigned TC, leaving the rest of the priorities mapped to the default +TC #0 which might be misleading. + +Fix by querying the TC mapping of all priorities on each ETS query, +regardless of the maximum number of TCs configured in FW. + +Fixes: 820c2c5e773d ("net/mlx5e: Read ETS settings directly from firmware") +Signed-off-by: Maher Sanalla +Reviewed-by: Moshe Shemesh +Signed-off-by: Saeed Mahameed +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +index 722998d685646..6f1f53f91ed8c 100644 +--- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c ++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +@@ -109,12 +109,14 @@ static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev, + if (!MLX5_CAP_GEN(priv->mdev, ets)) + return -EOPNOTSUPP; + +- ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; +- for (i = 0; i < ets->ets_cap; i++) { ++ for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { + err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]); + if (err) + return err; ++ } + ++ ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; ++ for (i = 0; i < ets->ets_cap; i++) { + err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]); + if (err) + return err; +-- +2.39.2 + diff --git a/queue-4.19/net-ps3_gelic_net-fix-rx-sk_buff-length.patch b/queue-4.19/net-ps3_gelic_net-fix-rx-sk_buff-length.patch new file mode 100644 index 00000000000..8489bf6ae77 --- /dev/null +++ b/queue-4.19/net-ps3_gelic_net-fix-rx-sk_buff-length.patch @@ -0,0 +1,108 @@ +From 1b829ac8cbc1c95a1ba12a09c7f9db23dc0fc333 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 18 Mar 2023 17:39:16 +0000 +Subject: net/ps3_gelic_net: Fix RX sk_buff length + +From: Geoff Levand + +[ Upstream commit 19b3bb51c3bc288b3f2c6f8c4450b0f548320625 ] + +The Gelic Ethernet device needs to have the RX sk_buffs aligned to +GELIC_NET_RXBUF_ALIGN, and also the length of the RX sk_buffs must +be a multiple of GELIC_NET_RXBUF_ALIGN. + +The current Gelic Ethernet driver was not allocating sk_buffs large +enough to allow for this alignment. + +Also, correct the maximum and minimum MTU sizes, and add a new +preprocessor macro for the maximum frame size, GELIC_NET_MAX_FRAME. + +Fixes various randomly occurring runtime network errors. + +Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") +Signed-off-by: Geoff Levand +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/toshiba/ps3_gelic_net.c | 19 ++++++++++--------- + drivers/net/ethernet/toshiba/ps3_gelic_net.h | 5 +++-- + 2 files changed, 13 insertions(+), 11 deletions(-) + +diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c +index 75237c81c63d6..67f61379ba672 100644 +--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c ++++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c +@@ -378,28 +378,29 @@ static int gelic_card_init_chain(struct gelic_card *card, + * + * allocates a new rx skb, iommu-maps it and attaches it to the descriptor. + * Activate the descriptor state-wise ++ * ++ * Gelic RX sk_buffs must be aligned to GELIC_NET_RXBUF_ALIGN and the length ++ * must be a multiple of GELIC_NET_RXBUF_ALIGN. + */ + static int gelic_descr_prepare_rx(struct gelic_card *card, + struct gelic_descr *descr) + { ++ static const unsigned int rx_skb_size = ++ ALIGN(GELIC_NET_MAX_FRAME, GELIC_NET_RXBUF_ALIGN) + ++ GELIC_NET_RXBUF_ALIGN - 1; + int offset; +- unsigned int bufsize; + + if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) + dev_info(ctodev(card), "%s: ERROR status\n", __func__); +- /* we need to round up the buffer size to a multiple of 128 */ +- bufsize = ALIGN(GELIC_NET_MAX_MTU, GELIC_NET_RXBUF_ALIGN); + +- /* and we need to have it 128 byte aligned, therefore we allocate a +- * bit more */ +- descr->skb = dev_alloc_skb(bufsize + GELIC_NET_RXBUF_ALIGN - 1); ++ descr->skb = netdev_alloc_skb(*card->netdev, rx_skb_size); + if (!descr->skb) { + descr->buf_addr = 0; /* tell DMAC don't touch memory */ + dev_info(ctodev(card), + "%s:allocate skb failed !!\n", __func__); + return -ENOMEM; + } +- descr->buf_size = cpu_to_be32(bufsize); ++ descr->buf_size = cpu_to_be32(rx_skb_size); + descr->dmac_cmd_status = 0; + descr->result_size = 0; + descr->valid_size = 0; +@@ -412,7 +413,7 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, + /* io-mmu-map the skb */ + descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), + descr->skb->data, +- GELIC_NET_MAX_MTU, ++ GELIC_NET_MAX_FRAME, + DMA_FROM_DEVICE)); + if (!descr->buf_addr) { + dev_kfree_skb_any(descr->skb); +@@ -930,7 +931,7 @@ static void gelic_net_pass_skb_up(struct gelic_descr *descr, + data_error = be32_to_cpu(descr->data_error); + /* unmap skb buffer */ + dma_unmap_single(ctodev(card), be32_to_cpu(descr->buf_addr), +- GELIC_NET_MAX_MTU, ++ GELIC_NET_MAX_FRAME, + DMA_FROM_DEVICE); + + skb_put(skb, be32_to_cpu(descr->valid_size)? +diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.h b/drivers/net/ethernet/toshiba/ps3_gelic_net.h +index fbbf9b54b173b..0e592fc19f6c5 100644 +--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.h ++++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.h +@@ -32,8 +32,9 @@ + #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */ + #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */ + +-#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN +-#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN ++#define GELIC_NET_MAX_FRAME 2312 ++#define GELIC_NET_MAX_MTU 2294 ++#define GELIC_NET_MIN_MTU 64 + #define GELIC_NET_RXBUF_ALIGN 128 + #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */ + #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ +-- +2.39.2 + diff --git a/queue-4.19/net-ps3_gelic_net-use-dma_mapping_error.patch b/queue-4.19/net-ps3_gelic_net-use-dma_mapping_error.patch new file mode 100644 index 00000000000..e14e581d9a8 --- /dev/null +++ b/queue-4.19/net-ps3_gelic_net-use-dma_mapping_error.patch @@ -0,0 +1,89 @@ +From 99e770d6a4e4eeb4f785dead153b52760660c423 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 18 Mar 2023 17:39:16 +0000 +Subject: net/ps3_gelic_net: Use dma_mapping_error + +From: Geoff Levand + +[ Upstream commit bebe933d35a63d4f042fbf4dce4f22e689ba0fcd ] + +The current Gelic Etherenet driver was checking the return value of its +dma_map_single call, and not using the dma_mapping_error() routine. + +Fixes runtime problems like these: + + DMA-API: ps3_gelic_driver sb_05: device driver failed to check map error + WARNING: CPU: 0 PID: 0 at kernel/dma/debug.c:1027 .check_unmap+0x888/0x8dc + +Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") +Reviewed-by: Alexander Duyck +Signed-off-by: Geoff Levand +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/toshiba/ps3_gelic_net.c | 24 +++++++++++--------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c +index 67f61379ba672..572294678faf0 100644 +--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c ++++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c +@@ -330,15 +330,17 @@ static int gelic_card_init_chain(struct gelic_card *card, + + /* set up the hardware pointers in each descriptor */ + for (i = 0; i < no; i++, descr++) { ++ dma_addr_t cpu_addr; ++ + gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE); +- descr->bus_addr = +- dma_map_single(ctodev(card), descr, +- GELIC_DESCR_SIZE, +- DMA_BIDIRECTIONAL); + +- if (!descr->bus_addr) ++ cpu_addr = dma_map_single(ctodev(card), descr, ++ GELIC_DESCR_SIZE, DMA_BIDIRECTIONAL); ++ ++ if (dma_mapping_error(ctodev(card), cpu_addr)) + goto iommu_error; + ++ descr->bus_addr = cpu_to_be32(cpu_addr); + descr->next = descr + 1; + descr->prev = descr - 1; + } +@@ -388,6 +390,7 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, + static const unsigned int rx_skb_size = + ALIGN(GELIC_NET_MAX_FRAME, GELIC_NET_RXBUF_ALIGN) + + GELIC_NET_RXBUF_ALIGN - 1; ++ dma_addr_t cpu_addr; + int offset; + + if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) +@@ -411,11 +414,10 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, + if (offset) + skb_reserve(descr->skb, GELIC_NET_RXBUF_ALIGN - offset); + /* io-mmu-map the skb */ +- descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), +- descr->skb->data, +- GELIC_NET_MAX_FRAME, +- DMA_FROM_DEVICE)); +- if (!descr->buf_addr) { ++ cpu_addr = dma_map_single(ctodev(card), descr->skb->data, ++ GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE); ++ descr->buf_addr = cpu_to_be32(cpu_addr); ++ if (dma_mapping_error(ctodev(card), cpu_addr)) { + dev_kfree_skb_any(descr->skb); + descr->skb = NULL; + dev_info(ctodev(card), +@@ -795,7 +797,7 @@ static int gelic_descr_prepare_tx(struct gelic_card *card, + + buf = dma_map_single(ctodev(card), skb->data, skb->len, DMA_TO_DEVICE); + +- if (!buf) { ++ if (dma_mapping_error(ctodev(card), buf)) { + dev_err(ctodev(card), + "dma map 2 failed (%p, %i). Dropping packet\n", + skb->data, skb->len); +-- +2.39.2 + diff --git a/queue-4.19/net-qcom-emac-fix-use-after-free-bug-in-emac_remove-.patch b/queue-4.19/net-qcom-emac-fix-use-after-free-bug-in-emac_remove-.patch new file mode 100644 index 00000000000..3599a78539e --- /dev/null +++ b/queue-4.19/net-qcom-emac-fix-use-after-free-bug-in-emac_remove-.patch @@ -0,0 +1,63 @@ +From 64212358a2a70e3b053daa9d56487a0364214e84 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 18 Mar 2023 16:05:26 +0800 +Subject: net: qcom/emac: Fix use after free bug in emac_remove due to race + condition + +From: Zheng Wang + +[ Upstream commit 6b6bc5b8bd2d4ca9e1efa9ae0f98a0b0687ace75 ] + +In emac_probe, &adpt->work_thread is bound with +emac_work_thread. Then it will be started by timeout +handler emac_tx_timeout or a IRQ handler emac_isr. + +If we remove the driver which will call emac_remove + to make cleanup, there may be a unfinished work. + +The possible sequence is as follows: + +Fix it by finishing the work before cleanup in the emac_remove +and disable timeout response. + +CPU0 CPU1 + + |emac_work_thread +emac_remove | +free_netdev | +kfree(netdev); | + |emac_reinit_locked + |emac_mac_down + |//use netdev +Fixes: b9b17debc69d ("net: emac: emac gigabit ethernet controller driver") +Signed-off-by: Zheng Wang + +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/qualcomm/emac/emac.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/net/ethernet/qualcomm/emac/emac.c b/drivers/net/ethernet/qualcomm/emac/emac.c +index 76a9b37c8680f..3c764c28d5dbc 100644 +--- a/drivers/net/ethernet/qualcomm/emac/emac.c ++++ b/drivers/net/ethernet/qualcomm/emac/emac.c +@@ -752,9 +752,15 @@ static int emac_remove(struct platform_device *pdev) + struct net_device *netdev = dev_get_drvdata(&pdev->dev); + struct emac_adapter *adpt = netdev_priv(netdev); + ++ netif_carrier_off(netdev); ++ netif_tx_disable(netdev); ++ + unregister_netdev(netdev); + netif_napi_del(&adpt->rx_q.napi); + ++ free_irq(adpt->irq.irq, &adpt->irq); ++ cancel_work_sync(&adpt->work_thread); ++ + emac_clks_teardown(adpt); + + put_device(&adpt->phydev->mdio.dev); +-- +2.39.2 + diff --git a/queue-4.19/net-sonic-use-dma_mapping_error-for-error-check.patch b/queue-4.19/net-sonic-use-dma_mapping_error-for-error-check.patch new file mode 100644 index 00000000000..cdae301dad0 --- /dev/null +++ b/queue-4.19/net-sonic-use-dma_mapping_error-for-error-check.patch @@ -0,0 +1,49 @@ +From 7c274cb51fdbfec39679e186e964c10c4ae4ca22 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Mar 2023 14:45:43 +1100 +Subject: net/sonic: use dma_mapping_error() for error check + +From: Zhang Changzhong + +[ Upstream commit 4107b8746d93ace135b8c4da4f19bbae81db785f ] + +The DMA address returned by dma_map_single() should be checked with +dma_mapping_error(). Fix it accordingly. + +Fixes: efcce839360f ("[PATCH] macsonic/jazzsonic network drivers update") +Signed-off-by: Zhang Changzhong +Tested-by: Stan Johnson +Signed-off-by: Finn Thain +Reviewed-by: Leon Romanovsky +Link: https://lore.kernel.org/r/6645a4b5c1e364312103f48b7b36783b94e197a2.1679370343.git.fthain@linux-m68k.org +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/natsemi/sonic.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/natsemi/sonic.c b/drivers/net/ethernet/natsemi/sonic.c +index 69282f31d519e..fe54bcab705f8 100644 +--- a/drivers/net/ethernet/natsemi/sonic.c ++++ b/drivers/net/ethernet/natsemi/sonic.c +@@ -255,7 +255,7 @@ static int sonic_send_packet(struct sk_buff *skb, struct net_device *dev) + */ + + laddr = dma_map_single(lp->device, skb->data, length, DMA_TO_DEVICE); +- if (!laddr) { ++ if (dma_mapping_error(lp->device, laddr)) { + pr_err_ratelimited("%s: failed to map tx DMA buffer.\n", dev->name); + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; +@@ -473,7 +473,7 @@ static bool sonic_alloc_rb(struct net_device *dev, struct sonic_local *lp, + + *new_addr = dma_map_single(lp->device, skb_put(*new_skb, SONIC_RBSIZE), + SONIC_RBSIZE, DMA_FROM_DEVICE); +- if (!*new_addr) { ++ if (dma_mapping_error(lp->device, *new_addr)) { + dev_kfree_skb(*new_skb); + *new_skb = NULL; + return false; +-- +2.39.2 + diff --git a/queue-4.19/net-usb-smsc95xx-limit-packet-length-to-skb-len.patch b/queue-4.19/net-usb-smsc95xx-limit-packet-length-to-skb-len.patch new file mode 100644 index 00000000000..2f56de2d4a0 --- /dev/null +++ b/queue-4.19/net-usb-smsc95xx-limit-packet-length-to-skb-len.patch @@ -0,0 +1,43 @@ +From f857425147e7c00655c29b456827cb8ea68757a1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Mar 2023 11:19:54 +0100 +Subject: net: usb: smsc95xx: Limit packet length to skb->len + +From: Szymon Heidrich + +[ Upstream commit ff821092cf02a70c2bccd2d19269f01e29aa52cf ] + +Packet length retrieved from descriptor may be larger than +the actual socket buffer length. In such case the cloned +skb passed up the network stack will leak kernel memory contents. + +Fixes: 2f7ca802bdae ("net: Add SMSC LAN9500 USB2.0 10/100 ethernet adapter driver") +Signed-off-by: Szymon Heidrich +Reviewed-by: Jakub Kicinski +Link: https://lore.kernel.org/r/20230316101954.75836-1-szymon.heidrich@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/usb/smsc95xx.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c +index 4f29010e1aeff..0850486864135 100644 +--- a/drivers/net/usb/smsc95xx.c ++++ b/drivers/net/usb/smsc95xx.c +@@ -1950,6 +1950,12 @@ static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) + size = (u16)((header & RX_STS_FL_) >> 16); + align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; + ++ if (unlikely(size > skb->len)) { ++ netif_dbg(dev, rx_err, dev->net, ++ "size err header=0x%08x\n", header); ++ return 0; ++ } ++ + if (unlikely(header & RX_STS_ES_)) { + netif_dbg(dev, rx_err, dev->net, + "Error header=0x%08x\n", header); +-- +2.39.2 + diff --git a/queue-4.19/power-supply-da9150-fix-use-after-free-bug-in-da9150.patch b/queue-4.19/power-supply-da9150-fix-use-after-free-bug-in-da9150.patch new file mode 100644 index 00000000000..71b8064b96d --- /dev/null +++ b/queue-4.19/power-supply-da9150-fix-use-after-free-bug-in-da9150.patch @@ -0,0 +1,55 @@ +From 0935b4a2d5b905c3bb857aa24024d43acc1f6ba5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 12 Mar 2023 01:46:50 +0800 +Subject: power: supply: da9150: Fix use after free bug in + da9150_charger_remove due to race condition + +From: Zheng Wang + +[ Upstream commit 06615d11cc78162dfd5116efb71f29eb29502d37 ] + +In da9150_charger_probe, &charger->otg_work is bound with +da9150_charger_otg_work. da9150_charger_otg_ncb may be +called to start the work. + +If we remove the module which will call da9150_charger_remove +to make cleanup, there may be a unfinished work. The possible +sequence is as follows: + +Fix it by canceling the work before cleanup in the da9150_charger_remove + +CPU0 CPUc1 + + |da9150_charger_otg_work +da9150_charger_remove | +power_supply_unregister | +device_unregister | +power_supply_dev_release| +kfree(psy) | + | + | power_supply_changed(charger->usb); + | //use + +Fixes: c1a281e34dae ("power: Add support for DA9150 Charger") +Signed-off-by: Zheng Wang +Signed-off-by: Sebastian Reichel +Signed-off-by: Sasha Levin +--- + drivers/power/supply/da9150-charger.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/power/supply/da9150-charger.c b/drivers/power/supply/da9150-charger.c +index 60099815296e7..b2d38eb32288a 100644 +--- a/drivers/power/supply/da9150-charger.c ++++ b/drivers/power/supply/da9150-charger.c +@@ -666,6 +666,7 @@ static int da9150_charger_remove(struct platform_device *pdev) + + if (!IS_ERR_OR_NULL(charger->usb_phy)) + usb_unregister_notifier(charger->usb_phy, &charger->otg_nb); ++ cancel_work_sync(&charger->otg_work); + + power_supply_unregister(charger->battery); + power_supply_unregister(charger->usb); +-- +2.39.2 + diff --git a/queue-4.19/qed-qed_sriov-guard-against-null-derefs-from-qed_iov.patch b/queue-4.19/qed-qed_sriov-guard-against-null-derefs-from-qed_iov.patch new file mode 100644 index 00000000000..af8162b60e2 --- /dev/null +++ b/queue-4.19/qed-qed_sriov-guard-against-null-derefs-from-qed_iov.patch @@ -0,0 +1,51 @@ +From 6de2fc9875eec6e2b838ea19dacc177a66f98fc4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Mar 2023 13:29:21 +0300 +Subject: qed/qed_sriov: guard against NULL derefs from qed_iov_get_vf_info + +From: Daniil Tatianin + +[ Upstream commit 25143b6a01d0cc5319edd3de22ffa2578b045550 ] + +We have to make sure that the info returned by the helper is valid +before using it. + +Found by Linux Verification Center (linuxtesting.org) with the SVACE +static analysis tool. + +Fixes: f990c82c385b ("qed*: Add support for ndo_set_vf_trust") +Fixes: 733def6a04bf ("qed*: IOV link control") +Signed-off-by: Daniil Tatianin +Reviewed-by: Michal Swiatkowski +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/qlogic/qed/qed_sriov.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.c b/drivers/net/ethernet/qlogic/qed/qed_sriov.c +index 402c1c3d84ce2..5c8eaded6b30d 100644 +--- a/drivers/net/ethernet/qlogic/qed/qed_sriov.c ++++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.c +@@ -4403,6 +4403,9 @@ qed_iov_configure_min_tx_rate(struct qed_dev *cdev, int vfid, u32 rate) + } + + vf = qed_iov_get_vf_info(QED_LEADING_HWFN(cdev), (u16)vfid, true); ++ if (!vf) ++ return -EINVAL; ++ + vport_id = vf->vport_id; + + return qed_configure_vport_wfq(cdev, vport_id, rate); +@@ -5142,7 +5145,7 @@ static void qed_iov_handle_trust_change(struct qed_hwfn *hwfn) + + /* Validate that the VF has a configured vport */ + vf = qed_iov_get_vf_info(hwfn, i, true); +- if (!vf->vport_instance) ++ if (!vf || !vf->vport_instance) + continue; + + memset(¶ms, 0, sizeof(params)); +-- +2.39.2 + diff --git a/queue-4.19/scsi-scsi_dh_alua-fix-memleak-for-qdata-in-alua_acti.patch b/queue-4.19/scsi-scsi_dh_alua-fix-memleak-for-qdata-in-alua_acti.patch new file mode 100644 index 00000000000..f082f23b256 --- /dev/null +++ b/queue-4.19/scsi-scsi_dh_alua-fix-memleak-for-qdata-in-alua_acti.patch @@ -0,0 +1,61 @@ +From 5eb6aa0a59503b50181157153d17c2a028acd5c4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 15 Mar 2023 14:21:54 +0800 +Subject: scsi: scsi_dh_alua: Fix memleak for 'qdata' in alua_activate() + +From: Yu Kuai + +[ Upstream commit a13faca032acbf2699293587085293bdfaafc8ae ] + +If alua_rtpg_queue() failed from alua_activate(), then 'qdata' is not +freed, which will cause following memleak: + +unreferenced object 0xffff88810b2c6980 (size 32): + comm "kworker/u16:2", pid 635322, jiffies 4355801099 (age 1216426.076s) + hex dump (first 32 bytes): + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 40 39 24 c1 ff ff ff ff 00 f8 ea 0a 81 88 ff ff @9$............. + backtrace: + [<0000000098f3a26d>] alua_activate+0xb0/0x320 + [<000000003b529641>] scsi_dh_activate+0xb2/0x140 + [<000000007b296db3>] activate_path_work+0xc6/0xe0 [dm_multipath] + [<000000007adc9ace>] process_one_work+0x3c5/0x730 + [<00000000c457a985>] worker_thread+0x93/0x650 + [<00000000cb80e628>] kthread+0x1ba/0x210 + [<00000000a1e61077>] ret_from_fork+0x22/0x30 + +Fix the problem by freeing 'qdata' in error path. + +Fixes: 625fe857e4fa ("scsi: scsi_dh_alua: Check scsi_device_get() return value") +Signed-off-by: Yu Kuai +Link: https://lore.kernel.org/r/20230315062154.668812-1-yukuai1@huaweicloud.com +Reviewed-by: Benjamin Block +Reviewed-by: Bart Van Assche +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/device_handler/scsi_dh_alua.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c +index 4cf7c3348bffe..9be913c19a6e0 100644 +--- a/drivers/scsi/device_handler/scsi_dh_alua.c ++++ b/drivers/scsi/device_handler/scsi_dh_alua.c +@@ -1050,10 +1050,12 @@ static int alua_activate(struct scsi_device *sdev, + rcu_read_unlock(); + mutex_unlock(&h->init_mutex); + +- if (alua_rtpg_queue(pg, sdev, qdata, true)) ++ if (alua_rtpg_queue(pg, sdev, qdata, true)) { + fn = NULL; +- else ++ } else { ++ kfree(qdata); + err = SCSI_DH_DEV_OFFLINED; ++ } + kref_put(&pg->kref, release_port_group); + out: + if (fn) +-- +2.39.2 + diff --git a/queue-4.19/series b/queue-4.19/series new file mode 100644 index 00000000000..4123d66df24 --- /dev/null +++ b/queue-4.19/series @@ -0,0 +1,24 @@ +power-supply-da9150-fix-use-after-free-bug-in-da9150.patch +i40evf-change-a-vf-mac-without-reloading-the-vf-driv.patch +intel-ethernet-rename-i40evf-to-iavf.patch +iavf-diet-and-reformat.patch +iavf-fix-inverted-rx-hash-condition-leading-to-disab.patch +intel-igbvf-free-irq-on-the-error-path-in-igbvf_requ.patch +igbvf-regard-vf-reset-nack-as-success.patch +i2c-imx-lpi2c-check-only-for-enabled-interrupt-flags.patch +scsi-scsi_dh_alua-fix-memleak-for-qdata-in-alua_acti.patch +net-usb-smsc95xx-limit-packet-length-to-skb-len.patch +qed-qed_sriov-guard-against-null-derefs-from-qed_iov.patch +xirc2ps_cs-fix-use-after-free-bug-in-xirc2ps_detach.patch +net-qcom-emac-fix-use-after-free-bug-in-emac_remove-.patch +net-ps3_gelic_net-fix-rx-sk_buff-length.patch +net-ps3_gelic_net-use-dma_mapping_error.patch +bpf-adjust-insufficient-default-bpf_jit_limit.patch +net-mlx5-read-the-tc-mapping-of-all-priorities-on-et.patch +atm-idt77252-fix-kmemleak-when-rmmod-idt77252.patch +erspan-do-not-use-skb_mac_header-in-ndo_start_xmit.patch +net-sonic-use-dma_mapping_error-for-error-check.patch +hvc-xen-prevent-concurrent-accesses-to-the-shared-ri.patch +net-mdio-thunder-add-missing-fwnode_handle_put.patch +bluetooth-btqcomsmd-fix-command-timeout-after-settin.patch +bluetooth-btsdio-fix-use-after-free-bug-in-btsdio_re.patch diff --git a/queue-4.19/xirc2ps_cs-fix-use-after-free-bug-in-xirc2ps_detach.patch b/queue-4.19/xirc2ps_cs-fix-use-after-free-bug-in-xirc2ps_detach.patch new file mode 100644 index 00000000000..fa4d8f7ce9e --- /dev/null +++ b/queue-4.19/xirc2ps_cs-fix-use-after-free-bug-in-xirc2ps_detach.patch @@ -0,0 +1,58 @@ +From f5cf52fd9e2af0bd1108689592c480b084ee21ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 Mar 2023 00:15:26 +0800 +Subject: xirc2ps_cs: Fix use after free bug in xirc2ps_detach + +From: Zheng Wang + +[ Upstream commit e8d20c3ded59a092532513c9bd030d1ea66f5f44 ] + +In xirc2ps_probe, the local->tx_timeout_task was bounded +with xirc2ps_tx_timeout_task. When timeout occurs, +it will call xirc_tx_timeout->schedule_work to start the +work. + +When we call xirc2ps_detach to remove the driver, there +may be a sequence as follows: + +Stop responding to timeout tasks and complete scheduled +tasks before cleanup in xirc2ps_detach, which will fix +the problem. + +CPU0 CPU1 + + |xirc2ps_tx_timeout_task +xirc2ps_detach | + free_netdev | + kfree(dev); | + | + | do_reset + | //use dev + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Signed-off-by: Zheng Wang +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/xircom/xirc2ps_cs.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/net/ethernet/xircom/xirc2ps_cs.c b/drivers/net/ethernet/xircom/xirc2ps_cs.c +index fd5288ff53b53..e3438cef5f9c6 100644 +--- a/drivers/net/ethernet/xircom/xirc2ps_cs.c ++++ b/drivers/net/ethernet/xircom/xirc2ps_cs.c +@@ -503,6 +503,11 @@ static void + xirc2ps_detach(struct pcmcia_device *link) + { + struct net_device *dev = link->priv; ++ struct local_info *local = netdev_priv(dev); ++ ++ netif_carrier_off(dev); ++ netif_tx_disable(dev); ++ cancel_work_sync(&local->tx_timeout_task); + + dev_dbg(&link->dev, "detach\n"); + +-- +2.39.2 +