From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 7 Jan 2022 17:07:59 +0000 (+0000)
Subject: hw/intc/arm_gicv3_its: Correct comment about CTE RDBase field size
X-Git-Tag: v7.0.0-rc0~103^2~7
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=257bb6501cda75e9ba0804cd5b45e17275928252;p=thirdparty%2Fqemu.git

hw/intc/arm_gicv3_its: Correct comment about CTE RDBase field size

The comment says that in our CTE format the RDBase field is 36 bits;
in fact for us it is only 16 bits, because we use the RDBase format
where it specifies a 16-bit CPU number. The code already uses
RDBASE_PROCNUM_LENGTH (16) as the field width, so fix the comment
to match it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---

diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 6a3b145f377..14e8ef68e02 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -400,7 +400,7 @@ FIELD(DTE, ITTADDR, 6, 44)
 
 /*
  * 8 bytes Collection Table Entry size
- * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
+ * Valid = 1 bit, RDBase = 16 bits
  */
 #define GITS_CTE_SIZE                 (0x8ULL)
 #define GITS_CTE_RDBASE_PROCNUM_MASK  MAKE_64BIT_MASK(1, RDBASE_PROCNUM_LENGTH)