From: Ville Syrjälä Date: Tue, 8 Oct 2024 21:43:46 +0000 (+0300) Subject: drm/i915/gt: Nuke gen2_irq_{enable,disable}() X-Git-Tag: v6.13-rc1~122^2~16^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=259f5a9d1c80c2b1d10030f77a7d860689f1178a;p=thirdparty%2Fkernel%2Flinux.git drm/i915/gt: Nuke gen2_irq_{enable,disable}() We've determined that accessing the (supposedly) 16bit interrupt registers on gen2 as 32bit works just fine. We already dropped the special case from the main interrupt code, do so also for the gt interrupt stuff. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20241008214349.23331-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 8fe0499308ffe..54077cab8e166 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -290,23 +290,6 @@ int gen4_emit_bb_start(struct i915_request *rq, return 0; } -void gen2_irq_enable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *i915 = engine->i915; - - i915->irq_mask &= ~engine->irq_enable_mask; - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); - ENGINE_POSTING_READ16(engine, RING_IMR); -} - -void gen2_irq_disable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *i915 = engine->i915; - - i915->irq_mask |= engine->irq_enable_mask; - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); -} - void gen3_irq_enable(struct intel_engine_cs *engine) { engine->i915->irq_mask &= ~engine->irq_enable_mask; diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h index a5cd64a65c9e5..2f707620b3d44 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h @@ -28,8 +28,6 @@ int gen4_emit_bb_start(struct i915_request *rq, u64 offset, u32 length, unsigned int dispatch_flags); -void gen2_irq_enable(struct intel_engine_cs *engine); -void gen2_irq_disable(struct intel_engine_cs *engine); void gen3_irq_enable(struct intel_engine_cs *engine); void gen3_irq_disable(struct intel_engine_cs *engine); void gen5_irq_enable(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 72277bc8322e8..694cb79d5452b 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1090,12 +1090,9 @@ static void setup_irq(struct intel_engine_cs *engine) } else if (GRAPHICS_VER(i915) >= 5) { engine->irq_enable = gen5_irq_enable; engine->irq_disable = gen5_irq_disable; - } else if (GRAPHICS_VER(i915) >= 3) { + } else { engine->irq_enable = gen3_irq_enable; engine->irq_disable = gen3_irq_disable; - } else { - engine->irq_enable = gen2_irq_enable; - engine->irq_disable = gen2_irq_disable; } }