From: Miquel Raynal Date: Thu, 3 Apr 2025 09:19:29 +0000 (+0200) Subject: mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips X-Git-Tag: v6.16-rc1~81^2^2~15 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=25e08bf666607f572d5b9b87b0728d126b9bdef9;p=thirdparty%2Flinux.git mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips These chips support single SPI, octal SPI and octal DDR SPI. For now, only the SDR protocols are supported. Tested with the W35N02JW variant, but the 04 one just has twice more dies and is described in the same datasheet, so we can reasonably expect that it will behave identically. Acked-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index c263c9b5affe7..19f8dd4a63707 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -287,6 +287,24 @@ static const struct spinand_info winbond_spinand_table[] = { &update_cache_octal_variants), 0, SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)), + SPINAND_INFO("W35N02JW", /* 1.8V */ + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22), + NAND_MEMORG(1, 4096, 128, 64, 512, 10, 2, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, + &write_cache_octal_variants, + &update_cache_octal_variants), + 0, + SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)), + SPINAND_INFO("W35N04JW", /* 1.8V */ + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23), + NAND_MEMORG(1, 4096, 128, 64, 512, 10, 4, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, + &write_cache_octal_variants, + &update_cache_octal_variants), + 0, + SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)), /* 2G-bit densities */ SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),