From: Marco Chiappero Date: Thu, 7 Apr 2022 16:54:48 +0000 (+0100) Subject: crypto: qat - test PFVF registers for spurious interrupts on GEN4 X-Git-Tag: v5.19-rc1~112^2~90 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=27c0f3a14f9fd16eed4e0167cf58225ca28ab4f8;p=thirdparty%2Flinux.git crypto: qat - test PFVF registers for spurious interrupts on GEN4 Spurious PFVF interrupts can happen when either the ISR is invoked without a valid source being set or, otherwise, when no interrupt bit is set in the PFVF register containing the message. The latter test was present for GEN2 devices but missing for GEN4, this patch fills the gap. Signed-off-by: Marco Chiappero Reviewed-by: Giovanni Cabiddu Signed-off-by: Herbert Xu --- diff --git a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c index d80d493a77568..f7860bf612da9 100644 --- a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c +++ b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c @@ -96,10 +96,16 @@ static struct pfvf_message adf_gen4_pfvf_recv(struct adf_accel_dev *accel_dev, u32 pfvf_offset, u8 compat_ver) { void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); + struct pfvf_message msg = { 0 }; u32 csr_val; /* Read message from the CSR */ csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); + if (!(csr_val & ADF_PFVF_INT)) { + dev_info(&GET_DEV(accel_dev), + "Spurious PFVF interrupt, msg 0x%.8x. Ignored\n", csr_val); + return msg; + } /* We can now acknowledge the message reception by clearing the * interrupt bit