From: Paolo Bonzini Date: Tue, 1 Jun 2021 13:31:38 +0000 (+0200) Subject: target/i386: tcg: fix segment register offsets for 16-bit TSS X-Git-Tag: v6.1.0-rc0~84^2~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=28f6aa1178581c3647819e1abc4905899d97d3a2;p=thirdparty%2Fqemu.git target/i386: tcg: fix segment register offsets for 16-bit TSS The TSS offsets in the manuals have only 2-byte slots for the segment registers. QEMU incorrectly uses 4-byte slots, so that SS overlaps the LDT selector. Resolves: #382 Reported-by: Peter Maydell Signed-off-by: Paolo Bonzini --- diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 2f6cdc8239a..547b9596896 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -281,7 +281,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector, retaddr) | 0xffff0000; } for (i = 0; i < 4; i++) { - new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 4), + new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2), retaddr); } new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr); @@ -349,7 +349,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector, cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr); cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr); for (i = 0; i < 4; i++) { - cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 4), + cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2), env->segs[i].selector, retaddr); } }