From: Shengjiu Wang Date: Sat, 7 May 2022 12:14:13 +0000 (+0800) Subject: ASoC: fsl_micfil: explicitly clear software reset bit X-Git-Tag: v6.1-rc8~15^2^2~2^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=292709b9cf3ba470af94b62c9bb60284cc581b79;p=thirdparty%2Fkernel%2Flinux.git ASoC: fsl_micfil: explicitly clear software reset bit SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined as non volatile register, it still remain in regmap cache after set, then every update of REG_MICFIL_CTRL1, software reset happens. to avoid this, clear it explicitly. Signed-off-by: Shengjiu Wang Link: https://lore.kernel.org/r/1651925654-32060-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown --- diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c index 9f90989ac59a6..cb84d95c3aac1 100644 --- a/sound/soc/fsl/fsl_micfil.c +++ b/sound/soc/fsl/fsl_micfil.c @@ -191,6 +191,17 @@ static int fsl_micfil_reset(struct device *dev) return ret; } + /* + * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined + * as non-volatile register, so SRES still remain in regmap + * cache after set, that every update of REG_MICFIL_CTRL1, + * software reset happens. so clear it explicitly. + */ + ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, + MICFIL_CTRL1_SRES); + if (ret) + return ret; + return 0; }