From: Greg Kroah-Hartman Date: Fri, 24 Nov 2023 15:13:36 +0000 (+0000) Subject: 6.5-stable patches X-Git-Tag: v4.14.331~35 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2986f6e190439687c65983844f851c2f48687646;p=thirdparty%2Fkernel%2Fstable-queue.git 6.5-stable patches added patches: drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch drm-amd-display-fix-dsc-not-enabled-on-direct-mst-sink.patch drm-amd-display-guard-against-invalid-rptr-wptr-being-set.patch drm-amd-pm-fix-error-of-maco-flag-setting-code.patch drm-amdgpu-add-a-retry-for-ip-discovery-init.patch drm-amdgpu-don-t-use-atrm-for-external-devices.patch drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch drm-amdgpu-fix-error-handling-in-amdgpu_vm_init.patch drm-amdgpu-fix-grbm-read-timeout-when-do-mes_self_test.patch drm-amdgpu-fix-possible-null-pointer-dereference.patch drm-amdgpu-lower-cs-errors-to-debug-severity.patch drm-amdgpu-smu13-drop-compute-workload-workaround.patch drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch drm-i915-fix-potential-spectre-vulnerability.patch drm-i915-flush-wc-ggtt-only-on-required-platforms.patch drm-i915-mtl-support-hbr3-rate-with-c10-phy-and-edp-in-mtl.patch --- diff --git a/queue-6.5/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch b/queue-6.5/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch new file mode 100644 index 00000000000..bea2edb0033 --- /dev/null +++ b/queue-6.5/drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch @@ -0,0 +1,208 @@ +From 5911d02cac70d7fb52009fbd37423e63f8f6f9bc Mon Sep 17 00:00:00 2001 +From: Lewis Huang +Date: Thu, 19 Oct 2023 17:22:21 +0800 +Subject: drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox + +From: Lewis Huang + +commit 5911d02cac70d7fb52009fbd37423e63f8f6f9bc upstream. + +[WHY] +Flush command sent to DMCUB spends more time for execution on +a dGPU than on an APU. This causes cursor lag when using high +refresh rate mouses. + +[HOW] +1. Change the DMCUB mailbox memory location from FB to inbox. +2. Only change windows memory to inbox. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Nicholas Kazlauskas +Acked-by: Alex Hung +Signed-off-by: Lewis Huang +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++---- + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 22 +++++++++------ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 32 ++++++++++++++++------ + 3 files changed, 45 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2077,7 +2077,7 @@ static int dm_dmub_sw_init(struct amdgpu + struct dmub_srv_create_params create_params; + struct dmub_srv_region_params region_params; + struct dmub_srv_region_info region_info; +- struct dmub_srv_fb_params fb_params; ++ struct dmub_srv_memory_params memory_params; + struct dmub_srv_fb_info *fb_info; + struct dmub_srv *dmub_srv; + const struct dmcub_firmware_header_v1_0 *hdr; +@@ -2177,6 +2177,7 @@ static int dm_dmub_sw_init(struct amdgpu + adev->dm.dmub_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + + PSP_HEADER_BYTES; ++ region_params.is_mailbox_in_inbox = false; + + status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, + ®ion_info); +@@ -2200,10 +2201,10 @@ static int dm_dmub_sw_init(struct amdgpu + return r; + + /* Rebase the regions on the framebuffer address. */ +- memset(&fb_params, 0, sizeof(fb_params)); +- fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; +- fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; +- fb_params.region_info = ®ion_info; ++ memset(&memory_params, 0, sizeof(memory_params)); ++ memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; ++ memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; ++ memory_params.region_info = ®ion_info; + + adev->dm.dmub_fb_info = + kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); +@@ -2215,7 +2216,7 @@ static int dm_dmub_sw_init(struct amdgpu + return -ENOMEM; + } + +- status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); ++ status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); + if (status != DMUB_STATUS_OK) { + DRM_ERROR("Error calculating DMUB FB info: %d\n", status); + return -EINVAL; +--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h ++++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +@@ -186,6 +186,7 @@ struct dmub_srv_region_params { + uint32_t vbios_size; + const uint8_t *fw_inst_const; + const uint8_t *fw_bss_data; ++ bool is_mailbox_in_inbox; + }; + + /** +@@ -205,20 +206,25 @@ struct dmub_srv_region_params { + */ + struct dmub_srv_region_info { + uint32_t fb_size; ++ uint32_t inbox_size; + uint8_t num_regions; + struct dmub_region regions[DMUB_WINDOW_TOTAL]; + }; + + /** +- * struct dmub_srv_fb_params - parameters used for driver fb setup ++ * struct dmub_srv_memory_params - parameters used for driver fb setup + * @region_info: region info calculated by dmub service +- * @cpu_addr: base cpu address for the framebuffer +- * @gpu_addr: base gpu virtual address for the framebuffer ++ * @cpu_fb_addr: base cpu address for the framebuffer ++ * @cpu_inbox_addr: base cpu address for the gart ++ * @gpu_fb_addr: base gpu virtual address for the framebuffer ++ * @gpu_inbox_addr: base gpu virtual address for the gart + */ +-struct dmub_srv_fb_params { ++struct dmub_srv_memory_params { + const struct dmub_srv_region_info *region_info; +- void *cpu_addr; +- uint64_t gpu_addr; ++ void *cpu_fb_addr; ++ void *cpu_inbox_addr; ++ uint64_t gpu_fb_addr; ++ uint64_t gpu_inbox_addr; + }; + + /** +@@ -545,8 +551,8 @@ dmub_srv_calc_region_info(struct dmub_sr + * DMUB_STATUS_OK - success + * DMUB_STATUS_INVALID - unspecified error + */ +-enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, +- const struct dmub_srv_fb_params *params, ++enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, ++ const struct dmub_srv_memory_params *params, + struct dmub_srv_fb_info *out); + + /** +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -385,7 +385,7 @@ dmub_srv_calc_region_info(struct dmub_sr + uint32_t fw_state_size = DMUB_FW_STATE_SIZE; + uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; + uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; +- ++ uint32_t previous_top = 0; + if (!dmub->sw_init) + return DMUB_STATUS_INVALID; + +@@ -410,8 +410,15 @@ dmub_srv_calc_region_info(struct dmub_sr + bios->base = dmub_align(stack->top, 256); + bios->top = bios->base + params->vbios_size; + +- mail->base = dmub_align(bios->top, 256); +- mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ if (params->is_mailbox_in_inbox) { ++ mail->base = 0; ++ mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ previous_top = bios->top; ++ } else { ++ mail->base = dmub_align(bios->top, 256); ++ mail->top = mail->base + DMUB_MAILBOX_SIZE; ++ previous_top = mail->top; ++ } + + fw_info = dmub_get_fw_meta_info(params); + +@@ -430,7 +437,7 @@ dmub_srv_calc_region_info(struct dmub_sr + dmub->fw_version = fw_info->fw_version; + } + +- trace_buff->base = dmub_align(mail->top, 256); ++ trace_buff->base = dmub_align(previous_top, 256); + trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); + + fw_state->base = dmub_align(trace_buff->top, 256); +@@ -441,11 +448,14 @@ dmub_srv_calc_region_info(struct dmub_sr + + out->fb_size = dmub_align(scratch_mem->top, 4096); + ++ if (params->is_mailbox_in_inbox) ++ out->inbox_size = dmub_align(mail->top, 4096); ++ + return DMUB_STATUS_OK; + } + +-enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, +- const struct dmub_srv_fb_params *params, ++enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, ++ const struct dmub_srv_memory_params *params, + struct dmub_srv_fb_info *out) + { + uint8_t *cpu_base; +@@ -460,8 +470,8 @@ enum dmub_status dmub_srv_calc_fb_info(s + if (params->region_info->num_regions != DMUB_NUM_WINDOWS) + return DMUB_STATUS_INVALID; + +- cpu_base = (uint8_t *)params->cpu_addr; +- gpu_base = params->gpu_addr; ++ cpu_base = (uint8_t *)params->cpu_fb_addr; ++ gpu_base = params->gpu_fb_addr; + + for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { + const struct dmub_region *reg = +@@ -469,6 +479,12 @@ enum dmub_status dmub_srv_calc_fb_info(s + + out->fb[i].cpu_addr = cpu_base + reg->base; + out->fb[i].gpu_addr = gpu_base + reg->base; ++ ++ if (i == DMUB_WINDOW_4_MAILBOX && params->cpu_inbox_addr != 0) { ++ out->fb[i].cpu_addr = (uint8_t *)params->cpu_inbox_addr + reg->base; ++ out->fb[i].gpu_addr = params->gpu_inbox_addr + reg->base; ++ } ++ + out->fb[i].size = reg->top - reg->base; + } + diff --git a/queue-6.5/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch b/queue-6.5/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch new file mode 100644 index 00000000000..16056893b8b --- /dev/null +++ b/queue-6.5/drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch @@ -0,0 +1,51 @@ +From 435f5b369657cffee4b04db1f5805b48599f4dbe Mon Sep 17 00:00:00 2001 +From: Tianci Yin +Date: Wed, 1 Nov 2023 09:47:13 +0800 +Subject: drm/amd/display: Enable fast plane updates on DCN3.2 and above + +From: Tianci Yin + +commit 435f5b369657cffee4b04db1f5805b48599f4dbe upstream. + +[WHY] +When cursor moves across screen boarder, lag cursor observed, +since subvp settings need to sync up with vblank that causes +cursor updates being delayed. + +[HOW] +Enable fast plane updates on DCN3.2 to fix it. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Aurabindo Pillai +Acked-by: Alex Hung +Signed-off-by: Tianci Yin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -9507,14 +9507,14 @@ static bool should_reset_plane(struct dr + struct drm_plane *other; + struct drm_plane_state *old_other_state, *new_other_state; + struct drm_crtc_state *new_crtc_state; ++ struct amdgpu_device *adev = drm_to_adev(plane->dev); + int i; + + /* +- * TODO: Remove this hack once the checks below are sufficient +- * enough to determine when we need to reset all the planes on +- * the stream. ++ * TODO: Remove this hack for all asics once it proves that the ++ * fast updates works fine on DCN3.2+. + */ +- if (state->allow_modeset) ++ if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) + return true; + + /* Exit early if we know that we're adding or removing the plane. */ diff --git a/queue-6.5/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch b/queue-6.5/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch new file mode 100644 index 00000000000..d0814fceaf7 --- /dev/null +++ b/queue-6.5/drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch @@ -0,0 +1,40 @@ +From b71f4ade1b8900d30c661d6c27f87c35214c398c Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 8 Nov 2023 13:31:57 -0600 +Subject: drm/amd/display: fix a NULL pointer dereference in amdgpu_dm_i2c_xfer() + +From: Mario Limonciello + +commit b71f4ade1b8900d30c661d6c27f87c35214c398c upstream. + +When ddc_service_construct() is called, it explicitly checks both the +link type and whether there is something on the link which will +dictate whether the pin is marked as hw_supported. + +If the pin isn't set or the link is not set (such as from +unloading/reloading amdgpu in an IGT test) then fail the +amdgpu_dm_i2c_xfer() call. + +Cc: stable@vger.kernel.org +Fixes: 22676bc500c2 ("drm/amd/display: Fix dmub soft hang for PSR 1") +Link: https://github.com/fwupd/fwupd/issues/6327 +Signed-off-by: Mario Limonciello +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7394,6 +7394,9 @@ static int amdgpu_dm_i2c_xfer(struct i2c + int i; + int result = -EIO; + ++ if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) ++ return result; ++ + cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); + + if (!cmd.payloads) diff --git a/queue-6.5/drm-amd-display-fix-dsc-not-enabled-on-direct-mst-sink.patch b/queue-6.5/drm-amd-display-fix-dsc-not-enabled-on-direct-mst-sink.patch new file mode 100644 index 00000000000..44c67ea62fa --- /dev/null +++ b/queue-6.5/drm-amd-display-fix-dsc-not-enabled-on-direct-mst-sink.patch @@ -0,0 +1,83 @@ +From a58555359a9f870543aaddef277c3396159895ce Mon Sep 17 00:00:00 2001 +From: Fangzhi Zuo +Date: Mon, 23 Oct 2023 13:57:32 -0400 +Subject: drm/amd/display: Fix DSC not Enabled on Direct MST Sink + +From: Fangzhi Zuo + +commit a58555359a9f870543aaddef277c3396159895ce upstream. + +[WHY & HOW] +For the scenario when a dsc capable MST sink device is directly +connected, it needs to use max dsc compression as the link bw constraint. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Roman Li +Acked-by: Alex Hung +Signed-off-by: Fangzhi Zuo +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 29 +++++------- + 1 file changed, 14 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +@@ -1591,31 +1591,31 @@ enum dc_status dm_dp_mst_is_port_support + unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; + unsigned int max_compressed_bw_in_kbps = 0; + struct dc_dsc_bw_range bw_range = {0}; +- struct drm_dp_mst_topology_mgr *mst_mgr; ++ uint16_t full_pbn = aconnector->mst_output_port->full_pbn; + + /* +- * check if the mode could be supported if DSC pass-through is supported +- * AND check if there enough bandwidth available to support the mode +- * with DSC enabled. ++ * Consider the case with the depth of the mst topology tree is equal or less than 2 ++ * A. When dsc bitstream can be transmitted along the entire path ++ * 1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND ++ * 2. dsc passthrough supported at MST branch, or ++ * 3. dsc decoding supported at leaf MST device ++ * Use maximum dsc compression as bw constraint ++ * B. When dsc bitstream cannot be transmitted along the entire path ++ * Use native bw as bw constraint + */ + if (is_dsc_common_config_possible(stream, &bw_range) && +- aconnector->mst_output_port->passthrough_aux) { +- mst_mgr = aconnector->mst_output_port->mgr; +- mutex_lock(&mst_mgr->lock); +- ++ (aconnector->mst_output_port->passthrough_aux || ++ aconnector->dsc_aux == &aconnector->mst_output_port->aux)) { + cur_link_settings = stream->link->verified_link_cap; + + upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, +- &cur_link_settings +- ); +- down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn); ++ &cur_link_settings); ++ down_link_bw_in_kbps = kbps_from_pbn(full_pbn); + + /* pick the bottleneck */ + end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, + down_link_bw_in_kbps); + +- mutex_unlock(&mst_mgr->lock); +- + /* + * use the maximum dsc compression bandwidth as the required + * bandwidth for the mode +@@ -1630,8 +1630,7 @@ enum dc_status dm_dp_mst_is_port_support + /* check if mode could be supported within full_pbn */ + bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); +- +- if (pbn > aconnector->mst_output_port->full_pbn) ++ if (pbn > full_pbn) + return DC_FAIL_BANDWIDTH_VALIDATE; + } + diff --git a/queue-6.5/drm-amd-display-guard-against-invalid-rptr-wptr-being-set.patch b/queue-6.5/drm-amd-display-guard-against-invalid-rptr-wptr-being-set.patch new file mode 100644 index 00000000000..acce307ee24 --- /dev/null +++ b/queue-6.5/drm-amd-display-guard-against-invalid-rptr-wptr-being-set.patch @@ -0,0 +1,63 @@ +From 1ffa8602e39b89469dc703ebab7a7e44c33da0f7 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Wed, 13 Sep 2023 16:18:44 -0400 +Subject: drm/amd/display: Guard against invalid RPTR/WPTR being set + +From: Nicholas Kazlauskas + +commit 1ffa8602e39b89469dc703ebab7a7e44c33da0f7 upstream. + +[WHY] +HW can return invalid values on register read, guard against these being +set and causing us to access memory out of range and page fault. + +[HOW] +Guard at sync_inbox1 and guard at pushing commands. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Hansen Dsouza +Acked-by: Alex Hung +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -657,9 +657,16 @@ enum dmub_status dmub_srv_sync_inbox1(st + return DMUB_STATUS_INVALID; + + if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { +- dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); +- dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); +- dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; ++ uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); ++ uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); ++ ++ if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { ++ return DMUB_STATUS_HW_FAILURE; ++ } else { ++ dmub->inbox1_rb.rptr = rptr; ++ dmub->inbox1_rb.wrpt = wptr; ++ dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; ++ } + } + + return DMUB_STATUS_OK; +@@ -693,6 +700,11 @@ enum dmub_status dmub_srv_cmd_queue(stru + if (!dmub->hw_init) + return DMUB_STATUS_INVALID; + ++ if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || ++ dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) { ++ return DMUB_STATUS_HW_FAILURE; ++ } ++ + if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) + return DMUB_STATUS_OK; + diff --git a/queue-6.5/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch b/queue-6.5/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch new file mode 100644 index 00000000000..74e9694b974 --- /dev/null +++ b/queue-6.5/drm-amd-pm-fix-error-of-maco-flag-setting-code.patch @@ -0,0 +1,60 @@ +From 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 Mon Sep 17 00:00:00 2001 +From: Ma Jun +Date: Tue, 31 Oct 2023 11:11:04 +0800 +Subject: drm/amd/pm: Fix error of MACO flag setting code + +From: Ma Jun + +commit 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 upstream. + +MACO only works if BACO is supported + +Signed-off-by: Ma Jun +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 ++++---- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 9 +++++---- + 2 files changed, 9 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -343,12 +343,12 @@ static int smu_v13_0_0_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) +- smu_baco->maco_support = true; ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ smu_baco->maco_support = true; ++ } + + /* + * We are in the transition to a new OD mechanism. +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -333,12 +333,13 @@ static int smu_v13_0_7_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) +- smu_baco->maco_support = true; ++ if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) ++ smu_baco->maco_support = true; ++ } + + #if 0 + if (!overdrive_lowerlimits->FeatureCtrlMask || diff --git a/queue-6.5/drm-amdgpu-add-a-retry-for-ip-discovery-init.patch b/queue-6.5/drm-amdgpu-add-a-retry-for-ip-discovery-init.patch new file mode 100644 index 00000000000..2c47b0d6b00 --- /dev/null +++ b/queue-6.5/drm-amdgpu-add-a-retry-for-ip-discovery-init.patch @@ -0,0 +1,77 @@ +From 3938eb956e383ef88b8fc7d556492336ebee52df Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 19 Oct 2023 13:56:56 -0400 +Subject: drm/amdgpu: add a retry for IP discovery init + +From: Alex Deucher + +commit 3938eb956e383ef88b8fc7d556492336ebee52df upstream. + +AMD dGPUs have integrated FW that runs as soon as the +device gets power and initializes the board (determines +the amount of memory, provides configuration details to +the driver, etc.). For direct PCIe attached cards this +happens as soon as power is applied and normally completes +well before the OS has even started loading. However, with +hotpluggable ports like USB4, the driver needs to wait for +this to complete before initializing the device. + +This normally takes 60-100ms, but could take longer on +some older boards periodically due to memory training. + +Retry for up to a second. In the non-hotplug case, there +should be no change in behavior and this should complete +on the first try. + +v2: adjust test criteria +v3: adjust checks for the masks, only enable on removable devices +v4: skip bif_fb_en check + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 23 +++++++++++++++++++++-- + 1 file changed, 21 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -92,6 +92,7 @@ + MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); + + #define mmRCC_CONFIG_MEMSIZE 0xde3 ++#define mmMP0_SMN_C2PMSG_33 0x16061 + #define mmMM_INDEX 0x0 + #define mmMM_INDEX_HI 0x6 + #define mmMM_DATA 0x1 +@@ -230,8 +231,26 @@ static int amdgpu_discovery_read_binary_ + static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, + uint8_t *binary) + { +- uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; +- int ret = 0; ++ uint64_t vram_size; ++ u32 msg; ++ int i, ret = 0; ++ ++ /* It can take up to a second for IFWI init to complete on some dGPUs, ++ * but generally it should be in the 60-100ms range. Normally this starts ++ * as soon as the device gets power so by the time the OS loads this has long ++ * completed. However, when a card is hotplugged via e.g., USB4, we need to ++ * wait for this to complete. Once the C2PMSG is updated, we can ++ * continue. ++ */ ++ if (dev_is_removable(&adev->pdev->dev)) { ++ for (i = 0; i < 1000; i++) { ++ msg = RREG32(mmMP0_SMN_C2PMSG_33); ++ if (msg & 0x80000000) ++ break; ++ msleep(1); ++ } ++ } ++ vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; + + if (vram_size) { + uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; diff --git a/queue-6.5/drm-amdgpu-don-t-use-atrm-for-external-devices.patch b/queue-6.5/drm-amdgpu-don-t-use-atrm-for-external-devices.patch new file mode 100644 index 00000000000..5f2b6150ae2 --- /dev/null +++ b/queue-6.5/drm-amdgpu-don-t-use-atrm-for-external-devices.patch @@ -0,0 +1,48 @@ +From 432e664e7c98c243fab4c3c95bd463bea3aeed28 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 17 Oct 2023 15:40:01 -0400 +Subject: drm/amdgpu: don't use ATRM for external devices + +From: Alex Deucher + +commit 432e664e7c98c243fab4c3c95bd463bea3aeed28 upstream. + +The ATRM ACPI method is for fetching the dGPU vbios rom +image on laptops and all-in-one systems. It should not be +used for external add in cards. If the dGPU is thunderbolt +connected, don't try ATRM. + +v2: pci_is_thunderbolt_attached only works for Intel. Use + pdev->external_facing instead. +v3: dev_is_removable() seems to be what we want + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +@@ -29,6 +29,7 @@ + #include "amdgpu.h" + #include "atom.h" + ++#include + #include + #include + #include +@@ -287,6 +288,10 @@ static bool amdgpu_atrm_get_bios(struct + if (adev->flags & AMD_IS_APU) + return false; + ++ /* ATRM is for on-platform devices only */ ++ if (dev_is_removable(&adev->pdev->dev)) ++ return false; ++ + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) diff --git a/queue-6.5/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch b/queue-6.5/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch new file mode 100644 index 00000000000..99a2206e263 --- /dev/null +++ b/queue-6.5/drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch @@ -0,0 +1,96 @@ +From 7b1c6263eaf4fd64ffe1cafdc504a42ee4bfbb33 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 17 Oct 2023 16:30:00 -0400 +Subject: drm/amdgpu: don't use pci_is_thunderbolt_attached() + +From: Alex Deucher + +commit 7b1c6263eaf4fd64ffe1cafdc504a42ee4bfbb33 upstream. + +It's only valid on Intel systems with the Intel VSEC. +Use dev_is_removable() instead. This should do the right +thing regardless of the platform. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- + drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 5 +++-- + 2 files changed, 7 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -43,6 +43,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2233,7 +2234,6 @@ out: + */ + static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) + { +- struct drm_device *dev = adev_to_drm(adev); + struct pci_dev *parent; + int i, r; + bool total; +@@ -2304,7 +2304,7 @@ static int amdgpu_device_ip_early_init(s + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && + ((adev->flags & AMD_IS_APU) == 0) && +- !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) ++ !dev_is_removable(&adev->pdev->dev)) + adev->flags |= AMD_IS_PX; + + if (!(adev->flags & AMD_IS_APU)) { +@@ -4132,7 +4132,7 @@ fence_driver_init: + + px = amdgpu_device_supports_px(ddev); + +- if (px || (!pci_is_thunderbolt_attached(adev->pdev) && ++ if (px || (!dev_is_removable(&adev->pdev->dev) && + apple_gmux_detect(NULL, NULL))) + vga_switcheroo_register_client(adev->pdev, + &amdgpu_switcheroo_ops, px); +@@ -4278,7 +4278,7 @@ void amdgpu_device_fini_sw(struct amdgpu + + px = amdgpu_device_supports_px(adev_to_drm(adev)); + +- if (px || (!pci_is_thunderbolt_attached(adev->pdev) && ++ if (px || (!dev_is_removable(&adev->pdev->dev) && + apple_gmux_detect(NULL, NULL))) + vga_switcheroo_unregister_client(adev->pdev); + +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +@@ -28,6 +28,7 @@ + #include "nbio/nbio_2_3_offset.h" + #include "nbio/nbio_2_3_sh_mask.h" + #include ++#include + #include + + #define smnPCIE_CONFIG_CNTL 0x11180044 +@@ -361,7 +362,7 @@ static void nbio_v2_3_enable_aspm(struct + + data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; + +- if (pci_is_thunderbolt_attached(adev->pdev)) ++ if (dev_is_removable(&adev->pdev->dev)) + data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + else + data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; +@@ -480,7 +481,7 @@ static void nbio_v2_3_program_aspm(struc + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); + data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; +- if (pci_is_thunderbolt_attached(adev->pdev)) ++ if (dev_is_removable(&adev->pdev->dev)) + data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + else + data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; diff --git a/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch b/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch new file mode 100644 index 00000000000..cdd4cac08f8 --- /dev/null +++ b/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch @@ -0,0 +1,35 @@ +From 12f76050d8d4d10dab96333656b821bd4620d103 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Thu, 9 Nov 2023 10:12:39 +0100 +Subject: drm/amdgpu: fix error handling in amdgpu_bo_list_get() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 12f76050d8d4d10dab96333656b821bd4620d103 upstream. + +We should not leak the pointer where we couldn't grab the reference +on to the caller because it can be that the error handling still +tries to put the reference then. + +Signed-off-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +@@ -179,6 +179,7 @@ int amdgpu_bo_list_get(struct amdgpu_fpr + } + + rcu_read_unlock(); ++ *result = NULL; + return -ENOENT; + } + diff --git a/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_vm_init.patch b/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_vm_init.patch new file mode 100644 index 00000000000..414d250ab84 --- /dev/null +++ b/queue-6.5/drm-amdgpu-fix-error-handling-in-amdgpu_vm_init.patch @@ -0,0 +1,91 @@ +From 8473bfdcb5b1a32fd05629c4535ccacd73bc5567 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Tue, 31 Oct 2023 15:35:27 +0100 +Subject: drm/amdgpu: fix error handling in amdgpu_vm_init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 8473bfdcb5b1a32fd05629c4535ccacd73bc5567 upstream. + +When clearing the root PD fails we need to properly release it again. + +Signed-off-by: Christian König +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 ++++++++++++++++--------------- + 1 file changed, 16 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -2129,7 +2129,8 @@ long amdgpu_vm_wait_idle(struct amdgpu_v + * Returns: + * 0 for success, error for failure. + */ +-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) ++int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ++ int32_t xcp_id) + { + struct amdgpu_bo *root_bo; + struct amdgpu_bo_vm *root; +@@ -2148,6 +2149,7 @@ int amdgpu_vm_init(struct amdgpu_device + INIT_LIST_HEAD(&vm->done); + INIT_LIST_HEAD(&vm->pt_freed); + INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work); ++ INIT_KFIFO(vm->faults); + + r = amdgpu_vm_init_entities(adev, vm); + if (r) +@@ -2182,34 +2184,33 @@ int amdgpu_vm_init(struct amdgpu_device + false, &root, xcp_id); + if (r) + goto error_free_delayed; +- root_bo = &root->bo; ++ ++ root_bo = amdgpu_bo_ref(&root->bo); + r = amdgpu_bo_reserve(root_bo, true); +- if (r) +- goto error_free_root; ++ if (r) { ++ amdgpu_bo_unref(&root->shadow); ++ amdgpu_bo_unref(&root_bo); ++ goto error_free_delayed; ++ } + ++ amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); + r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + if (r) +- goto error_unreserve; +- +- amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); ++ goto error_free_root; + + r = amdgpu_vm_pt_clear(adev, vm, root, false); + if (r) +- goto error_unreserve; ++ goto error_free_root; + + amdgpu_bo_unreserve(vm->root.bo); +- +- INIT_KFIFO(vm->faults); ++ amdgpu_bo_unref(&root_bo); + + return 0; + +-error_unreserve: +- amdgpu_bo_unreserve(vm->root.bo); +- + error_free_root: +- amdgpu_bo_unref(&root->shadow); ++ amdgpu_vm_pt_free_root(adev, vm); ++ amdgpu_bo_unreserve(vm->root.bo); + amdgpu_bo_unref(&root_bo); +- vm->root.bo = NULL; + + error_free_delayed: + dma_fence_put(vm->last_tlb_flush); diff --git a/queue-6.5/drm-amdgpu-fix-grbm-read-timeout-when-do-mes_self_test.patch b/queue-6.5/drm-amdgpu-fix-grbm-read-timeout-when-do-mes_self_test.patch new file mode 100644 index 00000000000..61063577246 --- /dev/null +++ b/queue-6.5/drm-amdgpu-fix-grbm-read-timeout-when-do-mes_self_test.patch @@ -0,0 +1,60 @@ +From 36e7ff5c13cb15cb7b06c76d42bb76cbf6b7ea75 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Wed, 1 Nov 2023 14:22:04 +0800 +Subject: drm/amdgpu: fix GRBM read timeout when do mes_self_test + +From: Tim Huang + +commit 36e7ff5c13cb15cb7b06c76d42bb76cbf6b7ea75 upstream. + +Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers +can be touched when initialize the compute and gfx mqd in mes_self_test. +Otherwise, we expect no response from CP and an GRBM eventual timeout. + +Signed-off-by: Tim Huang +Acked-by: Alex Deucher +Reviewed-by: Yifan Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +@@ -627,8 +627,20 @@ static void amdgpu_mes_queue_init_mqd(st + mqd_prop.hqd_queue_priority = p->hqd_queue_priority; + mqd_prop.hqd_active = false; + ++ if (p->queue_type == AMDGPU_RING_TYPE_GFX || ++ p->queue_type == AMDGPU_RING_TYPE_COMPUTE) { ++ mutex_lock(&adev->srbm_mutex); ++ amdgpu_gfx_select_me_pipe_q(adev, p->ring->me, p->ring->pipe, 0, 0, 0); ++ } ++ + mqd_mgr->init_mqd(adev, q->mqd_cpu_ptr, &mqd_prop); + ++ if (p->queue_type == AMDGPU_RING_TYPE_GFX || ++ p->queue_type == AMDGPU_RING_TYPE_COMPUTE) { ++ amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0); ++ mutex_unlock(&adev->srbm_mutex); ++ } ++ + amdgpu_bo_unreserve(q->mqd_obj); + } + +@@ -1062,9 +1074,13 @@ int amdgpu_mes_add_ring(struct amdgpu_de + switch (queue_type) { + case AMDGPU_RING_TYPE_GFX: + ring->funcs = adev->gfx.gfx_ring[0].funcs; ++ ring->me = adev->gfx.gfx_ring[0].me; ++ ring->pipe = adev->gfx.gfx_ring[0].pipe; + break; + case AMDGPU_RING_TYPE_COMPUTE: + ring->funcs = adev->gfx.compute_ring[0].funcs; ++ ring->me = adev->gfx.compute_ring[0].me; ++ ring->pipe = adev->gfx.compute_ring[0].pipe; + break; + case AMDGPU_RING_TYPE_SDMA: + ring->funcs = adev->sdma.instance[0].ring.funcs; diff --git a/queue-6.5/drm-amdgpu-fix-possible-null-pointer-dereference.patch b/queue-6.5/drm-amdgpu-fix-possible-null-pointer-dereference.patch new file mode 100644 index 00000000000..c43458f458c --- /dev/null +++ b/queue-6.5/drm-amdgpu-fix-possible-null-pointer-dereference.patch @@ -0,0 +1,37 @@ +From 256503071c2de2b5b5c20e06654aa9a44f13aa62 Mon Sep 17 00:00:00 2001 +From: Felix Kuehling +Date: Tue, 31 Oct 2023 13:30:00 -0400 +Subject: drm/amdgpu: Fix possible null pointer dereference +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Felix Kuehling + +commit 256503071c2de2b5b5c20e06654aa9a44f13aa62 upstream. + +mem = bo->tbo.resource may be NULL in amdgpu_vm_bo_update. + +Fixes: 180253782038 ("drm/ttm: stop allocating dummy resources during BO creation") +Signed-off-by: Felix Kuehling +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -1099,8 +1099,8 @@ int amdgpu_vm_bo_update(struct amdgpu_de + bo = gem_to_amdgpu_bo(gobj); + } + mem = bo->tbo.resource; +- if (mem->mem_type == TTM_PL_TT || +- mem->mem_type == AMDGPU_PL_PREEMPT) ++ if (mem && (mem->mem_type == TTM_PL_TT || ++ mem->mem_type == AMDGPU_PL_PREEMPT)) + pages_addr = bo->tbo.ttm->dma_address; + } + diff --git a/queue-6.5/drm-amdgpu-lower-cs-errors-to-debug-severity.patch b/queue-6.5/drm-amdgpu-lower-cs-errors-to-debug-severity.patch new file mode 100644 index 00000000000..ac04e7cd1de --- /dev/null +++ b/queue-6.5/drm-amdgpu-lower-cs-errors-to-debug-severity.patch @@ -0,0 +1,34 @@ +From 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Thu, 9 Nov 2023 10:14:14 +0100 +Subject: drm/amdgpu: lower CS errors to debug severity +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 upstream. + +Otherwise userspace can spam the logs by using incorrect input values. + +Signed-off-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1438,7 +1438,7 @@ int amdgpu_cs_ioctl(struct drm_device *d + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS && r != -EAGAIN) +- DRM_ERROR("Failed to process the buffer list %d!\n", r); ++ DRM_DEBUG("Failed to process the buffer list %d!\n", r); + goto error_fini; + } + diff --git a/queue-6.5/drm-amdgpu-smu13-drop-compute-workload-workaround.patch b/queue-6.5/drm-amdgpu-smu13-drop-compute-workload-workaround.patch new file mode 100644 index 00000000000..3b10902108f --- /dev/null +++ b/queue-6.5/drm-amdgpu-smu13-drop-compute-workload-workaround.patch @@ -0,0 +1,63 @@ +From 23170863ea0a0965d224342c0eb2ad8303b1f267 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 1 Nov 2023 15:48:14 -0400 +Subject: drm/amdgpu/smu13: drop compute workload workaround + +From: Alex Deucher + +commit 23170863ea0a0965d224342c0eb2ad8303b1f267 upstream. + +This was fixed in PMFW before launch and is no longer +required. + +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 32 +------------------ + 1 file changed, 2 insertions(+), 30 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2162,38 +2162,10 @@ static int smu_v13_0_0_set_power_profile + } + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE && +- (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) || +- ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) { +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_COMPUTE_BIT, +- (void *)(&activity_monitor_external), +- false); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); +- return ret; +- } +- +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_CUSTOM_BIT, +- (void *)(&activity_monitor_external), +- true); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); +- return ret; +- } +- +- workload_type = smu_cmn_to_asic_specific_index(smu, +- CMN2ASIC_MAPPING_WORKLOAD, +- PP_SMC_POWER_PROFILE_CUSTOM); +- } else { +- /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ +- workload_type = smu_cmn_to_asic_specific_index(smu, ++ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ ++ workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + smu->power_profile_mode); +- } + + if (workload_type < 0) + return -EINVAL; diff --git a/queue-6.5/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch b/queue-6.5/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch new file mode 100644 index 00000000000..e25109f27e4 --- /dev/null +++ b/queue-6.5/drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch @@ -0,0 +1,62 @@ +From 0cb89cd42fd22bbdec0b046c48f35775f5b88bdb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 31 Oct 2023 18:08:00 +0200 +Subject: drm/i915: Bump GLK CDCLK frequency when driving multiple pipes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 0cb89cd42fd22bbdec0b046c48f35775f5b88bdb upstream. + +On GLK CDCLK frequency needs to be at least 2*96 MHz when accessing +the audio hardware. Currently we bump the CDCLK frequency up +temporarily (if not high enough already) whenever audio hardware +is being accessed, and drop it back down afterwards. + +With a single active pipe this works just fine as we can switch +between all the valid CDCLK frequencies by changing the cd2x +divider, which doesn't require a full modeset. However with +multiple active pipes the cd2x divider trick no longer works, +and thus we end up blinking all displays off and back on. + +To avoid this let's just bump the CDCLK frequency to >=2*96MHz +whenever multiple pipes are active. The downside is slightly +higher power consumption, but that seems like an acceptable +tradeoff. With a single active pipe we can stick to the current +more optiomal (from power comsumption POV) behaviour. + +Cc: stable@vger.kernel.org +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9599 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231031160800.18371-1-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit 451eaa1a614c911f5a51078dcb68022874e4cb12) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_cdclk.c ++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c +@@ -2680,6 +2680,18 @@ static int intel_compute_min_cdclk(struc + for_each_pipe(dev_priv, pipe) + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); + ++ /* ++ * Avoid glk_force_audio_cdclk() causing excessive screen ++ * blinking when multiple pipes are active by making sure ++ * CDCLK frequency is always high enough for audio. With a ++ * single active pipe we can always change CDCLK frequency ++ * by changing the cd2x divider (see glk_cdclk_table[]) and ++ * thus a full modeset won't be needed then. ++ */ ++ if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && ++ !is_power_of_2(cdclk_state->active_pipes)) ++ min_cdclk = max(2 * 96000, min_cdclk); ++ + if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { + drm_dbg_kms(&dev_priv->drm, + "required cdclk (%d kHz) exceeds max (%d kHz)\n", diff --git a/queue-6.5/drm-i915-fix-potential-spectre-vulnerability.patch b/queue-6.5/drm-i915-fix-potential-spectre-vulnerability.patch new file mode 100644 index 00000000000..1879f8633f8 --- /dev/null +++ b/queue-6.5/drm-i915-fix-potential-spectre-vulnerability.patch @@ -0,0 +1,36 @@ +From 1a8e9bad6ef563c28ab0f8619628d5511be55431 Mon Sep 17 00:00:00 2001 +From: Kunwu Chan +Date: Fri, 3 Nov 2023 11:09:22 +0000 +Subject: drm/i915: Fix potential spectre vulnerability + +From: Kunwu Chan + +commit 1a8e9bad6ef563c28ab0f8619628d5511be55431 upstream. + +Fix smatch warning: +drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu() +warn: potential spectre issue 'pc->user_engines' [r] (local cap) + +Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create parameters (v5)") +Cc: # v5.15+ +Signed-off-by: Kunwu Chan +Reviewed-by: Tvrtko Ursulin +Signed-off-by: Tvrtko Ursulin +Link: https://patchwork.freedesktop.org/patch/msgid/20231103110922.430122-1-tvrtko.ursulin@linux.intel.com +(cherry picked from commit 27b086382c22efb7e0a16442f7bdc2e120108ef3) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c +@@ -844,6 +844,7 @@ static int set_proto_ctx_sseu(struct drm + if (idx >= pc->num_user_engines) + return -EINVAL; + ++ idx = array_index_nospec(idx, pc->num_user_engines); + pe = &pc->user_engines[idx]; + + /* Only render engine supports RPCS configuration. */ diff --git a/queue-6.5/drm-i915-flush-wc-ggtt-only-on-required-platforms.patch b/queue-6.5/drm-i915-flush-wc-ggtt-only-on-required-platforms.patch new file mode 100644 index 00000000000..ce80df20a10 --- /dev/null +++ b/queue-6.5/drm-i915-flush-wc-ggtt-only-on-required-platforms.patch @@ -0,0 +1,107 @@ +From 7d7a328d0e8d6edefb7b0d665185d468667588d0 Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Wed, 18 Oct 2023 11:38:15 +0200 +Subject: drm/i915: Flush WC GGTT only on required platforms +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nirmoy Das + +commit 7d7a328d0e8d6edefb7b0d665185d468667588d0 upstream. + +gen8_ggtt_invalidate() is only needed for limited set of platforms +where GGTT is mapped as WC. This was added as way to fix WC based GGTT in +commit 0f9b91c754b7 ("drm/i915: flush system agent TLBs on SNB") and +there are no reference in HW docs that forces us to use this on non-WC +backed GGTT. + +This can also cause unwanted side-effects on XE_HP platforms where +GFX_FLSH_CNTL_GEN6 is not valid anymore. + +v2: Add a func to detect wc ggtt detection (Ville) +v3: Improve commit log and add reference commit (Daniel) + +Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") +Cc: Rodrigo Vivi +Cc: Tvrtko Ursulin +Cc: Joonas Lahtinen +Cc: Jani Nikula +Cc: Jonathan Cavitt +Cc: John Harrison +Cc: Andi Shyti +Cc: Ville Syrjälä +Cc: Daniel Vetter +Cc: # v6.2+ +Suggested-by: Matt Roper +Signed-off-by: Nirmoy Das +Reviewed-by: Matt Roper +Reviewed-by: Andi Shyti +Link: https://patchwork.freedesktop.org/patch/msgid/20231018093815.1349-1-nirmoy.das@intel.com +(cherry picked from commit 81de3e296b10a13e5c9f13172825b0d8d9495c68) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gt/intel_ggtt.c | 35 ++++++++++++++++++++++++----------- + 1 file changed, 24 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c +@@ -190,6 +190,21 @@ void gen6_ggtt_invalidate(struct i915_gg + spin_unlock_irq(&uncore->lock); + } + ++static bool needs_wc_ggtt_mapping(struct drm_i915_private *i915) ++{ ++ /* ++ * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range ++ * will be dropped. For WC mappings in general we have 64 byte burst ++ * writes when the WC buffer is flushed, so we can't use it, but have to ++ * resort to an uncached mapping. The WC issue is easily caught by the ++ * readback check when writing GTT PTE entries. ++ */ ++ if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11) ++ return true; ++ ++ return false; ++} ++ + static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt) + { + struct intel_uncore *uncore = ggtt->vm.gt->uncore; +@@ -197,8 +212,12 @@ static void gen8_ggtt_invalidate(struct + /* + * Note that as an uncached mmio write, this will flush the + * WCB of the writes into the GGTT before it triggers the invalidate. ++ * ++ * Only perform this when GGTT is mapped as WC, see ggtt_probe_common(). + */ +- intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); ++ if (needs_wc_ggtt_mapping(ggtt->vm.i915)) ++ intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, ++ GFX_FLSH_CNTL_EN); + } + + static void guc_ggtt_invalidate(struct i915_ggtt *ggtt) +@@ -902,17 +921,11 @@ static int ggtt_probe_common(struct i915 + GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); + phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915); + +- /* +- * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range +- * will be dropped. For WC mappings in general we have 64 byte burst +- * writes when the WC buffer is flushed, so we can't use it, but have to +- * resort to an uncached mapping. The WC issue is easily caught by the +- * readback check when writing GTT PTE entries. +- */ +- if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11) +- ggtt->gsm = ioremap(phys_addr, size); +- else ++ if (needs_wc_ggtt_mapping(i915)) + ggtt->gsm = ioremap_wc(phys_addr, size); ++ else ++ ggtt->gsm = ioremap(phys_addr, size); ++ + if (!ggtt->gsm) { + drm_err(&i915->drm, "Failed to map the ggtt page table\n"); + return -ENOMEM; diff --git a/queue-6.5/drm-i915-mtl-support-hbr3-rate-with-c10-phy-and-edp-in-mtl.patch b/queue-6.5/drm-i915-mtl-support-hbr3-rate-with-c10-phy-and-edp-in-mtl.patch new file mode 100644 index 00000000000..af12b27e335 --- /dev/null +++ b/queue-6.5/drm-i915-mtl-support-hbr3-rate-with-c10-phy-and-edp-in-mtl.patch @@ -0,0 +1,39 @@ +From ce4941c2d6459664761c9854701015d8e99414fb Mon Sep 17 00:00:00 2001 +From: Chaitanya Kumar Borah +Date: Wed, 18 Oct 2023 17:06:22 +0530 +Subject: drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL + +From: Chaitanya Kumar Borah + +commit ce4941c2d6459664761c9854701015d8e99414fb upstream. + +eDP specification supports HBR3 link rate since v1.4a. Moreover, +C10 phy can support HBR3 link rate for both DP and eDP. Therefore, +do not clamp the supported rates for eDP at 6.75Gbps. + +Cc: + +BSpec: 70073 74224 + +Signed-off-by: Chaitanya Kumar Borah +Reviewed-by: Mika Kahola +Signed-off-by: Mika Kahola +Link: https://patchwork.freedesktop.org/patch/msgid/20231018113622.2761997-1-chaitanya.kumar.borah@intel.com +(cherry picked from commit a3431650f30a94b179d419ef87c21213655c28cd) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct in + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); + + if (intel_is_c10phy(i915, phy)) +- return intel_dp_is_edp(intel_dp) ? 675000 : 810000; ++ return 810000; + + return 2000000; + } diff --git a/queue-6.5/series b/queue-6.5/series index b333ce9a045..dca5066a96d 100644 --- a/queue-6.5/series +++ b/queue-6.5/series @@ -470,3 +470,22 @@ ext4-properly-sync-file-size-update-after-o_sync-direct-io.patch ext4-fix-racy-may-inline-data-check-in-dio-write.patch drm-amd-pm-handle-non-terminated-overdrive-commands.patch drm-bridge-it66121-get_edid-callback-must-not-return-err-pointers.patch +drm-i915-mtl-support-hbr3-rate-with-c10-phy-and-edp-in-mtl.patch +drm-i915-bump-glk-cdclk-frequency-when-driving-multiple-pipes.patch +drm-i915-fix-potential-spectre-vulnerability.patch +drm-i915-flush-wc-ggtt-only-on-required-platforms.patch +drm-amd-pm-fix-error-of-maco-flag-setting-code.patch +drm-amdgpu-smu13-drop-compute-workload-workaround.patch +drm-amdgpu-don-t-use-pci_is_thunderbolt_attached.patch +drm-amdgpu-fix-grbm-read-timeout-when-do-mes_self_test.patch +drm-amdgpu-add-a-retry-for-ip-discovery-init.patch +drm-amdgpu-don-t-use-atrm-for-external-devices.patch +drm-amdgpu-fix-error-handling-in-amdgpu_vm_init.patch +drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch +drm-amdgpu-lower-cs-errors-to-debug-severity.patch +drm-amdgpu-fix-possible-null-pointer-dereference.patch +drm-amd-display-guard-against-invalid-rptr-wptr-being-set.patch +drm-amd-display-fix-dsc-not-enabled-on-direct-mst-sink.patch +drm-amd-display-fix-a-null-pointer-dereference-in-amdgpu_dm_i2c_xfer.patch +drm-amd-display-enable-fast-plane-updates-on-dcn3.2-and-above.patch +drm-amd-display-change-the-dmcub-mailbox-memory-location-from-fb-to-inbox.patch