From: Greg Kroah-Hartman Date: Sat, 23 Aug 2025 08:07:39 +0000 (+0200) Subject: 6.12-stable patches X-Git-Tag: v6.16.3~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=29a28c9b04ac51e8a2d7bb8f2ab2f4b5bd95a8a3;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch drm-amd-display-avoid-a-null-pointer-dereference.patch drm-amd-display-don-t-overclock-dce-6-by-15.patch drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch drm-amdgpu-swm14-update-power-limit-logic.patch --- diff --git a/queue-6.12/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch b/queue-6.12/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch new file mode 100644 index 0000000000..dc89f2a738 --- /dev/null +++ b/queue-6.12/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch @@ -0,0 +1,44 @@ +From a44458dfd5bc0c79c6739c3f4c658361d3a5126b Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Wed, 21 Aug 2024 01:10:28 +0200 +Subject: accel/habanalabs/gaudi2: Use kvfree() for memory allocated with kvcalloc() + +From: Thorsten Blum + +commit a44458dfd5bc0c79c6739c3f4c658361d3a5126b upstream. + +Use kvfree() to fix the following Coccinelle/coccicheck warning reported +by kfree_mismatch.cocci: + + WARNING kvmalloc is used to allocate this memory at line 10398 + +Fixes: f728c17fc97a ("accel/habanalabs/gaudi2: move HMMU page tables to device memory") +Reported-by: Qianfeng Rong +Closes: https://patch.msgid.link/20250808085530.233737-1-rongqianfeng@vivo.com +Signed-off-by: Thorsten Blum +[lukas: acknowledge Qianfeng, adjust Thorsten's domain, add Fixes tag] +Signed-off-by: Lukas Wunner +Reviewed-by: Tomer Tayar +Cc: stable@vger.kernel.org # v6.9+ +Link: https://patch.msgid.link/20240820231028.136126-1-thorsten.blum@toblux.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/accel/habanalabs/gaudi2/gaudi2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c +index a38b88baadf2..5722e4128d3c 100644 +--- a/drivers/accel/habanalabs/gaudi2/gaudi2.c ++++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c +@@ -10437,7 +10437,7 @@ static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 siz + (u64 *)(lin_dma_pkts_arr), DEBUGFS_WRITE64); + WREG32(sob_addr, 0); + +- kfree(lin_dma_pkts_arr); ++ kvfree(lin_dma_pkts_arr); + + return rc; + } +-- +2.50.1 + diff --git a/queue-6.12/drm-amd-display-avoid-a-null-pointer-dereference.patch b/queue-6.12/drm-amd-display-avoid-a-null-pointer-dereference.patch new file mode 100644 index 0000000000..25cc8a4ca3 --- /dev/null +++ b/queue-6.12/drm-amd-display-avoid-a-null-pointer-dereference.patch @@ -0,0 +1,42 @@ +From 07b93a5704b0b72002f0c4bd1076214af67dc661 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Thu, 24 Jul 2025 15:00:43 -0500 +Subject: drm/amd/display: Avoid a NULL pointer dereference + +From: Mario Limonciello + +commit 07b93a5704b0b72002f0c4bd1076214af67dc661 upstream. + +[WHY] +Although unlikely drm_atomic_get_new_connector_state() or +drm_atomic_get_old_connector_state() can return NULL. + +[HOW] +Check returns before dereference. + +Cc: Mario Limonciello +Cc: Alex Deucher +Reviewed-by: Harry Wentland +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Hung +Tested-by: Dan Wheeler +Signed-off-by: Alex Deucher +(cherry picked from commit 1e5e8d672fec9f2ab352be121be971877bff2af9) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7583,6 +7583,9 @@ amdgpu_dm_connector_atomic_check(struct + struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); + int ret; + ++ if (WARN_ON(unlikely(!old_con_state || !new_con_state))) ++ return -EINVAL; ++ + trace_amdgpu_dm_connector_atomic_check(new_con_state); + + if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { diff --git a/queue-6.12/drm-amd-display-don-t-overclock-dce-6-by-15.patch b/queue-6.12/drm-amd-display-don-t-overclock-dce-6-by-15.patch new file mode 100644 index 0000000000..e7dd612d12 --- /dev/null +++ b/queue-6.12/drm-amd-display-don-t-overclock-dce-6-by-15.patch @@ -0,0 +1,53 @@ +From cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:46 +0200 +Subject: drm/amd/display: Don't overclock DCE 6 by 15% +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 upstream. + +The extra 15% clock was added as a workaround for a Polaris issue +which uses DCE 11, and should not have been used on DCE 6 which +is already hardcoded to the highest possible display clock. +Unfortunately, the extra 15% was mistakenly copied and kept +even on code paths which don't affect Polaris. + +This commit fixes that and also adds a check to make sure +not to exceed the maximum DCE 6 display clock. + +Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") +Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") +Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)") +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 427980c1cbd22bb256b9385f5ce73c0937562408) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -123,11 +123,9 @@ static void dce60_update_clocks(struct c + { + struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dm_pp_power_level_change_request level_change_req; +- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; +- +- /*TODO: W/A for dal3 linux, investigate why this works */ +- if (!clk_mgr_dce->dfs_bypass_active) +- patched_disp_clk = patched_disp_clk * 115 / 100; ++ const int max_disp_clk = ++ clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; ++ int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); + + level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); + /* get max clock state from PPLIB */ diff --git a/queue-6.12/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch b/queue-6.12/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch new file mode 100644 index 0000000000..a4732da766 --- /dev/null +++ b/queue-6.12/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch @@ -0,0 +1,78 @@ +From 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:49 +0200 +Subject: drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 upstream. + +Also needed by DCE 6. +This way the code that gathers this info can be shared between +different DCE versions and doesn't have to be repeated. + +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 8107432dff37db26fcb641b6cebeae8981cd73a0) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 -- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++------- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 -- + 3 files changed, 3 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +@@ -386,8 +386,6 @@ static void dce_pplib_apply_display_requ + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +- pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -124,6 +124,9 @@ void dce110_fill_display_configs( + int j; + int num_cfgs = 0; + ++ pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); ++ pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; ++ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; + pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; + + for (j = 0; j < context->stream_count; j++) { +@@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requireme + pp_display_cfg->min_engine_clock_deep_sleep_khz + = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; + +- pp_display_cfg->avail_mclk_switch_time_us = +- dce110_get_min_vblank_time_us(context); +- /* TODO: dce11.2*/ +- pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; +- +- pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -100,8 +100,6 @@ static void dce60_pplib_apply_display_re + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +- pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) diff --git a/queue-6.12/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch b/queue-6.12/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch new file mode 100644 index 0000000000..770957d000 --- /dev/null +++ b/queue-6.12/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch @@ -0,0 +1,84 @@ +From 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:48 +0200 +Subject: drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 upstream. + +dce110_fill_display_configs is shared between DCE 6-11, and +finding the first CRTC and its line time is relevant to DCE 6 too. +Move the code to find it from DCE 11 specific code. + +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 4ab09785f8d5d03df052827af073d5c508ff5f63) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 30 ++++++---- + 1 file changed, 20 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -120,9 +120,12 @@ void dce110_fill_display_configs( + const struct dc_state *context, + struct dm_pp_display_configuration *pp_display_cfg) + { ++ struct dc *dc = context->clk_mgr->ctx->dc; + int j; + int num_cfgs = 0; + ++ pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; ++ + for (j = 0; j < context->stream_count; j++) { + int k; + +@@ -164,6 +167,23 @@ void dce110_fill_display_configs( + cfg->v_refresh /= stream->timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) + / stream->timing.v_total; ++ ++ /* Find first CRTC index and calculate its line time. ++ * This is necessary for DPM on SI GPUs. ++ */ ++ if (cfg->pipe_idx < pp_display_cfg->crtc_index) { ++ const struct dc_crtc_timing *timing = ++ &context->streams[0]->timing; ++ ++ pp_display_cfg->crtc_index = cfg->pipe_idx; ++ pp_display_cfg->line_time_in_us = ++ timing->h_total * 10000 / timing->pix_clk_100hz; ++ } ++ } ++ ++ if (!num_cfgs) { ++ pp_display_cfg->crtc_index = 0; ++ pp_display_cfg->line_time_in_us = 0; + } + + pp_display_cfg->display_count = num_cfgs; +@@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requireme + + dce110_fill_display_configs(context, pp_display_cfg); + +- /* TODO: is this still applicable?*/ +- if (pp_display_cfg->display_count == 1) { +- const struct dc_crtc_timing *timing = +- &context->streams[0]->timing; +- +- pp_display_cfg->crtc_index = +- pp_display_cfg->disp_configs[0].pipe_idx; +- pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; +- } +- + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) + dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); + } diff --git a/queue-6.12/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch b/queue-6.12/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch new file mode 100644 index 0000000000..b74556a61f --- /dev/null +++ b/queue-6.12/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch @@ -0,0 +1,91 @@ +From 297a4833a68aac3316eb808b4123eb016ef242d7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Sat, 2 Aug 2025 17:51:53 +0200 +Subject: drm/amd/display: Fix DP audio DTO1 clock source on DCE 6. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 297a4833a68aac3316eb808b4123eb016ef242d7 upstream. + +On DCE 6, DP audio was not working. However, it worked when an +HDMI monitor was also plugged in. + +Looking at dce_aud_wall_dto_setup it seems that the main +difference is that we use DTO1 when only DP is plugged in. + +When programming DTO1, it uses audio_dto_source_clock_in_khz +which is set from get_dp_ref_freq_khz + +The dce60_get_dp_ref_freq_khz implementation looks incorrect, +because DENTIST_DISPCLK_CNTL seems to be always zero on DCE 6, +so it isn't usable. +I compared dce60_get_dp_ref_freq_khz to the legacy display code, +specifically dce_v6_0_audio_set_dto, and it turns out that in +case of DCE 6, it needs to use the display clock. With that, +DP audio started working on Pitcairn, Oland and Cape Verde. + +However, it still didn't work on Tahiti. Despite having the +same DCE version, Tahiti seems to have a different audio device. +After some trial and error I realized that it works with the +default display clock as reported by the VBIOS, not the current +display clock. + +The patch was tested on all four SI GPUs: + +* Pitcairn (DCE 6.0) +* Oland (DCE 6.4) +* Cape Verde (DCE 6.0) +* Tahiti (DCE 6.0 but different) + +The testing was done on Samsung Odyssey G7 LS28BG700EPXEN on +each of the above GPUs, at the following settings: + +* 4K 60 Hz +* 1080p 60 Hz +* 1080p 144 Hz + +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Timur Kristóf +Signed-off-by: Alex Deucher +(cherry picked from commit 645cc7863da5de700547d236697dffd6760cf051) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 21 +++-------- + 1 file changed, 6 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -83,22 +83,13 @@ static const struct state_dependent_cloc + static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) + { + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); +- int dprefclk_wdivider; +- int dp_ref_clk_khz; +- int target_div; ++ struct dc_context *ctx = clk_mgr_base->ctx; ++ int dp_ref_clk_khz = 0; + +- /* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */ +- +- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently +- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ +- REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); +- +- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ +- target_div = dentist_get_divider_from_did(dprefclk_wdivider); +- +- /* Calculate the current DFS clock, in kHz.*/ +- dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR +- * clk_mgr->base.dentist_vco_freq_khz) / target_div; ++ if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) ++ dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; ++ else ++ dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; + + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); + } diff --git a/queue-6.12/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch b/queue-6.12/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch new file mode 100644 index 0000000000..a5e5b3705d --- /dev/null +++ b/queue-6.12/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch @@ -0,0 +1,53 @@ +From 10507478468f165ea681605d133991ed05cdff62 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:52 +0200 +Subject: drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 10507478468f165ea681605d133991ed05cdff62 upstream. + +For later VBIOS versions, the fractional feedback divider is +calculated as the remainder of dividing the feedback divider by +a factor, which is set to 1000000. For reference, see: +- calculate_fb_and_fractional_fb_divider +- calc_pll_max_vco_construct + +However, in case of old VBIOS versions that have +set_pixel_clock_v3, they only have 1 byte available for the +fractional feedback divider, and it's expected to be set to the +remainder from dividing the feedback divider by 10. +For reference see the legacy display code: +- amdgpu_pll_compute +- amdgpu_atombios_crtc_program_pll + +This commit fixes set_pixel_clock_v3 by dividing the fractional +feedback divider passed to the function by 100000. + +Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 027e7acc7e17802ebf28e1edb88a404836ad50d6) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c +@@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3 + allocation.sPCLKInput.usFbDiv = + cpu_to_le16((uint16_t)bp_params->feedback_divider); + allocation.sPCLKInput.ucFracFbDiv = +- (uint8_t)bp_params->fractional_feedback_divider; ++ (uint8_t)(bp_params->fractional_feedback_divider / 100000); + allocation.sPCLKInput.ucPostDiv = + (uint8_t)bp_params->pixel_clock_post_divider; + diff --git a/queue-6.12/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch b/queue-6.12/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch new file mode 100644 index 0000000000..6d4d33a31a --- /dev/null +++ b/queue-6.12/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch @@ -0,0 +1,62 @@ +From 66af73a1c319336694a8610fe4c2943f7b33066c Mon Sep 17 00:00:00 2001 +From: Tom Chung +Date: Fri, 18 Jul 2025 18:25:08 +0800 +Subject: drm/amd/display: Fix Xorg desktop unresponsive on Replay panel + +From: Tom Chung + +commit 66af73a1c319336694a8610fe4c2943f7b33066c upstream. + +[WHY & HOW] +IPS & self-fresh feature can cause vblank counter resets between +vblank disable and enable. +It may cause system stuck due to wait the vblank counter. + +Call the drm_crtc_vblank_restore() during vblank enable to estimate +missed vblanks by using timestamps and update the vblank counter in +DRM. + +It can make the vblank counter increase smoothly and resolve this issue. + +Cc: Mario Limonciello +Cc: Alex Deucher +Reviewed-by: Sun peng (Leo) Li +Signed-off-by: Tom Chung +Signed-off-by: Alex Hung +Tested-by: Dan Wheeler +Signed-off-by: Alex Deucher +(cherry picked from commit 34d66bc7ff10e146a4cec76cf286979740a10954) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 19 +++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +@@ -302,6 +302,25 @@ static inline int amdgpu_dm_crtc_set_vbl + irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); + + if (enable) { ++ struct dc *dc = adev->dm.dc; ++ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); ++ struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; ++ struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; ++ bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || ++ pr->config.replay_supported; ++ ++ /* ++ * IPS & self-refresh feature can cause vblank counter resets between ++ * vblank disable and enable. ++ * It may cause system stuck due to waiting for the vblank counter. ++ * Call this function to estimate missed vblanks by using timestamps and ++ * update the vblank counter in DRM. ++ */ ++ if (dc->caps.ips_support && ++ dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && ++ sr_supported && vblank->config.disable_immediate) ++ drm_crtc_vblank_restore(crtc); ++ + /* vblank irq on -> Only need vupdate irq in vrr mode */ + if (amdgpu_dm_crtc_vrr_active(acrtc_state)) + rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); diff --git a/queue-6.12/drm-amdgpu-swm14-update-power-limit-logic.patch b/queue-6.12/drm-amdgpu-swm14-update-power-limit-logic.patch new file mode 100644 index 0000000000..84c17887b5 --- /dev/null +++ b/queue-6.12/drm-amdgpu-swm14-update-power-limit-logic.patch @@ -0,0 +1,72 @@ +From 79e25cd06e85105c75701ef1773c6c64bb304091 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 8 Aug 2025 13:12:07 -0400 +Subject: drm/amdgpu/swm14: Update power limit logic + +From: Alex Deucher + +commit 79e25cd06e85105c75701ef1773c6c64bb304091 upstream. + +Take into account the limits from the vbios. Ported +from the SMU13 code. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4352 +Reviewed-by: Jesse Zhang +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +(cherry picked from commit 203cc7f1dd86f2c8de5c3c6182f19adac7c9c206) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 30 +++++++++++++++---- + 1 file changed, 25 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -1668,9 +1668,11 @@ static int smu_v14_0_2_get_power_limit(s + uint32_t *min_power_limit) + { + struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_14_0_2_powerplay_table *powerplay_table = ++ table_context->power_play_table; + PPTable_t *pptable = table_context->driver_pptable; + CustomSkuTable_t *skutable = &pptable->CustomSkuTable; +- uint32_t power_limit; ++ uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; + uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; + + if (smu_v14_0_get_current_power_limit(smu, &power_limit)) +@@ -1683,11 +1685,29 @@ static int smu_v14_0_2_get_power_limit(s + if (default_power_limit) + *default_power_limit = power_limit; + +- if (max_power_limit) +- *max_power_limit = msg_limit; ++ if (powerplay_table) { ++ if (smu->od_enabled && ++ smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { ++ od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt; ++ od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; ++ } else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { ++ od_percent_upper = 0; ++ od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; ++ } ++ } + +- if (min_power_limit) +- *min_power_limit = 0; ++ dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", ++ od_percent_upper, od_percent_lower, power_limit); ++ ++ if (max_power_limit) { ++ *max_power_limit = msg_limit * (100 + od_percent_upper); ++ *max_power_limit /= 100; ++ } ++ ++ if (min_power_limit) { ++ *min_power_limit = power_limit * (100 + od_percent_lower); ++ *min_power_limit /= 100; ++ } + + return 0; + } diff --git a/queue-6.12/series b/queue-6.12/series index d6c783531d..beef3abfcd 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -176,3 +176,12 @@ rdma-rxe-flush-delayed-skbs-while-releasing-rxe-resources.patch s390-sclp-fix-sccb-present-check.patch platform-x86-intel-uncore-freq-check-write-blocked-for-elc.patch kvm-retry-nx_huge_page_recovery_thread-creation.patch +accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch +drm-amdgpu-swm14-update-power-limit-logic.patch +drm-amd-display-avoid-a-null-pointer-dereference.patch +drm-amd-display-don-t-overclock-dce-6-by-15.patch +drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch +drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch +drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch +drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch +drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch