From: Greg Kroah-Hartman Date: Fri, 25 Jun 2021 09:29:49 +0000 (+0200) Subject: 5.12-stable patches X-Git-Tag: v5.12.14~53 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2a7a7e923100ef5e11226902c89b64af409019e2;p=thirdparty%2Fkernel%2Fstable-queue.git 5.12-stable patches added patches: arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch drm-add-a-locked-version-of-drm_is_current_master.patch drm-amdgpu-wait-for-moving-fence-after-pinning.patch drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch drm-radeon-wait-for-moving-fence-after-pinning.patch mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch --- diff --git a/queue-5.12/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch b/queue-5.12/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch new file mode 100644 index 00000000000..e756d4f90df --- /dev/null +++ b/queue-5.12/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch @@ -0,0 +1,81 @@ +From dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 14 May 2021 11:26:37 +0100 +Subject: ARM: 9081/1: fix gcc-10 thumb2-kernel regression + +From: Arnd Bergmann + +commit dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 upstream. + +When building the kernel wtih gcc-10 or higher using the +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly +different set of registers for the inline assembly in cpu_init() that +subsequently results in a corrupt kernel stack as well as remaining in +FIQ mode. If a banked register is used for the last argument, the wrong +version of that register gets loaded into CPSR_c. When building in Arm +mode, the arguments are passed as immediate values and the bug cannot +happen. + +This got introduced when Daniel reworked the FIQ handling and was +technically always broken, but happened to work with both clang and gcc +before gcc-10 as long as they picked one of the lower registers. +This is probably an indication that still very few people build the +kernel in Thumb2 mode. + +Marek pointed out the problem on IRC, Arnd narrowed it down to this +inline assembly and Russell pinpointed the exact bug. + +Change the constraints to force the final mode switch to use a non-banked +register for the argument to ensure that the correct constant gets loaded. +Another alternative would be to always use registers for the constant +arguments to avoid the #ifdef that has now become more complex. + +Cc: # v3.18+ +Cc: Daniel Thompson +Reported-by: Marek Vasut +Acked-by: Ard Biesheuvel +Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler") +Signed-off-by: Arnd Bergmann +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/kernel/setup.c | 16 +++++++++------- + 1 file changed, 9 insertions(+), 7 deletions(-) + +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -545,9 +545,11 @@ void notrace cpu_init(void) + * In Thumb-2, msr with an immediate value is not allowed. + */ + #ifdef CONFIG_THUMB2_KERNEL +-#define PLC "r" ++#define PLC_l "l" ++#define PLC_r "r" + #else +-#define PLC "I" ++#define PLC_l "I" ++#define PLC_r "I" + #endif + + /* +@@ -569,15 +571,15 @@ void notrace cpu_init(void) + "msr cpsr_c, %9" + : + : "r" (stk), +- PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), + "I" (offsetof(struct stack, irq[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), + "I" (offsetof(struct stack, abt[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), + "I" (offsetof(struct stack, und[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), + "I" (offsetof(struct stack, fiq[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) ++ PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) + : "r14"); + #endif + } diff --git a/queue-5.12/drm-add-a-locked-version-of-drm_is_current_master.patch b/queue-5.12/drm-add-a-locked-version-of-drm_is_current_master.patch new file mode 100644 index 00000000000..71262397b30 --- /dev/null +++ b/queue-5.12/drm-add-a-locked-version-of-drm_is_current_master.patch @@ -0,0 +1,121 @@ +From 1815d9c86e3090477fbde066ff314a7e9721ee0f Mon Sep 17 00:00:00 2001 +From: Desmond Cheong Zhi Xi +Date: Sun, 20 Jun 2021 19:03:26 +0800 +Subject: drm: add a locked version of drm_is_current_master + +From: Desmond Cheong Zhi Xi + +commit 1815d9c86e3090477fbde066ff314a7e9721ee0f upstream. + +While checking the master status of the DRM file in +drm_is_current_master(), the device's master mutex should be +held. Without the mutex, the pointer fpriv->master may be freed +concurrently by another process calling drm_setmaster_ioctl(). This +could lead to use-after-free errors when the pointer is subsequently +dereferenced in drm_lease_owner(). + +The callers of drm_is_current_master() from drm_auth.c hold the +device's master mutex, but external callers do not. Hence, we implement +drm_is_current_master_locked() to be used within drm_auth.c, and +modify drm_is_current_master() to grab the device's master mutex +before checking the master status. + +Reported-by: Daniel Vetter +Signed-off-by: Desmond Cheong Zhi Xi +Reviewed-by: Emil Velikov +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Vetter +Link: https://patchwork.freedesktop.org/patch/msgid/20210620110327.4964-2-desmondcheongzx@gmail.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/drm_auth.c | 51 ++++++++++++++++++++++++++++----------------- + 1 file changed, 32 insertions(+), 19 deletions(-) + +--- a/drivers/gpu/drm/drm_auth.c ++++ b/drivers/gpu/drm/drm_auth.c +@@ -61,6 +61,35 @@ + * trusted clients. + */ + ++static bool drm_is_current_master_locked(struct drm_file *fpriv) ++{ ++ lockdep_assert_held_once(&fpriv->master->dev->master_mutex); ++ ++ return fpriv->is_master && drm_lease_owner(fpriv->master) == fpriv->minor->dev->master; ++} ++ ++/** ++ * drm_is_current_master - checks whether @priv is the current master ++ * @fpriv: DRM file private ++ * ++ * Checks whether @fpriv is current master on its device. This decides whether a ++ * client is allowed to run DRM_MASTER IOCTLs. ++ * ++ * Most of the modern IOCTL which require DRM_MASTER are for kernel modesetting ++ * - the current master is assumed to own the non-shareable display hardware. ++ */ ++bool drm_is_current_master(struct drm_file *fpriv) ++{ ++ bool ret; ++ ++ mutex_lock(&fpriv->master->dev->master_mutex); ++ ret = drm_is_current_master_locked(fpriv); ++ mutex_unlock(&fpriv->master->dev->master_mutex); ++ ++ return ret; ++} ++EXPORT_SYMBOL(drm_is_current_master); ++ + int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv) + { + struct drm_auth *auth = data; +@@ -223,7 +252,7 @@ int drm_setmaster_ioctl(struct drm_devic + if (ret) + goto out_unlock; + +- if (drm_is_current_master(file_priv)) ++ if (drm_is_current_master_locked(file_priv)) + goto out_unlock; + + if (dev->master) { +@@ -272,7 +301,7 @@ int drm_dropmaster_ioctl(struct drm_devi + if (ret) + goto out_unlock; + +- if (!drm_is_current_master(file_priv)) { ++ if (!drm_is_current_master_locked(file_priv)) { + ret = -EINVAL; + goto out_unlock; + } +@@ -321,7 +350,7 @@ void drm_master_release(struct drm_file + if (file_priv->magic) + idr_remove(&file_priv->master->magic_map, file_priv->magic); + +- if (!drm_is_current_master(file_priv)) ++ if (!drm_is_current_master_locked(file_priv)) + goto out; + + drm_legacy_lock_master_cleanup(dev, master); +@@ -343,22 +372,6 @@ out: + } + + /** +- * drm_is_current_master - checks whether @priv is the current master +- * @fpriv: DRM file private +- * +- * Checks whether @fpriv is current master on its device. This decides whether a +- * client is allowed to run DRM_MASTER IOCTLs. +- * +- * Most of the modern IOCTL which require DRM_MASTER are for kernel modesetting +- * - the current master is assumed to own the non-shareable display hardware. +- */ +-bool drm_is_current_master(struct drm_file *fpriv) +-{ +- return fpriv->is_master && drm_lease_owner(fpriv->master) == fpriv->minor->dev->master; +-} +-EXPORT_SYMBOL(drm_is_current_master); +- +-/** + * drm_master_get - reference a master pointer + * @master: &struct drm_master + * diff --git a/queue-5.12/drm-amdgpu-wait-for-moving-fence-after-pinning.patch b/queue-5.12/drm-amdgpu-wait-for-moving-fence-after-pinning.patch new file mode 100644 index 00000000000..b8a0275ed5c --- /dev/null +++ b/queue-5.12/drm-amdgpu-wait-for-moving-fence-after-pinning.patch @@ -0,0 +1,50 @@ +From 8ddf5b9bb479570a3825d70fecfb9399bc15700c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 21 Jun 2021 14:29:14 +0200 +Subject: drm/amdgpu: wait for moving fence after pinning +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 8ddf5b9bb479570a3825d70fecfb9399bc15700c upstream. + +We actually need to wait for the moving fence after pinning +the BO to make sure that the pin is completed. + +Signed-off-by: Christian König +Reviewed-by: Daniel Vetter +References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/ +CC: stable@kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-3-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +@@ -214,9 +214,21 @@ static int amdgpu_dma_buf_pin(struct dma + { + struct drm_gem_object *obj = attach->dmabuf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); ++ int r; + + /* pin buffer into GTT */ +- return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); ++ r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); ++ if (r) ++ return r; ++ ++ if (bo->tbo.moving) { ++ r = dma_fence_wait(bo->tbo.moving, true); ++ if (r) { ++ amdgpu_bo_unpin(bo); ++ return r; ++ } ++ } ++ return 0; + } + + /** diff --git a/queue-5.12/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch b/queue-5.12/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch new file mode 100644 index 00000000000..429e9b4e97d --- /dev/null +++ b/queue-5.12/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch @@ -0,0 +1,53 @@ +From 17b11f71795abdce46f62a808f906857e525cea8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 21 Jun 2021 13:36:35 +0200 +Subject: drm/nouveau: wait for moving fence after pinning v2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 17b11f71795abdce46f62a808f906857e525cea8 upstream. + +We actually need to wait for the moving fence after pinning +the BO to make sure that the pin is completed. + +v2: grab the lock while waiting + +Signed-off-by: Christian König +Reviewed-by: Daniel Vetter +References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/ +CC: stable@kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-1-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/nouveau/nouveau_prime.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/nouveau/nouveau_prime.c ++++ b/drivers/gpu/drm/nouveau/nouveau_prime.c +@@ -93,7 +93,22 @@ int nouveau_gem_prime_pin(struct drm_gem + if (ret) + return -EINVAL; + +- return 0; ++ ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); ++ if (ret) ++ goto error; ++ ++ if (nvbo->bo.moving) ++ ret = dma_fence_wait(nvbo->bo.moving, true); ++ ++ ttm_bo_unreserve(&nvbo->bo); ++ if (ret) ++ goto error; ++ ++ return ret; ++ ++error: ++ nouveau_bo_unpin(nvbo); ++ return ret; + } + + void nouveau_gem_prime_unpin(struct drm_gem_object *obj) diff --git a/queue-5.12/drm-radeon-wait-for-moving-fence-after-pinning.patch b/queue-5.12/drm-radeon-wait-for-moving-fence-after-pinning.patch new file mode 100644 index 00000000000..54d2f2518be --- /dev/null +++ b/queue-5.12/drm-radeon-wait-for-moving-fence-after-pinning.patch @@ -0,0 +1,49 @@ +From 4b41726aae563273bb4b4a9462ba51ce4d372f78 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 21 Jun 2021 13:43:05 +0200 +Subject: drm/radeon: wait for moving fence after pinning +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 4b41726aae563273bb4b4a9462ba51ce4d372f78 upstream. + +We actually need to wait for the moving fence after pinning +the BO to make sure that the pin is completed. + +Signed-off-by: Christian König +Reviewed-by: Daniel Vetter +References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/ +CC: stable@kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-2-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/radeon/radeon_prime.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_prime.c ++++ b/drivers/gpu/drm/radeon/radeon_prime.c +@@ -77,9 +77,19 @@ int radeon_gem_prime_pin(struct drm_gem_ + + /* pin buffer into GTT */ + ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL); +- if (likely(ret == 0)) +- bo->prime_shared_count++; ++ if (unlikely(ret)) ++ goto error; + ++ if (bo->tbo.moving) { ++ ret = dma_fence_wait(bo->tbo.moving, false); ++ if (unlikely(ret)) { ++ radeon_bo_unpin(bo); ++ goto error; ++ } ++ } ++ ++ bo->prime_shared_count++; ++error: + radeon_bo_unreserve(bo); + return ret; + } diff --git a/queue-5.12/mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch b/queue-5.12/mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch new file mode 100644 index 00000000000..873bc097199 --- /dev/null +++ b/queue-5.12/mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch @@ -0,0 +1,118 @@ +From 103a5348c22c3fca8b96c735a9e353b8a0801842 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Wed, 9 Jun 2021 17:02:30 +0200 +Subject: mmc: meson-gx: use memcpy_to/fromio for dram-access-quirk + +From: Neil Armstrong + +commit 103a5348c22c3fca8b96c735a9e353b8a0801842 upstream. + +It has been reported that usage of memcpy() to/from an iomem mapping is invalid, +and a recent arm64 memcpy update [1] triggers a memory abort when dram-access-quirk +is used on the G12A/G12B platforms. + +This adds a local sg_copy_to_buffer which makes usage of io versions of memcpy +when dram-access-quirk is enabled. + +[1] 285133040e6c ("arm64: Import latest memcpy()/memmove() implementation") + +Fixes: acdc8e71d9bb ("mmc: meson-gx: add dram-access-quirk") +Reported-by: Marek Szyprowski +Suggested-by: Mark Rutland +Signed-off-by: Neil Armstrong +Tested-by: Marek Szyprowski +Link: https://lore.kernel.org/r/20210609150230.9291-1-narmstrong@baylibre.com +Cc: stable@vger.kernel.org +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/host/meson-gx-mmc.c | 50 ++++++++++++++++++++++++++++++++++++---- + 1 file changed, 45 insertions(+), 5 deletions(-) + +--- a/drivers/mmc/host/meson-gx-mmc.c ++++ b/drivers/mmc/host/meson-gx-mmc.c +@@ -165,6 +165,7 @@ struct meson_host { + + unsigned int bounce_buf_size; + void *bounce_buf; ++ void __iomem *bounce_iomem_buf; + dma_addr_t bounce_dma_addr; + struct sd_emmc_desc *descs; + dma_addr_t descs_dma_addr; +@@ -745,6 +746,47 @@ static void meson_mmc_desc_chain_transfe + writel(start, host->regs + SD_EMMC_START); + } + ++/* local sg copy to buffer version with _to/fromio usage for dram_access_quirk */ ++static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data, ++ size_t buflen, bool to_buffer) ++{ ++ unsigned int sg_flags = SG_MITER_ATOMIC; ++ struct scatterlist *sgl = data->sg; ++ unsigned int nents = data->sg_len; ++ struct sg_mapping_iter miter; ++ unsigned int offset = 0; ++ ++ if (to_buffer) ++ sg_flags |= SG_MITER_FROM_SG; ++ else ++ sg_flags |= SG_MITER_TO_SG; ++ ++ sg_miter_start(&miter, sgl, nents, sg_flags); ++ ++ while ((offset < buflen) && sg_miter_next(&miter)) { ++ unsigned int len; ++ ++ len = min(miter.length, buflen - offset); ++ ++ /* When dram_access_quirk, the bounce buffer is a iomem mapping */ ++ if (host->dram_access_quirk) { ++ if (to_buffer) ++ memcpy_toio(host->bounce_iomem_buf + offset, miter.addr, len); ++ else ++ memcpy_fromio(miter.addr, host->bounce_iomem_buf + offset, len); ++ } else { ++ if (to_buffer) ++ memcpy(host->bounce_buf + offset, miter.addr, len); ++ else ++ memcpy(miter.addr, host->bounce_buf + offset, len); ++ } ++ ++ offset += len; ++ } ++ ++ sg_miter_stop(&miter); ++} ++ + static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) + { + struct meson_host *host = mmc_priv(mmc); +@@ -788,8 +830,7 @@ static void meson_mmc_start_cmd(struct m + if (data->flags & MMC_DATA_WRITE) { + cmd_cfg |= CMD_CFG_DATA_WR; + WARN_ON(xfer_bytes > host->bounce_buf_size); +- sg_copy_to_buffer(data->sg, data->sg_len, +- host->bounce_buf, xfer_bytes); ++ meson_mmc_copy_buffer(host, data, xfer_bytes, true); + dma_wmb(); + } + +@@ -958,8 +999,7 @@ static irqreturn_t meson_mmc_irq_thread( + if (meson_mmc_bounce_buf_read(data)) { + xfer_bytes = data->blksz * data->blocks; + WARN_ON(xfer_bytes > host->bounce_buf_size); +- sg_copy_from_buffer(data->sg, data->sg_len, +- host->bounce_buf, xfer_bytes); ++ meson_mmc_copy_buffer(host, data, xfer_bytes, false); + } + + next_cmd = meson_mmc_get_next_command(cmd); +@@ -1179,7 +1219,7 @@ static int meson_mmc_probe(struct platfo + * instead of the DDR memory + */ + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; +- host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; ++ host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; + } else { + /* data bounce buffer */ diff --git a/queue-5.12/revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch b/queue-5.12/revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch new file mode 100644 index 00000000000..2c462c3613e --- /dev/null +++ b/queue-5.12/revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch @@ -0,0 +1,39 @@ +From baacf52a473b24e10322b67757ddb92ab8d86717 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Sat, 19 Jun 2021 11:39:43 +0800 +Subject: Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell." + +From: Yifan Zhang + +commit baacf52a473b24e10322b67757ddb92ab8d86717 upstream. + +This reverts commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3. + +Reason for revert: Side effect of enlarging CP_MEC_DOORBELL_RANGE may +cause some APUs fail to enter gfxoff in certain user cases. + +Signed-off-by: Yifan Zhang +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -6769,12 +6769,8 @@ static int gfx_v10_0_kiq_init_register(s + if (ring->use_doorbell) { + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, + (adev->doorbell_index.kiq * 2) << 2); +- /* If GC has entered CGPG, ringing doorbell > first page doesn't +- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround +- * this issue. +- */ + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, +- (adev->doorbell.size - 4)); ++ (adev->doorbell_index.userqueue_end * 2) << 2); + } + + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, diff --git a/queue-5.12/revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch b/queue-5.12/revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch new file mode 100644 index 00000000000..e8ca631b65e --- /dev/null +++ b/queue-5.12/revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch @@ -0,0 +1,39 @@ +From ee5468b9f1d3bf48082eed351dace14598e8ca39 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Sat, 19 Jun 2021 11:40:54 +0800 +Subject: Revert "drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue." + +From: Yifan Zhang + +commit ee5468b9f1d3bf48082eed351dace14598e8ca39 upstream. + +This reverts commit 4cbbe34807938e6e494e535a68d5ff64edac3f20. + +Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may +cause some APUs fail to enter gfxoff in certain user cases. + +Signed-off-by: Yifan Zhang +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3623,12 +3623,8 @@ static int gfx_v9_0_kiq_init_register(st + if (ring->use_doorbell) { + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, + (adev->doorbell_index.kiq * 2) << 2); +- /* If GC has entered CGPG, ringing doorbell > first page doesn't +- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround +- * this issue. +- */ + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, +- (adev->doorbell.size - 4)); ++ (adev->doorbell_index.userqueue_end * 2) << 2); + } + + WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, diff --git a/queue-5.12/series b/queue-5.12/series index 794e880604f..5225a392fec 100644 --- a/queue-5.12/series +++ b/queue-5.12/series @@ -1 +1,9 @@ module-limit-enabling-module.sig_enforce.patch +revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch +revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch +drm-add-a-locked-version-of-drm_is_current_master.patch +drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch +drm-radeon-wait-for-moving-fence-after-pinning.patch +drm-amdgpu-wait-for-moving-fence-after-pinning.patch +arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch +mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch