From: Jeff Law <jlaw@ventanamicro.com>
Date: Sun, 7 Sep 2025 18:11:55 +0000 (-0600)
Subject: [RISC-V] Fix ordering of pipeline models
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2b7afb69ab42367cd926bffb26ba713e51b91914;p=thirdparty%2Fgcc.git

[RISC-V] Fix ordering of pipeline models

I missed that the new ascalon pipeline description was put into the wrong place
during review.  The net is tests which wanted to use generic-ooo explicitly for
stability in the test output ended up getting  a different pipeline model and
different codegen than the test expected.

This tripped a small number of vsetvl failures in the testsuite.

This has spun on riscv64-elf and riscv32-elf in my tester and fixes the
regression.  I'm going to go ahead and push it as I'm likely offline this
afternoon/evening and don't want anyone else to waste their time chasing the
regression down.

gcc/
	* config/riscv/riscv-opts.h (riscv_microarchitecture_type): Fix ordering.
---

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 54f89781a55..4e4e9d8930e 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,10 +57,10 @@ enum riscv_microarchitecture_type {
   sifive_7,
   sifive_p400,
   sifive_p600,
-  tt_ascalon_d8,
   xiangshan,
   generic_ooo,
   mips_p8700,
+  tt_ascalon_d8,
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;