From: Greg Kroah-Hartman Date: Tue, 13 Oct 2015 21:52:59 +0000 (-0700) Subject: 3.14-stable patches X-Git-Tag: v3.10.91~76 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2c32e6280bee3171e13b5350c1d848dc5b4b8e30;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: dmaengine-dw-properly-read-dwc_params-register.patch x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch --- diff --git a/queue-3.14/dmaengine-dw-properly-read-dwc_params-register.patch b/queue-3.14/dmaengine-dw-properly-read-dwc_params-register.patch new file mode 100644 index 00000000000..5bb0503dcca --- /dev/null +++ b/queue-3.14/dmaengine-dw-properly-read-dwc_params-register.patch @@ -0,0 +1,52 @@ +From 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Mon, 28 Sep 2015 18:57:03 +0300 +Subject: dmaengine: dw: properly read DWC_PARAMS register + +From: Andy Shevchenko + +commit 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf upstream. + +In case we have less than maximum allowed channels (8) and autoconfiguration is +enabled the DWC_PARAMS read is wrong because it uses different arithmetic to +what is needed for channel priority setup. + +Re-do the caclulations properly. This now works on AVR32 board well. + +Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers) +Cc: yitian.bu@tangramtek.com +Signed-off-by: Andy Shevchenko +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/dma/dw/core.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/dma/dw/core.c ++++ b/drivers/dma/dw/core.c +@@ -1561,7 +1561,6 @@ int dw_dma_probe(struct dw_dma_chip *chi + INIT_LIST_HEAD(&dw->dma.channels); + for (i = 0; i < nr_channels; i++) { + struct dw_dma_chan *dwc = &dw->chan[i]; +- int r = nr_channels - i - 1; + + dwc->chan.device = &dw->dma; + dma_cookie_init(&dwc->chan); +@@ -1573,7 +1572,7 @@ int dw_dma_probe(struct dw_dma_chip *chi + + /* 7 is highest priority & 0 is lowest. */ + if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) +- dwc->priority = r; ++ dwc->priority = nr_channels - i - 1; + else + dwc->priority = i; + +@@ -1593,6 +1592,7 @@ int dw_dma_probe(struct dw_dma_chip *chi + /* Hardware configuration */ + if (autocfg) { + unsigned int dwc_params; ++ unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; + void __iomem *addr = chip->regs + r * sizeof(u32); + + dwc_params = dma_read_byaddr(addr, DWC_PARAMS); diff --git a/queue-3.14/series b/queue-3.14/series index 8bd00995935..21a698d4e12 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -10,3 +10,6 @@ arm-fix-thumb2-signal-handling-when-armv6-is-enabled.patch arm-8429-1-disable-gcc-sra-optimization.patch windfarm-decrement-client-count-when-unregistering.patch arm-dts-omap5-uevm.dts-fix-i2c5-pinctrl-offsets.patch +dmaengine-dw-properly-read-dwc_params-register.patch +x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch +x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch diff --git a/queue-3.14/x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch b/queue-3.14/x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch new file mode 100644 index 00000000000..9d30d2580df --- /dev/null +++ b/queue-3.14/x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch @@ -0,0 +1,77 @@ +From 5d7c631d926b59aa16f3c56eaeb83f1036c81dc7 Mon Sep 17 00:00:00 2001 +From: Shaohua Li +Date: Thu, 30 Jul 2015 16:24:43 -0700 +Subject: x86/apic: Serialize LVTT and TSC_DEADLINE writes + +From: Shaohua Li + +commit 5d7c631d926b59aa16f3c56eaeb83f1036c81dc7 upstream. + +The APIC LVTT register is MMIO mapped but the TSC_DEADLINE register is an +MSR. The write to the TSC_DEADLINE MSR is not serializing, so it's not +guaranteed that the write to LVTT has reached the APIC before the +TSC_DEADLINE MSR is written. In such a case the write to the MSR is +ignored and as a consequence the local timer interrupt never fires. + +The SDM decribes this issue for xAPIC and x2APIC modes. The +serialization methods recommended by the SDM differ. + +xAPIC: + "1. Memory-mapped write to LVT Timer Register, setting bits 18:17 to 10b. + 2. WRMSR to the IA32_TSC_DEADLINE MSR a value much larger than current time-stamp counter. + 3. If RDMSR of the IA32_TSC_DEADLINE MSR returns zero, go to step 2. + 4. WRMSR to the IA32_TSC_DEADLINE MSR the desired deadline." + +x2APIC: + "To allow for efficient access to the APIC registers in x2APIC mode, + the serializing semantics of WRMSR are relaxed when writing to the + APIC registers. Thus, system software should not use 'WRMSR to APIC + registers in x2APIC mode' as a serializing instruction. Read and write + accesses to the APIC registers will occur in program order. A WRMSR to + an APIC register may complete before all preceding stores are globally + visible; software can prevent this by inserting a serializing + instruction, an SFENCE, or an MFENCE before the WRMSR." + +The xAPIC method is to just wait for the memory mapped write to hit +the LVTT by checking whether the MSR write has reached the hardware. +There is no reason why a proper MFENCE after the memory mapped write would +not do the same. Andi Kleen confirmed that MFENCE is sufficient for the +xAPIC case as well. + +Issue MFENCE before writing to the TSC_DEADLINE MSR. This can be done +unconditionally as all CPUs which have TSC_DEADLINE also have MFENCE +support. + +[ tglx: Massaged the changelog ] + +Signed-off-by: Shaohua Li +Reviewed-by: Ingo Molnar +Cc: +Cc: +Cc: +Cc: Andi Kleen +Cc: H. Peter Anvin +Link: http://lkml.kernel.org/r/20150909041352.GA2059853@devbig257.prn2.facebook.com +Signed-off-by: Thomas Gleixner +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/apic/apic.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/x86/kernel/apic/apic.c ++++ b/arch/x86/kernel/apic/apic.c +@@ -359,6 +359,13 @@ static void __setup_APIC_LVTT(unsigned i + apic_write(APIC_LVTT, lvtt_value); + + if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { ++ /* ++ * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, ++ * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. ++ * According to Intel, MFENCE can do the serialization here. ++ */ ++ asm volatile("mfence" : : : "memory"); ++ + printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); + return; + } diff --git a/queue-3.14/x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch b/queue-3.14/x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch new file mode 100644 index 00000000000..b14e42c9e4c --- /dev/null +++ b/queue-3.14/x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch @@ -0,0 +1,74 @@ +From 03da3ff1cfcd7774c8780d2547ba0d995f7dc03d Mon Sep 17 00:00:00 2001 +From: David Woodhouse +Date: Wed, 16 Sep 2015 14:10:03 +0100 +Subject: x86/platform: Fix Geode LX timekeeping in the generic x86 build + +From: David Woodhouse + +commit 03da3ff1cfcd7774c8780d2547ba0d995f7dc03d upstream. + +In 2007, commit 07190a08eef36 ("Mark TSC on GeodeLX reliable") +bypassed verification of the TSC on Geode LX. However, this code +(now in the check_system_tsc_reliable() function in +arch/x86/kernel/tsc.c) was only present if CONFIG_MGEODE_LX was +set. + +OpenWRT has recently started building its generic Geode target +for Geode GX, not LX, to include support for additional +platforms. This broke the timekeeping on LX-based devices, +because the TSC wasn't marked as reliable: +https://dev.openwrt.org/ticket/20531 + +By adding a runtime check on is_geode_lx(), we can also include +the fix if CONFIG_MGEODEGX1 or CONFIG_X86_GENERIC are set, thus +fixing the problem. + +Signed-off-by: David Woodhouse +Cc: Andres Salomon +Cc: Linus Torvalds +Cc: Marcelo Tosatti +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1442409003.131189.87.camel@infradead.org +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/tsc.c | 17 ++++++++++------- + 1 file changed, 10 insertions(+), 7 deletions(-) + +--- a/arch/x86/kernel/tsc.c ++++ b/arch/x86/kernel/tsc.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ + EXPORT_SYMBOL(cpu_khz); +@@ -1011,15 +1012,17 @@ EXPORT_SYMBOL_GPL(mark_tsc_unstable); + + static void __init check_system_tsc_reliable(void) + { +-#ifdef CONFIG_MGEODE_LX +- /* RTSC counts during suspend */ ++#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) ++ if (is_geode_lx()) { ++ /* RTSC counts during suspend */ + #define RTSC_SUSP 0x100 +- unsigned long res_low, res_high; ++ unsigned long res_low, res_high; + +- rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); +- /* Geode_LX - the OLPC CPU has a very reliable TSC */ +- if (res_low & RTSC_SUSP) +- tsc_clocksource_reliable = 1; ++ rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); ++ /* Geode_LX - the OLPC CPU has a very reliable TSC */ ++ if (res_low & RTSC_SUSP) ++ tsc_clocksource_reliable = 1; ++ } + #endif + if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) + tsc_clocksource_reliable = 1;