From: Axel Heider <axel.heider@hensoldt.net>
Date: Tue, 25 Oct 2022 18:32:30 +0000 (+0200)
Subject: hw/timer/imx_epit: update interrupt state on CR write access
X-Git-Tag: v8.0.0-rc0~108^2~21
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2ca267fd36a275c771528bd5ae50ae8406155ad9;p=thirdparty%2Fqemu.git

hw/timer/imx_epit: update interrupt state on CR write access

The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index f148868b8cb..7af3a8b10e8 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -206,12 +206,20 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         if (s->cr & CR_SWR) {
             /* handle the reset */
             imx_epit_reset(DEVICE(s));
-            /*
-             * TODO: could we 'break' here? following operations appear
-             * to duplicate the work imx_epit_reset() already did.
-             */
         }
 
+        /*
+         * The interrupt state can change due to:
+         * - reset clears both SR.OCIF and CR.OCIE
+         * - write to CR.EN or CR.OCIE
+         */
+        imx_epit_update_int(s);
+
+        /*
+         * TODO: could we 'break' here for reset? following operations appear
+         * to duplicate the work imx_epit_reset() already did.
+         */
+
         ptimer_transaction_begin(s->timer_cmp);
         ptimer_transaction_begin(s->timer_reload);