From: Aurelien Jarno Date: Thu, 30 Jun 2016 19:18:34 +0000 (+0200) Subject: SPARC: fix nearbyint on sNaN input X-Git-Tag: glibc-2.24~47 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538;p=thirdparty%2Fglibc.git SPARC: fix nearbyint on sNaN input nearbyint and nearbyintf should not trigger inexact exceptions, but should still trigger an invalid exception for a sNaN input. The SPARC specific implementations of these functions save the FSR at the beginning of the function and restore it at the end to not trigger an inexact exception. This however doesn't work for an sNaN input which need to trigger an invalid exception. Fix that by adding a fcmp instruction using the input value before saving FSR, so that an invalid exception is triggered for a sNaN input. This fixes the math/test-nearbyint-except test on SPARC. Changelog: * sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Trigger an invalid exception for a sNaN input. * sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise. * sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3): Likewise * sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3): Likewise * sparc/sparc64/fpu/s_nearbyint.S (__nearbyint): Likewise. * sparc/sparc64/fpu/s_nearbyintf.S (__nearbyintf): Likewise. * sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3): Likewise. * sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3): Likewise. --- diff --git a/ChangeLog b/ChangeLog index 5844894b263..a7ca1ff16e9 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,19 @@ +2016-07-01 Aurelien Jarno + + * sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Trigger an + invalid exception for a sNaN input. + * sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise. + * sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S + (__nearbyint_vis3): Likewise + * sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S + (__nearbyintf_vis3): Likewise + * sparc/sparc64/fpu/s_nearbyint.S (__nearbyint): Likewise. + * sparc/sparc64/fpu/s_nearbyintf.S (__nearbyintf): Likewise. + * sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3): + Likewise. + * sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3): + Likewise. + 2016-07-01 H.J. Lu [BZ #20139] diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S index 4475e8c315c..d9ff0cc2884 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S @@ -36,6 +36,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint_vis3) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ st %fsr, [%sp + 88] sethi %hi(TWO_FIFTYTWO), %o2 sethi %hi(0xf8003e0), %o5 diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S index e39134b6866..5cd1eb02db5 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf_vis3) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ st %fsr, [%sp + 88] movwtos %o0, %f1 sethi %hi(TWO_TWENTYTHREE), %o2 diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S index 29b56b471c0..84a10971a4e 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S @@ -36,6 +36,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ st %fsr, [%sp + 88] sethi %hi(TWO_FIFTYTWO), %o2 sethi %hi(0xf8003e0), %o5 diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S index e2188b20a4c..d5cf5ce815a 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ st %fsr, [%sp + 88] st %o0, [%sp + 68] sethi %hi(TWO_TWENTYTHREE), %o2 diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S index fff277ae490..3180554f11a 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint_vis3) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(TWO_FIFTYTWO), %o2 sllx %o2, 32, %o2 diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S index c6e94ba73b9..7bf7eedb9a2 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf_vis3) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(0xf8003e0), %o5 sethi %hi(TWO_TWENTYTHREE), %o2 diff --git a/sysdeps/sparc/sparc64/fpu/s_nearbyint.S b/sysdeps/sparc/sparc64/fpu/s_nearbyint.S index caf4d729e05..456c31565f2 100644 --- a/sysdeps/sparc/sparc64/fpu/s_nearbyint.S +++ b/sysdeps/sparc/sparc64/fpu/s_nearbyint.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(TWO_FIFTYTWO), %o2 sllx %o2, 32, %o2 diff --git a/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S b/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S index 4232eca9ade..d0d9bed3dd8 100644 --- a/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S +++ b/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(0xf8003e0), %o5 sethi %hi(TWO_TWENTYTHREE), %o2