From: BALATON Zoltan via Date: Sun, 3 Jan 2021 01:09:33 +0000 (+0100) Subject: ppc440_pcix: Fix register write trace event X-Git-Tag: v6.0.0-rc0~159^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2d4c816a8dcfb0d38712c3ffed5f5fcaedd7fe40;p=thirdparty%2Fqemu.git ppc440_pcix: Fix register write trace event The trace event for pci_host_config_write() was also using the trace event for read. Add corresponding trace and correct this. Signed-off-by: BALATON Zoltan Message-Id: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index eb1290ffc8f..7829d3e5563 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -169,7 +169,7 @@ static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr, { struct PPC440PCIXState *s = opaque; - trace_ppc440_pcix_reg_read(addr, val); + trace_ppc440_pcix_reg_write(addr, val, size); switch (addr) { case PCI_VENDOR_ID ... PCI_MAX_LAT: stl_le_p(s->dev->config + addr, val); diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 6d8d095aa28..1e91984526a 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -96,3 +96,4 @@ ppc440_pcix_set_irq(int irq_num) "PCI irq %d" ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32