From: Greg Kroah-Hartman Date: Wed, 12 Sep 2018 09:01:51 +0000 (+0200) Subject: 4.14-stable patches X-Git-Tag: v4.4.156~28 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2d9248f56619e2852a913dcaf58bb8dca3e7f679;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch drm-amdgpu-add-new-firmware-id-for-vcn.patch drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch drm-amdgpu-add-vcn-support-in-psp-driver.patch drm-amdgpu-update-tmr-mc-address.patch drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch --- diff --git a/queue-4.14/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch b/queue-4.14/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch new file mode 100644 index 00000000000..edc548ba75b --- /dev/null +++ b/queue-4.14/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch @@ -0,0 +1,75 @@ +From 2d227ec2c11c568910299e8f913bac2dda47397c Mon Sep 17 00:00:00 2001 +From: Rex Zhu +Date: Fri, 20 Jul 2018 16:26:46 +0800 +Subject: drm/amd/pp/Polaris12: Fix a chunk of registers missed to program + +From: Rex Zhu + +commit 2d227ec2c11c568910299e8f913bac2dda47397c upstream. + +DIDTConfig_Polaris12[] table missed a big chunk of data. + +Pointed by aidan.fabius + +Reviewed-by: Alex Deucher +Signed-off-by: Rex Zhu +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 43 +++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +@@ -403,6 +403,49 @@ static const struct gpu_pt_config_reg DI + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, + + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, + + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, diff --git a/queue-4.14/drm-amdgpu-add-new-firmware-id-for-vcn.patch b/queue-4.14/drm-amdgpu-add-new-firmware-id-for-vcn.patch new file mode 100644 index 00000000000..4328d134dfb --- /dev/null +++ b/queue-4.14/drm-amdgpu-add-new-firmware-id-for-vcn.patch @@ -0,0 +1,34 @@ +From c9ca989696ff28ffb015cc2b7c5577938ef2626c Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:40 +0800 +Subject: drm/amdgpu:add new firmware id for VCN + +From: Likun Gao + +commit c9ca989696ff28ffb015cc2b7c5577938ef2626c upstream. + +Add the new firmware id for VCN into the enum + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +@@ -172,6 +172,7 @@ enum AMDGPU_UCODE_ID { + AMDGPU_UCODE_ID_SMC, + AMDGPU_UCODE_ID_UVD, + AMDGPU_UCODE_ID_VCE, ++ AMDGPU_UCODE_ID_VCN, + AMDGPU_UCODE_ID_MAXIMUM, + }; + diff --git a/queue-4.14/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch b/queue-4.14/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch new file mode 100644 index 00000000000..216f10e83b0 --- /dev/null +++ b/queue-4.14/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch @@ -0,0 +1,37 @@ +From abf412b3efb2f943d9b98a489e9aca836be21333 Mon Sep 17 00:00:00 2001 +From: James Zhu +Date: Fri, 10 Aug 2018 00:31:38 +0800 +Subject: drm/amdgpu:add tmr mc address into amdgpu_firmware_info + +From: James Zhu + +commit abf412b3efb2f943d9b98a489e9aca836be21333 upstream. + +amdgpu IP blocks booting need Trust Memory Region(tmr) mc address +of its firmware which is loaded by PSP + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +@@ -204,6 +204,9 @@ struct amdgpu_firmware_info { + void *kaddr; + /* ucode_size_bytes */ + uint32_t ucode_size; ++ /* starting tmr mc address */ ++ uint32_t tmr_mc_addr_lo; ++ uint32_t tmr_mc_addr_hi; + }; + + void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); diff --git a/queue-4.14/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch b/queue-4.14/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch new file mode 100644 index 00000000000..dfe604534a5 --- /dev/null +++ b/queue-4.14/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch @@ -0,0 +1,126 @@ +From 4d77c0f676e910fb1f1870738aa4bd168f253621 Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:42 +0800 +Subject: drm/amdgpu:add VCN booting with firmware loaded by PSP + +From: Likun Gao + +commit 4d77c0f676e910fb1f1870738aa4bd168f253621 upstream. + +Setup psp firmware loading for VCN, and make VCN block +booting from tmr mac address. + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 ++++++++------ + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 38 +++++++++++++++++++++++++------- + 2 files changed, 40 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +@@ -93,9 +93,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_dev + version_major, version_minor, family_id); + + +- bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) +- + AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE ++ bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE + + AMDGPU_VCN_SESSION_SIZE * 40; ++ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ++ bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, + &adev->vcn.gpu_addr, &adev->vcn.cpu_addr); +@@ -191,11 +192,13 @@ int amdgpu_vcn_resume(struct amdgpu_devi + unsigned offset; + + hdr = (const struct common_firmware_header *)adev->vcn.fw->data; +- offset = le32_to_cpu(hdr->ucode_array_offset_bytes); +- memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, +- le32_to_cpu(hdr->ucode_size_bytes)); +- size -= le32_to_cpu(hdr->ucode_size_bytes); +- ptr += le32_to_cpu(hdr->ucode_size_bytes); ++ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { ++ offset = le32_to_cpu(hdr->ucode_array_offset_bytes); ++ memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, ++ le32_to_cpu(hdr->ucode_size_bytes)); ++ size -= le32_to_cpu(hdr->ucode_size_bytes); ++ ptr += le32_to_cpu(hdr->ucode_size_bytes); ++ } + memset_io(ptr, 0, size); + } + +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -91,6 +91,16 @@ static int vcn_v1_0_sw_init(void *handle + if (r) + return r; + ++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { ++ const struct common_firmware_header *hdr; ++ hdr = (const struct common_firmware_header *)adev->vcn.fw->data; ++ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; ++ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; ++ adev->firmware.fw_size += ++ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); ++ DRM_INFO("PSP loading VCN firmware\n"); ++ } ++ + r = amdgpu_vcn_resume(adev); + if (r) + return r; +@@ -248,26 +258,38 @@ static int vcn_v1_0_resume(void *handle) + static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) + { + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); ++ uint32_t offset; + +- WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, ++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); ++ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); ++ offset = 0; ++ } else { ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr)); +- WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr)); +- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, +- AMDGPU_UVD_FIRMWARE_OFFSET >> 3); ++ offset = size; ++ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, ++ AMDGPU_UVD_FIRMWARE_OFFSET >> 3); ++ } ++ + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, +- lower_32_bits(adev->vcn.gpu_addr + size)); ++ lower_32_bits(adev->vcn.gpu_addr + offset)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, +- upper_32_bits(adev->vcn.gpu_addr + size)); ++ upper_32_bits(adev->vcn.gpu_addr + offset)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, +- lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); ++ lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, +- upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); ++ upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, + AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); diff --git a/queue-4.14/drm-amdgpu-add-vcn-support-in-psp-driver.patch b/queue-4.14/drm-amdgpu-add-vcn-support-in-psp-driver.patch new file mode 100644 index 00000000000..4d3625eefa5 --- /dev/null +++ b/queue-4.14/drm-amdgpu-add-vcn-support-in-psp-driver.patch @@ -0,0 +1,36 @@ +From 235ac9de625a0a586093ad81b3de6f7d7ab913ed Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:41 +0800 +Subject: drm/amdgpu:add VCN support in PSP driver + +From: Likun Gao + +commit 235ac9de625a0a586093ad81b3de6f7d7ab913ed upstream. + +Add VCN support in PSP driver + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +@@ -78,6 +78,9 @@ psp_v10_0_get_fw_type(struct amdgpu_firm + case AMDGPU_UCODE_ID_VCE: + *type = GFX_FW_TYPE_VCE; + break; ++ case AMDGPU_UCODE_ID_VCN: ++ *type = GFX_FW_TYPE_VCN; ++ break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + return -EINVAL; diff --git a/queue-4.14/drm-amdgpu-update-tmr-mc-address.patch b/queue-4.14/drm-amdgpu-update-tmr-mc-address.patch new file mode 100644 index 00000000000..1032fe8e7ed --- /dev/null +++ b/queue-4.14/drm-amdgpu-update-tmr-mc-address.patch @@ -0,0 +1,39 @@ +From 435198f33b56d7b875a8173a0227ddf0de285aa1 Mon Sep 17 00:00:00 2001 +From: James Zhu +Date: Fri, 10 Aug 2018 00:31:39 +0800 +Subject: drm/amdgpu: update tmr mc address + +From: James Zhu + +commit 435198f33b56d7b875a8173a0227ddf0de285aa1 upstream. + +Update tmr mc address with firmware loading address +which is returned from PSP firmware + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -134,6 +134,11 @@ psp_cmd_submit_buf(struct psp_context *p + msleep(1); + } + ++ if (ucode) { ++ ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; ++ ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; ++ } ++ + return ret; + } + diff --git a/queue-4.14/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch b/queue-4.14/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch new file mode 100644 index 00000000000..0efddd971c0 --- /dev/null +++ b/queue-4.14/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch @@ -0,0 +1,37 @@ +From 25da75043f8690fd083878447c91f289dfb63b87 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Thu, 23 Aug 2018 05:53:32 +0000 +Subject: drm/edid: Add 6 bpc quirk for SDC panel in Lenovo B50-80 + +From: Kai-Heng Feng + +commit 25da75043f8690fd083878447c91f289dfb63b87 upstream. + +Another panel that reports "DFP 1.x compliant TMDS" but it supports 6bpc +instead of 8 bpc. + +Apply 6 bpc quirk for the panel to fix it. + +BugLink: https://bugs.launchpad.net/bugs/1788308 +Cc: # v4.8+ +Signed-off-by: Kai-Heng Feng +Signed-off-by: Daniel Vetter +Link: https://patchwork.freedesktop.org/patch/msgid/20180823055332.7723-1-kai.heng.feng@canonical.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_edid.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -114,6 +114,9 @@ static const struct edid_quirk { + /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ + { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, + ++ /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ ++ { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, ++ + /* Belinea 10 15 55 */ + { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, + { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, diff --git a/queue-4.14/series b/queue-4.14/series index 48f9ba8aa76..e4aee68b26e 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -86,3 +86,11 @@ arm64-rockchip-force-config_pm-on-rockchip-systems.patch arm-rockchip-force-config_pm-on-rockchip-systems.patch drm-i915-lpe-mark-lpe-audio-runtime-pm-as-no-callbacks.patch drm-amdgpu-fix-rlc-safe-mode-test-in-gfx_v9_0_enter_rlc_safe_mode.patch +drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch +drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch +drm-amdgpu-update-tmr-mc-address.patch +drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch +drm-amdgpu-add-new-firmware-id-for-vcn.patch +drm-amdgpu-add-vcn-support-in-psp-driver.patch +drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch +uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch diff --git a/queue-4.14/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch b/queue-4.14/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch new file mode 100644 index 00000000000..861dcb8f984 --- /dev/null +++ b/queue-4.14/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch @@ -0,0 +1,55 @@ +From 8a2336e549d385bb0b46880435b411df8d8200e8 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Tue, 4 Sep 2018 15:46:13 -0700 +Subject: uapi/linux/keyctl.h: don't use C++ reserved keyword as a struct member name + +From: Randy Dunlap + +commit 8a2336e549d385bb0b46880435b411df8d8200e8 upstream. + +Since this header is in "include/uapi/linux/", apparently people want to +use it in userspace programs -- even in C++ ones. However, the header +uses a C++ reserved keyword ("private"), so change that to "dh_private" +instead to allow the header file to be used in C++ userspace. + +Fixes https://bugzilla.kernel.org/show_bug.cgi?id=191051 +Link: http://lkml.kernel.org/r/0db6c314-1ef4-9bfa-1baa-7214dd2ee061@infradead.org +Fixes: ddbb41148724 ("KEYS: Add KEYCTL_DH_COMPUTE command") +Signed-off-by: Randy Dunlap +Reviewed-by: Andrew Morton +Cc: David Howells +Cc: James Morris +Cc: "Serge E. Hallyn" +Cc: Mat Martineau +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + include/uapi/linux/keyctl.h | 2 +- + security/keys/dh.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/include/uapi/linux/keyctl.h ++++ b/include/uapi/linux/keyctl.h +@@ -65,7 +65,7 @@ + + /* keyctl structures */ + struct keyctl_dh_params { +- __s32 private; ++ __s32 dh_private; + __s32 prime; + __s32 base; + }; +--- a/security/keys/dh.c ++++ b/security/keys/dh.c +@@ -307,7 +307,7 @@ long __keyctl_dh_compute(struct keyctl_d + } + dh_inputs.g_size = dlen; + +- dlen = dh_data_from_key(pcopy.private, &dh_inputs.key); ++ dlen = dh_data_from_key(pcopy.dh_private, &dh_inputs.key); + if (dlen < 0) { + ret = dlen; + goto out2;