From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Date: Thu, 16 Aug 2018 08:06:04 +0000 (+0200)
Subject: ARM: dts: tegra20/tegra30: add pmu interrupt-affinity
X-Git-Tag: v4.20-rc1~66^2~31^2~126
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2db12b16e58a562fdf161b226739d30ea06bcd37;p=thirdparty%2Flinux.git

ARM: dts: tegra20/tegra30: add pmu interrupt-affinity

This is similar to tegra124 and avoids the following being reported
upon boot:

hw perfevents: no interrupt-affinity property for /pmu, guessing.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 80854f7de765c..20869757d32f4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -865,5 +865,7 @@
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&{/cpus/cpu@0}>,
+				     <&{/cpus/cpu@1}>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5a04ddefb71f6..d2b553f767190 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1013,5 +1013,9 @@
 			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&{/cpus/cpu@0}>,
+				     <&{/cpus/cpu@1}>,
+				     <&{/cpus/cpu@2}>,
+				     <&{/cpus/cpu@3}>;
 	};
 };