From: Tomer Maimon Date: Sun, 6 Jul 2025 13:42:06 +0000 (+0300) Subject: arm64: dts: nuvoton: combine NPCM845 reset and clk nodes X-Git-Tag: v6.18-rc1~147^2~53^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2e6028f8faf07e896ea4c2603adb4b06e8cb92fa;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: nuvoton: combine NPCM845 reset and clk nodes Combine the NPCM845 reset and clock controller nodes into a single node with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi, using the auxiliary device framework to provide clock functionality. Update the register range to 0xC4 to cover the shared reset and clock registers at 0xf0801000. Remove the separate nuvoton,npcm845-clk node, as the reset driver now handles clocks via an auxiliary device. Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20250706134207.2168184-2-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 5be132f3fd076..400d5c5b71ac0 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -42,17 +42,12 @@ interrupt-parent = <&gic>; ranges; - rstc: reset-controller@f0801000 { + clk: rstc: reset-controller@f0801000 { compatible = "nuvoton,npcm845-reset"; - reg = <0x0 0xf0801000 0x0 0x78>; - #reset-cells = <2>; + reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; - }; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm845-clk"; + #reset-cells = <2>; #clock-cells = <1>; - reg = <0x0 0xf0801000 0x0 0x1000>; }; apb {