From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 15 Feb 2023 02:05:31 +0000 (+0800)
Subject: target/riscv: Add property check for Zvfh{min} extensions
X-Git-Tag: v8.0.0-rc0~35^2~9^2~8
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2e60f9ec2ccb3906323deda7797f91c74b967b3f;p=thirdparty%2Fqemu.git

target/riscv: Add property check for Zvfh{min} extensions

Add check for Zvfh and Zvfhmin.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 49912c91745..49ac3686622 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfh) {
+        cpu->cfg.ext_zvfhmin = true;
+    }
+
+    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+        return;
+    }
+
     /* Set the ISA extensions, checks should have happened above */
     if (cpu->cfg.ext_zhinx) {
         cpu->cfg.ext_zhinxmin = true;