From: Greg Kroah-Hartman Date: Sun, 28 May 2023 07:42:31 +0000 (+0100) Subject: 4.19-stable patches X-Git-Tag: review~53 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2e91e81e97e75672a5523642e499b7f01cb70ba2;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: selftests-memfd-fix-unknown-type-name-build-failure.patch x86-mm-avoid-incomplete-global-invlpg-flushes.patch --- diff --git a/queue-4.19/selftests-memfd-fix-unknown-type-name-build-failure.patch b/queue-4.19/selftests-memfd-fix-unknown-type-name-build-failure.patch new file mode 100644 index 00000000000..0360228a727 --- /dev/null +++ b/queue-4.19/selftests-memfd-fix-unknown-type-name-build-failure.patch @@ -0,0 +1,38 @@ +From hargar@linux.microsoft.com Sun May 28 08:40:32 2023 +From: Hardik Garg +Date: Fri, 26 May 2023 16:21:36 -0700 +Subject: selftests/memfd: Fix unknown type name build failure +To: stable@vger.kernel.org +Cc: shuah@kernel.org, jeffxu@google.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, code@tyhicks.com, niyelchu@linux.microsoft.com +Message-ID: <20230526232136.255244-1-hargar@linux.microsoft.com> + +From: Hardik Garg + +Partially backport v6.3 commit 11f75a01448f ("selftests/memfd: add tests +for MFD_NOEXEC_SEAL MFD_EXEC") to fix an unknown type name build error. +In some systems, the __u64 typedef is not present due to differences in +system headers, causing compilation errors like this one: + +fuse_test.c:64:8: error: unknown type name '__u64' + 64 | static __u64 mfd_assert_get_seals(int fd) + +This header includes the __u64 typedef which increases the likelihood +of successful compilation on a wider variety of systems. + +Signed-off-by: Hardik Garg +Reviewed-by: Tyler Hicks (Microsoft) +Signed-off-by: Greg Kroah-Hartman +--- + tools/testing/selftests/memfd/fuse_test.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/tools/testing/selftests/memfd/fuse_test.c ++++ b/tools/testing/selftests/memfd/fuse_test.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include + #include + #include diff --git a/queue-4.19/series b/queue-4.19/series index 9a08637cc46..a0f8e759a4a 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -107,3 +107,5 @@ alsa-hda-ca0132-add-quirk-for-evga-x299-dark.patch m68k-move-signal-frame-following-exception-on-68020-030.patch parisc-allow-to-reboot-machine-after-system-halt.patch btrfs-use-nofs-when-cleaning-up-aborted-transactions.patch +x86-mm-avoid-incomplete-global-invlpg-flushes.patch +selftests-memfd-fix-unknown-type-name-build-failure.patch diff --git a/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch new file mode 100644 index 00000000000..4ab773fb916 --- /dev/null +++ b/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch @@ -0,0 +1,101 @@ +From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 +From: Dave Hansen +Date: Tue, 16 May 2023 12:24:25 -0700 +Subject: x86/mm: Avoid incomplete Global INVLPG flushes + +From: Dave Hansen + +commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. + +The INVLPG instruction is used to invalidate TLB entries for a +specified virtual address. When PCIDs are enabled, INVLPG is supposed +to invalidate TLB entries for the specified address for both the +current PCID *and* Global entries. (Note: Only kernel mappings set +Global=1.) + +Unfortunately, some INVLPG implementations can leave Global +translations unflushed when PCIDs are enabled. + +As a workaround, never enable PCIDs on affected processors. + +I expect there to eventually be microcode mitigations to replace this +software workaround. However, the exact version numbers where that +will happen are not known today. Once the version numbers are set in +stone, the processor list can be tweaked to only disable PCIDs on +affected processors with affected microcode. + +Note: if anyone wants a quick fix that doesn't require patching, just +stick 'nopcid' on your kernel command-line. + +Signed-off-by: Dave Hansen +Reviewed-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Sneddon +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/include/asm/intel-family.h | 5 +++++ + arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ + 2 files changed, 30 insertions(+) + +--- a/arch/x86/include/asm/intel-family.h ++++ b/arch/x86/include/asm/intel-family.h +@@ -74,6 +74,11 @@ + #define INTEL_FAM6_LAKEFIELD 0x8A + #define INTEL_FAM6_ALDERLAKE 0x97 + #define INTEL_FAM6_ALDERLAKE_L 0x9A ++#define INTEL_FAM6_ALDERLAKE_N 0xBE ++ ++#define INTEL_FAM6_RAPTORLAKE 0xB7 ++#define INTEL_FAM6_RAPTORLAKE_P 0xBA ++#define INTEL_FAM6_RAPTORLAKE_S 0xBF + + /* "Small Core" Processors (Atom) */ + +--- a/arch/x86/mm/init.c ++++ b/arch/x86/mm/init.c +@@ -9,6 +9,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -207,6 +208,24 @@ static void __init probe_page_size_mask( + } + } + ++#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ ++ .family = 6, \ ++ .model = _model, \ ++ } ++/* ++ * INVLPG may not properly flush Global entries ++ * on these CPUs when PCIDs are enabled. ++ */ ++static const struct x86_cpu_id invlpg_miss_ids[] = { ++ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), ++ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), ++ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), ++ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), ++ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), ++ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), ++ {} ++}; ++ + static void setup_pcid(void) + { + if (!IS_ENABLED(CONFIG_X86_64)) +@@ -215,6 +234,12 @@ static void setup_pcid(void) + if (!boot_cpu_has(X86_FEATURE_PCID)) + return; + ++ if (x86_match_cpu(invlpg_miss_ids)) { ++ pr_info("Incomplete global flushes, disabling PCID"); ++ setup_clear_cpu_cap(X86_FEATURE_PCID); ++ return; ++ } ++ + if (boot_cpu_has(X86_FEATURE_PGE)) { + /* + * This can't be cr4_set_bits_and_update_boot() -- the