From: Sasha Levin Date: Sat, 8 Mar 2025 14:08:45 +0000 (-0500) Subject: Fixes for 5.15 X-Git-Tag: v6.6.82~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2f313ff8f2df99c872d35a4b23b2415aa5693f4e;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/drm-amdgpu-check-extended-configuration-space-regist.patch b/queue-5.15/drm-amdgpu-check-extended-configuration-space-regist.patch new file mode 100644 index 0000000000..14aa321917 --- /dev/null +++ b/queue-5.15/drm-amdgpu-check-extended-configuration-space-regist.patch @@ -0,0 +1,53 @@ +From e92ab5be207038c41fc566617bf9cdc84ad4a7fe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 11:32:06 +0800 +Subject: drm/amdgpu: Check extended configuration space register when system + uses large bar +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ma Jun + +[ Upstream commit e372baeb3d336b20fd9463784c577fd8824497cd ] + +Some customer platforms do not enable mmconfig for various reasons, +such as bios bug, and therefore cannot access the GPU extend configuration +space through mmio. + +When the system enters the d3cold state and resumes, the amdgpu driver +fails to resume because the extend configuration space registers of +GPU can't be restored. At this point, Usually we only see some failure +dmesg log printed by amdgpu driver, it is difficult to find the root +cause. + +Therefor print a warnning message if the system can't access the +extended configuration space register when using large bar. + +Signed-off-by: Ma Jun +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Stable-dep-of: 099bffc7cadf ("drm/amdgpu: disable BAR resize on Dell G5 SE") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 4be8d2ca50f3a..387538f0ca54b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1202,6 +1202,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) + if (amdgpu_sriov_vf(adev)) + return 0; + ++ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */ ++ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR)) ++ DRM_WARN("System can't access extended configuration space,please check!!\n"); ++ + /* skip if the bios has already enabled large BAR */ + if (adev->gmc.real_vram_size && + (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) +-- +2.39.5 + diff --git a/queue-5.15/drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch b/queue-5.15/drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch new file mode 100644 index 0000000000..41cfe8c785 --- /dev/null +++ b/queue-5.15/drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch @@ -0,0 +1,50 @@ +From 681441d7fdbe26e16b70ddc6659ea2325a050122 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Feb 2025 10:55:05 -0500 +Subject: drm/amdgpu: disable BAR resize on Dell G5 SE + +From: Alex Deucher + +[ Upstream commit 099bffc7cadff40bfab1517c3461c53a7a38a0d7 ] + +There was a quirk added to add a workaround for a Sapphire +RX 5600 XT Pulse that didn't allow BAR resizing. However, +the quirk caused a regression with runtime pm on Dell laptops +using those chips, rather than narrowing the scope of the +resizing quirk, add a quirk to prevent amdgpu from resizing +the BAR on those Dell platforms unless runtime pm is disabled. + +v2: update commit message, add runpm check + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707 +Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse") +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +(cherry picked from commit 5235053f443cef4210606e5fb71f99b915a9723d) +Cc: stable@vger.kernel.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 387538f0ca54b..b11a98bee4f08 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1202,6 +1202,13 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) + if (amdgpu_sriov_vf(adev)) + return 0; + ++ /* resizing on Dell G5 SE platforms causes problems with runtime pm */ ++ if ((amdgpu_runtime_pm != 0) && ++ adev->pdev->vendor == PCI_VENDOR_ID_ATI && ++ adev->pdev->device == 0x731f && ++ adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) ++ return 0; ++ + /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */ + if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR)) + DRM_WARN("System can't access extended configuration space,please check!!\n"); +-- +2.39.5 + diff --git a/queue-5.15/efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch b/queue-5.15/efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch new file mode 100644 index 0000000000..0a6079040e --- /dev/null +++ b/queue-5.15/efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch @@ -0,0 +1,130 @@ +From 64c78128dd17f106729e5ffc7601597f8c9b75e3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 26 Feb 2025 15:18:39 -0500 +Subject: efi: Don't map the entire mokvar table to determine its size + +From: Peter Jones + +[ Upstream commit 2b90e7ace79774a3540ce569e000388f8d22c9e0 ] + +Currently, when validating the mokvar table, we (re)map the entire table +on each iteration of the loop, adding space as we discover new entries. +If the table grows over a certain size, this fails due to limitations of +early_memmap(), and we get a failure and traceback: + + ------------[ cut here ]------------ + WARNING: CPU: 0 PID: 0 at mm/early_ioremap.c:139 __early_ioremap+0xef/0x220 + ... + Call Trace: + + ? __early_ioremap+0xef/0x220 + ? __warn.cold+0x93/0xfa + ? __early_ioremap+0xef/0x220 + ? report_bug+0xff/0x140 + ? early_fixup_exception+0x5d/0xb0 + ? early_idt_handler_common+0x2f/0x3a + ? __early_ioremap+0xef/0x220 + ? efi_mokvar_table_init+0xce/0x1d0 + ? setup_arch+0x864/0xc10 + ? start_kernel+0x6b/0xa10 + ? x86_64_start_reservations+0x24/0x30 + ? x86_64_start_kernel+0xed/0xf0 + ? common_startup_64+0x13e/0x141 + + ---[ end trace 0000000000000000 ]--- + mokvar: Failed to map EFI MOKvar config table pa=0x7c4c3000, size=265187. + +Mapping the entire structure isn't actually necessary, as we don't ever +need more than one entry header mapped at once. + +Changes efi_mokvar_table_init() to only map each entry header, not the +entire table, when determining the table size. Since we're not mapping +any data past the variable name, it also changes the code to enforce +that each variable name is NUL terminated, rather than attempting to +verify it in place. + +Cc: +Signed-off-by: Peter Jones +Signed-off-by: Ard Biesheuvel +Signed-off-by: Sasha Levin +--- + drivers/firmware/efi/mokvar-table.c | 41 +++++++++-------------------- + 1 file changed, 13 insertions(+), 28 deletions(-) + +diff --git a/drivers/firmware/efi/mokvar-table.c b/drivers/firmware/efi/mokvar-table.c +index 38722d2009e20..3ac37f8cfd680 100644 +--- a/drivers/firmware/efi/mokvar-table.c ++++ b/drivers/firmware/efi/mokvar-table.c +@@ -103,7 +103,6 @@ void __init efi_mokvar_table_init(void) + void *va = NULL; + unsigned long cur_offset = 0; + unsigned long offset_limit; +- unsigned long map_size = 0; + unsigned long map_size_needed = 0; + unsigned long size; + struct efi_mokvar_table_entry *mokvar_entry; +@@ -134,48 +133,34 @@ void __init efi_mokvar_table_init(void) + */ + err = -EINVAL; + while (cur_offset + sizeof(*mokvar_entry) <= offset_limit) { +- mokvar_entry = va + cur_offset; +- map_size_needed = cur_offset + sizeof(*mokvar_entry); +- if (map_size_needed > map_size) { +- if (va) +- early_memunmap(va, map_size); +- /* +- * Map a little more than the fixed size entry +- * header, anticipating some data. It's safe to +- * do so as long as we stay within current memory +- * descriptor. +- */ +- map_size = min(map_size_needed + 2*EFI_PAGE_SIZE, +- offset_limit); +- va = early_memremap(efi.mokvar_table, map_size); +- if (!va) { +- pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%lu.\n", +- efi.mokvar_table, map_size); +- return; +- } +- mokvar_entry = va + cur_offset; ++ if (va) ++ early_memunmap(va, sizeof(*mokvar_entry)); ++ va = early_memremap(efi.mokvar_table + cur_offset, sizeof(*mokvar_entry)); ++ if (!va) { ++ pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%zu.\n", ++ efi.mokvar_table + cur_offset, sizeof(*mokvar_entry)); ++ return; + } ++ mokvar_entry = va; + + /* Check for last sentinel entry */ + if (mokvar_entry->name[0] == '\0') { + if (mokvar_entry->data_size != 0) + break; + err = 0; ++ map_size_needed = cur_offset + sizeof(*mokvar_entry); + break; + } + +- /* Sanity check that the name is null terminated */ +- size = strnlen(mokvar_entry->name, +- sizeof(mokvar_entry->name)); +- if (size >= sizeof(mokvar_entry->name)) +- break; ++ /* Enforce that the name is NUL terminated */ ++ mokvar_entry->name[sizeof(mokvar_entry->name) - 1] = '\0'; + + /* Advance to the next entry */ +- cur_offset = map_size_needed + mokvar_entry->data_size; ++ cur_offset += sizeof(*mokvar_entry) + mokvar_entry->data_size; + } + + if (va) +- early_memunmap(va, map_size); ++ early_memunmap(va, sizeof(*mokvar_entry)); + if (err) { + pr_err("EFI MOKvar config table is not valid\n"); + return; +-- +2.39.5 + diff --git a/queue-5.15/revert-riscv-set-more-data-to-cacheinfo.patch b/queue-5.15/revert-riscv-set-more-data-to-cacheinfo.patch new file mode 100644 index 0000000000..7a9d445e60 --- /dev/null +++ b/queue-5.15/revert-riscv-set-more-data-to-cacheinfo.patch @@ -0,0 +1,129 @@ +From 6a926a8e4697df959c64eaca9afad2d559360816 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Mar 2023 14:47:34 +0800 +Subject: Revert "riscv: Set more data to cacheinfo" + +From: Song Shuai + +[ Upstream commit 6a24915145c922b79d3ac78f681137a4c14a6d6b ] + +This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099. + +There are some duplicate cache attributes populations executed +in both ci_leaf_init() and later cache_setup_properties(). + +Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo") +to setup only the level and type attributes at this early place. + +Signed-off-by: Song Shuai +Acked-by: Sudeep Holla +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20230308064734.512457-1-suagrfillet@gmail.com +Signed-off-by: Palmer Dabbelt +Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") +Signed-off-by: Sasha Levin +--- + arch/riscv/kernel/cacheinfo.c | 66 ++++++++--------------------------- + 1 file changed, 15 insertions(+), 51 deletions(-) + +diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c +index 90deabfe63eaa..56141a65c7348 100644 +--- a/arch/riscv/kernel/cacheinfo.c ++++ b/arch/riscv/kernel/cacheinfo.c +@@ -64,53 +64,12 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) + 0; + } + +-static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, +- unsigned int level, unsigned int size, +- unsigned int sets, unsigned int line_size) ++static void ci_leaf_init(struct cacheinfo *this_leaf, ++ struct device_node *node, ++ enum cache_type type, unsigned int level) + { + this_leaf->level = level; + this_leaf->type = type; +- this_leaf->size = size; +- this_leaf->number_of_sets = sets; +- this_leaf->coherency_line_size = line_size; +- +- /* +- * If the cache is fully associative, there is no need to +- * check the other properties. +- */ +- if (sets == 1) +- return; +- +- /* +- * Set the ways number for n-ways associative, make sure +- * all properties are big than zero. +- */ +- if (sets > 0 && size > 0 && line_size > 0) +- this_leaf->ways_of_associativity = (size / sets) / line_size; +-} +- +-static void fill_cacheinfo(struct cacheinfo **this_leaf, +- struct device_node *node, unsigned int level) +-{ +- unsigned int size, sets, line_size; +- +- if (!of_property_read_u32(node, "cache-size", &size) && +- !of_property_read_u32(node, "cache-block-size", &line_size) && +- !of_property_read_u32(node, "cache-sets", &sets)) { +- ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); +- } +- +- if (!of_property_read_u32(node, "i-cache-size", &size) && +- !of_property_read_u32(node, "i-cache-sets", &sets) && +- !of_property_read_u32(node, "i-cache-block-size", &line_size)) { +- ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); +- } +- +- if (!of_property_read_u32(node, "d-cache-size", &size) && +- !of_property_read_u32(node, "d-cache-sets", &sets) && +- !of_property_read_u32(node, "d-cache-block-size", &line_size)) { +- ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); +- } + } + + int init_cache_level(unsigned int cpu) +@@ -163,24 +122,29 @@ int populate_cache_leaves(unsigned int cpu) + struct device_node *prev = NULL; + int levels = 1, level = 1; + +- /* Level 1 caches in cpu node */ +- fill_cacheinfo(&this_leaf, np, level); ++ if (of_property_read_bool(np, "cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); ++ if (of_property_read_bool(np, "i-cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); ++ if (of_property_read_bool(np, "d-cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); + +- /* Next level caches in cache nodes */ + prev = np; + while ((np = of_find_next_cache_node(np))) { + of_node_put(prev); + prev = np; +- + if (!of_device_is_compatible(np, "cache")) + break; + if (of_property_read_u32(np, "cache-level", &level)) + break; + if (level <= levels) + break; +- +- fill_cacheinfo(&this_leaf, np, level); +- ++ if (of_property_read_bool(np, "cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); ++ if (of_property_read_bool(np, "i-cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); ++ if (of_property_read_bool(np, "d-cache-size")) ++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); + levels = level; + } + of_node_put(np); +-- +2.39.5 + diff --git a/queue-5.15/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch b/queue-5.15/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch new file mode 100644 index 0000000000..54c215f612 --- /dev/null +++ b/queue-5.15/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch @@ -0,0 +1,74 @@ +From efe8d5b42d78aaf69eb9f6e5ec51f347c8cfe59d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Jun 2024 21:14:24 +0800 +Subject: riscv: cacheinfo: initialize cacheinfo's level and type from ACPI + PPTT + +From: Yunhui Cui + +[ Upstream commit 604f32ea6909b0ebb8ab0bf1ab7dc66ee3dc8955 ] + +Before cacheinfo can be built correctly, we need to initialize level +and type. Since RISC-V currently does not have a register group that +describes cache-related attributes like ARM64, we cannot obtain them +directly, so now we obtain cache leaves from the ACPI PPTT table +(acpi_get_cache_info()) and set the cache type through split_levels. + +Suggested-by: Jeremy Linton +Suggested-by: Sudeep Holla +Reviewed-by: Conor Dooley +Reviewed-by: Sunil V L +Reviewed-by: Jeremy Linton +Reviewed-by: Sudeep Holla +Signed-off-by: Yunhui Cui +Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com +Signed-off-by: Palmer Dabbelt +Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") +Signed-off-by: Sasha Levin +--- + arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c +index 7c6dff3dac2d6..8290cced2e62e 100644 +--- a/arch/riscv/kernel/cacheinfo.c ++++ b/arch/riscv/kernel/cacheinfo.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2017 SiFive + */ + ++#include + #include + #include + #include +@@ -121,6 +122,27 @@ int populate_cache_leaves(unsigned int cpu) + struct device_node *prev = NULL; + int levels = 1, level = 1; + ++ if (!acpi_disabled) { ++ int ret, fw_levels, split_levels; ++ ++ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); ++ if (ret) ++ return ret; ++ ++ BUG_ON((split_levels > fw_levels) || ++ (split_levels + fw_levels > this_cpu_ci->num_leaves)); ++ ++ for (; level <= this_cpu_ci->num_levels; level++) { ++ if (level <= split_levels) { ++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); ++ } else { ++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); ++ } ++ } ++ return 0; ++ } ++ + if (of_property_read_bool(np, "cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + if (of_property_read_bool(np, "i-cache-size")) +-- +2.39.5 + diff --git a/queue-5.15/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch b/queue-5.15/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch new file mode 100644 index 0000000000..3364cb28e5 --- /dev/null +++ b/queue-5.15/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch @@ -0,0 +1,71 @@ +From e73a44154d61f71cb23056500a8ef31f032541eb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Jun 2024 21:14:23 +0800 +Subject: riscv: cacheinfo: remove the useless input parameter (node) of + ci_leaf_init() + +From: Yunhui Cui + +[ Upstream commit ee3fab10cb1566562aa683f319066eaeecccf918 ] + +ci_leaf_init() is a declared static function. The implementation of the +function body and the caller do not use the parameter (struct device_node +*node) input parameter, so remove it. + +Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"") +Signed-off-by: Yunhui Cui +Reviewed-by: Jeremy Linton +Reviewed-by: Sudeep Holla +Link: https://lore.kernel.org/r/20240617131425.7526-1-cuiyunhui@bytedance.com +Signed-off-by: Palmer Dabbelt +Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") +Signed-off-by: Sasha Levin +--- + arch/riscv/kernel/cacheinfo.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c +index 56141a65c7348..7c6dff3dac2d6 100644 +--- a/arch/riscv/kernel/cacheinfo.c ++++ b/arch/riscv/kernel/cacheinfo.c +@@ -65,7 +65,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) + } + + static void ci_leaf_init(struct cacheinfo *this_leaf, +- struct device_node *node, + enum cache_type type, unsigned int level) + { + this_leaf->level = level; +@@ -123,11 +122,11 @@ int populate_cache_leaves(unsigned int cpu) + int levels = 1, level = 1; + + if (of_property_read_bool(np, "cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + if (of_property_read_bool(np, "i-cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + if (of_property_read_bool(np, "d-cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + + prev = np; + while ((np = of_find_next_cache_node(np))) { +@@ -140,11 +139,11 @@ int populate_cache_leaves(unsigned int cpu) + if (level <= levels) + break; + if (of_property_read_bool(np, "cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + if (of_property_read_bool(np, "i-cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + if (of_property_read_bool(np, "d-cache-size")) +- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); ++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + levels = level; + } + of_node_put(np); +-- +2.39.5 + diff --git a/queue-5.15/riscv-cacheinfo-use-of_property_present-for-non-bool.patch b/queue-5.15/riscv-cacheinfo-use-of_property_present-for-non-bool.patch new file mode 100644 index 0000000000..0f8f64ebf5 --- /dev/null +++ b/queue-5.15/riscv-cacheinfo-use-of_property_present-for-non-bool.patch @@ -0,0 +1,65 @@ +From 6ff9980af5a09b18734baf0094b269ff7b52feea Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Nov 2024 13:03:13 -0600 +Subject: riscv: cacheinfo: Use of_property_present() for non-boolean + properties +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Rob Herring + +[ Upstream commit fb8179ce2996bffaa36a04e2b6262843b01b7565 ] + +The use of of_property_read_bool() for non-boolean properties is +deprecated in favor of of_property_present() when testing for property +presence. + +Signed-off-by: Rob Herring (Arm) +Reviewed-by: Clément Léger +Cc: stable@vger.kernel.org +Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code") +Link: https://lore.kernel.org/r/20241104190314.270095-1-robh@kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Sasha Levin +--- + arch/riscv/kernel/cacheinfo.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c +index c196d1a0b8d98..f42c0886484a4 100644 +--- a/arch/riscv/kernel/cacheinfo.c ++++ b/arch/riscv/kernel/cacheinfo.c +@@ -146,11 +146,11 @@ int populate_cache_leaves(unsigned int cpu) + if (!np) + return -ENOENT; + +- if (of_property_read_bool(np, "cache-size")) ++ if (of_property_present(np, "cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); +- if (of_property_read_bool(np, "i-cache-size")) ++ if (of_property_present(np, "i-cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); +- if (of_property_read_bool(np, "d-cache-size")) ++ if (of_property_present(np, "d-cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + + prev = np; +@@ -163,11 +163,11 @@ int populate_cache_leaves(unsigned int cpu) + break; + if (level <= levels) + break; +- if (of_property_read_bool(np, "cache-size")) ++ if (of_property_present(np, "cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); +- if (of_property_read_bool(np, "i-cache-size")) ++ if (of_property_present(np, "i-cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); +- if (of_property_read_bool(np, "d-cache-size")) ++ if (of_property_present(np, "d-cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + levels = level; + } +-- +2.39.5 + diff --git a/queue-5.15/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch b/queue-5.15/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch new file mode 100644 index 0000000000..f6f7d97881 --- /dev/null +++ b/queue-5.15/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch @@ -0,0 +1,67 @@ +From c78c4280de09038dde48e207301dd6ddbdf64146 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 13 Sep 2024 10:00:52 +0200 +Subject: riscv: Prevent a bad reference count on CPU nodes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Miquel Sabaté Solà + +[ Upstream commit 37233169a6ea912020c572f870075a63293b786a ] + +When populating cache leaves we previously fetched the CPU device node +at the very beginning. But when ACPI is enabled we go through a +specific branch which returns early and does not call 'of_node_put' for +the node that was acquired. + +Since we are not using a CPU device node for the ACPI code anyways, we +can simply move the initialization of it just passed the ACPI block, and +we are guaranteed to have an 'of_node_put' call for the acquired node. +This prevents a bad reference count of the CPU device node. + +Moreover, the previous function did not check for errors when acquiring +the device node, so a return -ENOENT has been added for that case. + +Signed-off-by: Miquel Sabaté Solà +Reviewed-by: Sudeep Holla +Reviewed-by: Sunil V L +Reviewed-by: Alexandre Ghiti +Fixes: 604f32ea6909 ("riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com +Signed-off-by: Palmer Dabbelt +Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") +Signed-off-by: Sasha Levin +--- + arch/riscv/kernel/cacheinfo.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c +index 8290cced2e62e..c196d1a0b8d98 100644 +--- a/arch/riscv/kernel/cacheinfo.c ++++ b/arch/riscv/kernel/cacheinfo.c +@@ -118,8 +118,7 @@ int populate_cache_leaves(unsigned int cpu) + { + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + struct cacheinfo *this_leaf = this_cpu_ci->info_list; +- struct device_node *np = of_cpu_device_node_get(cpu); +- struct device_node *prev = NULL; ++ struct device_node *np, *prev; + int levels = 1, level = 1; + + if (!acpi_disabled) { +@@ -143,6 +142,10 @@ int populate_cache_leaves(unsigned int cpu) + return 0; + } + ++ np = of_cpu_device_node_get(cpu); ++ if (!np) ++ return -ENOENT; ++ + if (of_property_read_bool(np, "cache-size")) + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + if (of_property_read_bool(np, "i-cache-size")) +-- +2.39.5 + diff --git a/queue-5.15/series b/queue-5.15/series index 25afe26446..0a9fa7429c 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -531,3 +531,12 @@ vmlinux.lds-ensure-that-const-vars-with-relocations-are-mapped-r-o.patch sched-core-prevent-rescheduling-when-interrupts-are-disabled.patch intel_idle-handle-older-cpus-which-stop-the-tsc-in-deeper-c-states-correctly.patch pfifo_tail_enqueue-drop-new-packet-when-sch-limit-0.patch +smb-client-add-check-for-next_buffer-in-receive_encr.patch +drm-amdgpu-check-extended-configuration-space-regist.patch +drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch +revert-riscv-set-more-data-to-cacheinfo.patch +riscv-cacheinfo-remove-the-useless-input-parameter-n.patch +riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch +riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch +riscv-cacheinfo-use-of_property_present-for-non-bool.patch +efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch diff --git a/queue-5.15/smb-client-add-check-for-next_buffer-in-receive_encr.patch b/queue-5.15/smb-client-add-check-for-next_buffer-in-receive_encr.patch new file mode 100644 index 0000000000..9e5c711b67 --- /dev/null +++ b/queue-5.15/smb-client-add-check-for-next_buffer-in-receive_encr.patch @@ -0,0 +1,40 @@ +From 65cd7e5420d43ba42315e7bd1b8c972867d6c824 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Feb 2025 15:20:38 +0800 +Subject: smb: client: Add check for next_buffer in + receive_encrypted_standard() + +From: Haoxiang Li + +[ Upstream commit 860ca5e50f73c2a1cef7eefc9d39d04e275417f7 ] + +Add check for the return value of cifs_buf_get() and cifs_small_buf_get() +in receive_encrypted_standard() to prevent null pointer dereference. + +Fixes: eec04ea11969 ("smb: client: fix OOB in receive_encrypted_standard()") +Cc: stable@vger.kernel.org +Signed-off-by: Haoxiang Li +Signed-off-by: Steve French +Signed-off-by: Sasha Levin +--- + fs/cifs/smb2ops.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c +index ee9a1e6550e3c..7bce1ab86c4da 100644 +--- a/fs/cifs/smb2ops.c ++++ b/fs/cifs/smb2ops.c +@@ -5198,6 +5198,10 @@ receive_encrypted_standard(struct TCP_Server_Info *server, + next_buffer = (char *)cifs_buf_get(); + else + next_buffer = (char *)cifs_small_buf_get(); ++ if (!next_buffer) { ++ cifs_server_dbg(VFS, "No memory for (large) SMB response\n"); ++ return -1; ++ } + memcpy(next_buffer, buf + next_cmd, pdu_length - next_cmd); + } + +-- +2.39.5 +