From: Greg Kroah-Hartman Date: Tue, 18 Feb 2025 14:09:32 +0000 (+0100) Subject: 5.10-stable patches X-Git-Tag: v6.1.129~48 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2f645c231de503714fcd12fb0483436e555bf04c;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: drm-tidss-clear-the-interrupt-status-for-interrupts-being-disabled.patch drm-tidss-fix-issue-in-irq-handling-causing-irq-flood-issue.patch --- diff --git a/queue-5.10/drm-tidss-clear-the-interrupt-status-for-interrupts-being-disabled.patch b/queue-5.10/drm-tidss-clear-the-interrupt-status-for-interrupts-being-disabled.patch new file mode 100644 index 0000000000..d8c0944d4c --- /dev/null +++ b/queue-5.10/drm-tidss-clear-the-interrupt-status-for-interrupts-being-disabled.patch @@ -0,0 +1,72 @@ +From 361a2ebb5cad211732ec3c5d962de49b21895590 Mon Sep 17 00:00:00 2001 +From: Devarsh Thakkar +Date: Mon, 21 Oct 2024 17:07:49 +0300 +Subject: drm/tidss: Clear the interrupt status for interrupts being disabled + +From: Devarsh Thakkar + +commit 361a2ebb5cad211732ec3c5d962de49b21895590 upstream. + +The driver does not touch the irqstatus register when it is disabling +interrupts. This might cause an interrupt to trigger for an interrupt +that was just disabled. + +To fix the issue, clear the irqstatus registers right after disabling +the interrupts. + +Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") +Cc: stable@vger.kernel.org +Reported-by: Jonathan Cormier +Closes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1394222/am625-issue-about-tidss-rcu_preempt-self-detected-stall-on-cpu/5424479#5424479 +Signed-off-by: Devarsh Thakkar +[Tomi: mostly rewrote the patch] +Reviewed-by: Jonathan Cormier +Tested-by: Jonathan Cormier +Reviewed-by: Aradhya Bhatia +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20241021-tidss-irq-fix-v1-5-82ddaec94e4a@ideasonboard.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -596,7 +596,7 @@ void dispc_k2g_set_irqenable(struct disp + { + dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); + +- /* clear the irqstatus for newly enabled irqs */ ++ /* clear the irqstatus for irqs that will be enabled */ + dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); + + dispc_k2g_vp_set_irqenable(dispc, 0, mask); +@@ -604,6 +604,9 @@ void dispc_k2g_set_irqenable(struct disp + + dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); + ++ /* clear the irqstatus for irqs that were disabled */ ++ dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & old_mask); ++ + /* flush posted write */ + dispc_k2g_read_irqenable(dispc); + } +@@ -735,7 +738,7 @@ static void dispc_k3_set_irqenable(struc + + old_mask = dispc_k3_read_irqenable(dispc); + +- /* clear the irqstatus for newly enabled irqs */ ++ /* clear the irqstatus for irqs that will be enabled */ + dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); + + for (i = 0; i < dispc->feat->num_vps; ++i) { +@@ -760,6 +763,9 @@ static void dispc_k3_set_irqenable(struc + if (main_disable) + dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); + ++ /* clear the irqstatus for irqs that were disabled */ ++ dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & old_mask); ++ + /* Flush posted writes */ + dispc_read(dispc, DISPC_IRQENABLE_SET); + } diff --git a/queue-5.10/drm-tidss-fix-issue-in-irq-handling-causing-irq-flood-issue.patch b/queue-5.10/drm-tidss-fix-issue-in-irq-handling-causing-irq-flood-issue.patch new file mode 100644 index 0000000000..49334d777d --- /dev/null +++ b/queue-5.10/drm-tidss-fix-issue-in-irq-handling-causing-irq-flood-issue.patch @@ -0,0 +1,83 @@ +From 44b6730ab53ef04944fbaf6da0e77397531517b7 Mon Sep 17 00:00:00 2001 +From: Tomi Valkeinen +Date: Mon, 21 Oct 2024 17:07:45 +0300 +Subject: drm/tidss: Fix issue in irq handling causing irq-flood issue + +From: Tomi Valkeinen + +commit 44b6730ab53ef04944fbaf6da0e77397531517b7 upstream. + +It has been observed that sometimes DSS will trigger an interrupt and +the top level interrupt (DISPC_IRQSTATUS) is not zero, but the VP and +VID level interrupt-statuses are zero. + +As the top level irqstatus is supposed to tell whether we have VP/VID +interrupts, the thinking of the driver authors was that this particular +case could never happen. Thus the driver only clears the DISPC_IRQSTATUS +bits which has corresponding interrupts in VP/VID status. So when this +issue happens, the driver will not clear DISPC_IRQSTATUS, and we get an +interrupt flood. + +It is unclear why the issue happens. It could be a race issue in the +driver, but no such race has been found. It could also be an issue with +the HW. However a similar case can be easily triggered by manually +writing to DISPC_IRQSTATUS_RAW. This will forcibly set a bit in the +DISPC_IRQSTATUS and trigger an interrupt, and as the driver never clears +the bit, we get an interrupt flood. + +To fix the issue, always clear DISPC_IRQSTATUS. The concern with this +solution is that if the top level irqstatus is the one that triggers the +interrupt, always clearing DISPC_IRQSTATUS might leave some interrupts +unhandled if VP/VID interrupt statuses have bits set. However, testing +shows that if any of the irqstatuses is set (i.e. even if +DISPC_IRQSTATUS == 0, but a VID irqstatus has a bit set), we will get an +interrupt. + +Co-developed-by: Bin Liu +Signed-off-by: Bin Liu +Co-developed-by: Devarsh Thakkar +Signed-off-by: Devarsh Thakkar +Co-developed-by: Jonathan Cormier +Signed-off-by: Jonathan Cormier +Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") +Cc: stable@vger.kernel.org +Tested-by: Jonathan Cormier +Reviewed-by: Aradhya Bhatia +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20241021-tidss-irq-fix-v1-1-82ddaec94e4a@ideasonboard.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -676,24 +676,20 @@ static + void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) + { + unsigned int i; +- u32 top_clear = 0; + + for (i = 0; i < dispc->feat->num_vps; ++i) { +- if (clearmask & DSS_IRQ_VP_MASK(i)) { ++ if (clearmask & DSS_IRQ_VP_MASK(i)) + dispc_k3_vp_write_irqstatus(dispc, i, clearmask); +- top_clear |= BIT(i); +- } + } + for (i = 0; i < dispc->feat->num_planes; ++i) { +- if (clearmask & DSS_IRQ_PLANE_MASK(i)) { ++ if (clearmask & DSS_IRQ_PLANE_MASK(i)) + dispc_k3_vid_write_irqstatus(dispc, i, clearmask); +- top_clear |= BIT(4 + i); +- } + } + if (dispc->feat->subrev == DISPC_K2G) + return; + +- dispc_write(dispc, DISPC_IRQSTATUS, top_clear); ++ /* always clear the top level irqstatus */ ++ dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS)); + + /* Flush posted writes */ + dispc_read(dispc, DISPC_IRQSTATUS); diff --git a/queue-5.10/series b/queue-5.10/series index c85dd1a0a6..fb928e4b11 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -301,3 +301,5 @@ neighbour-use-rcu-protection-in-__neigh_notify.patch arp-use-rcu-protection-in-arp_xmit.patch openvswitch-use-rcu-protection-in-ovs_vport_cmd_fill.patch ndisc-extend-rcu-protection-in-ndisc_send_skb.patch +drm-tidss-fix-issue-in-irq-handling-causing-irq-flood-issue.patch +drm-tidss-clear-the-interrupt-status-for-interrupts-being-disabled.patch