From: Stephen Boyd <sboyd@kernel.org>
Date: Fri, 17 Jan 2020 19:01:09 +0000 (-0800)
Subject: Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
X-Git-Tag: v5.6-rc1~75^2~3^5
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=31ef091770da008b4b181e70858e2742ed0c3e39;p=thirdparty%2Fkernel%2Flinux.git

Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add meson8b DDR clock controller
 - Add input clocks to meson8b controllers
 - Fix meson8b mali clock update using the glitch free mux
 - Fix pll driver division by zero init

* tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson:
  clk: clarify that clk_set_rate() does updates from top to bottom
  clk: meson: meson8b: make the CCF use the glitch-free mali mux
  clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
  clk: meson: g12a: fix missing uart2 in regmap table
  clk: meson: meson8b: use of_clk_hw_register to register the clocks
  clk: meson: meson8b: don't register the XTAL clock when provided via OF
  clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
  clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
  clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
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31ef091770da008b4b181e70858e2742ed0c3e39