From: Greg Kroah-Hartman Date: Mon, 13 Jan 2014 18:21:24 +0000 (-0800) Subject: 3.4-stable patches X-Git-Tag: v3.4.77~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3202e113de616fa67852c037e4956785468cad94;p=thirdparty%2Fkernel%2Fstable-queue.git 3.4-stable patches added patches: arm-shmobile-mackerel-fix-coherent-dma-mask.patch x86-fpu-amd-clear-exceptions-in-amd-fxsave-workaround.patch --- diff --git a/queue-3.4/arm-shmobile-mackerel-fix-coherent-dma-mask.patch b/queue-3.4/arm-shmobile-mackerel-fix-coherent-dma-mask.patch new file mode 100644 index 00000000000..e0032ec2f9e --- /dev/null +++ b/queue-3.4/arm-shmobile-mackerel-fix-coherent-dma-mask.patch @@ -0,0 +1,45 @@ +From b6328a6b7ba57fc84c38248f6f0e387e1170f1a8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart +Date: Mon, 16 Dec 2013 19:16:09 +0100 +Subject: ARM: shmobile: mackerel: Fix coherent DMA mask + +From: Laurent Pinchart + +commit b6328a6b7ba57fc84c38248f6f0e387e1170f1a8 upstream. + +Commit 4dcfa60071b3d23f0181f27d8519f12e37cefbb9 ("ARM: DMA-API: better +handing of DMA masks for coherent allocations") added an additional +check to the coherent DMA mask that results in an error when the mask is +larger than what dma_addr_t can address. + +Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix +the problem. + +Signed-off-by: Laurent Pinchart +Signed-off-by: Simon Horman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-shmobile/board-mackerel.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-shmobile/board-mackerel.c ++++ b/arch/arm/mach-shmobile/board-mackerel.c +@@ -422,7 +422,7 @@ static struct platform_device lcdc_devic + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, +- .coherent_dma_mask = ~0, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }; + +@@ -498,7 +498,7 @@ static struct platform_device hdmi_lcdc_ + .id = 1, + .dev = { + .platform_data = &hdmi_lcdc_info, +- .coherent_dma_mask = ~0, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }; + diff --git a/queue-3.4/series b/queue-3.4/series index 8cf54fa97ee..c859ae59d94 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -19,3 +19,5 @@ vlan-fix-header-ops-passthru-when-doing-tx-vlan-offload.patch net-llc-fix-use-after-free-in-llc_ui_recvmsg.patch bridge-use-spin_lock_bh-in-br_multicast_set_hash_max.patch arm-fix-bad-mode-in-...-handler-message-for-undefined-instructions.patch +arm-shmobile-mackerel-fix-coherent-dma-mask.patch +x86-fpu-amd-clear-exceptions-in-amd-fxsave-workaround.patch diff --git a/queue-3.4/x86-fpu-amd-clear-exceptions-in-amd-fxsave-workaround.patch b/queue-3.4/x86-fpu-amd-clear-exceptions-in-amd-fxsave-workaround.patch new file mode 100644 index 00000000000..b6741435815 --- /dev/null +++ b/queue-3.4/x86-fpu-amd-clear-exceptions-in-amd-fxsave-workaround.patch @@ -0,0 +1,45 @@ +From 26bef1318adc1b3a530ecc807ef99346db2aa8b0 Mon Sep 17 00:00:00 2001 +From: Linus Torvalds +Date: Sat, 11 Jan 2014 19:15:52 -0800 +Subject: x86, fpu, amd: Clear exceptions in AMD FXSAVE workaround + +From: Linus Torvalds + +commit 26bef1318adc1b3a530ecc807ef99346db2aa8b0 upstream. + +Before we do an EMMS in the AMD FXSAVE information leak workaround we +need to clear any pending exceptions, otherwise we trap with a +floating-point exception inside this code. + +Reported-by: halfdog +Tested-by: Borislav Petkov +Link: http://lkml.kernel.org/r/CA%2B55aFxQnY_PCG_n4=0w-VG=YLXL-yr7oMxyy0WU2gCBAf3ydg@mail.gmail.com +Signed-off-by: H. Peter Anvin +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/include/asm/fpu-internal.h | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +--- a/arch/x86/include/asm/fpu-internal.h ++++ b/arch/x86/include/asm/fpu-internal.h +@@ -266,12 +266,13 @@ static inline int restore_fpu_checking(s + /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception + is pending. Clear the x87 state here by setting it to fixed + values. "m" is a random variable that should be in L1 */ +- alternative_input( +- ASM_NOP8 ASM_NOP2, +- "emms\n\t" /* clear stack tags */ +- "fildl %P[addr]", /* set F?P to defined value */ +- X86_FEATURE_FXSAVE_LEAK, +- [addr] "m" (tsk->thread.fpu.has_fpu)); ++ if (unlikely(static_cpu_has(X86_FEATURE_FXSAVE_LEAK))) { ++ asm volatile( ++ "fnclex\n\t" ++ "emms\n\t" ++ "fildl %P[addr]" /* set F?P to defined value */ ++ : : [addr] "m" (tsk->thread.fpu.has_fpu)); ++ } + + return fpu_restore_checking(&tsk->thread.fpu); + }