From: Siddhesh Poyarekar Date: Fri, 11 Sep 2020 03:48:08 +0000 (+0530) Subject: [Morello] ADR, ADRP and ADRDP X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=321c4e1a0556b154164c997f8eed2230d61bae3e;p=thirdparty%2Fbinutils-gdb.git [Morello] ADR, ADRP and ADRDP The opcodes for these instructions overlap with their A64 equivalents; in fact they're the same with one bit reduced in the immediate. Use mapping symbols to determine the correct disassembly. gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operands): Add A64C_ADDR_ADRDP. Support 20-bit offset for capability variants. * testsuite/gas/aarch64/morello_insn-c64.d: Add tests. * testsuite/gas/aarch64/morello_insn.d: Likewise. * testsuite/gas/aarch64/morello_insn.s: Likewise. include/ChangeLog: 2020-10-20 Siddhesh Poyarekar * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_ADRDP. opcodes/ChangeLog: 2020-10-20 Siddhesh Poyarekar * aarch64-dis.c (aarch64_ext_regno): Reject A64 ADR when in C64. (aarch64_ext_imm): Select ADRDP in C64. * aarch64-opc.c (fields): Add a64c_immhi field. (validate_adr_reg_for_feature): New function. (operand_general_constraint_met_p): Use it. (aarch64_print_operand): Add A64C_ADDR_ADRDP. * aarch64-opc.h (aarch64_field_kind): FLD_a64c_immhi. * aarch64-tbl.h (aarch64_opcode_table): Add new instructions. (AARCH64_OPERANDS): Add new operands. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index f6ad769d5ca..b03a6718474 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2020-10-20 Siddhesh Poyarekar + + * config/tc-aarch64.c (parse_operands): Add A64C_ADDR_ADRDP. + Support 20-bit offset for capability variants. + * testsuite/gas/aarch64/morello_insn-c64.d: Add tests. + * testsuite/gas/aarch64/morello_insn.d: Likewise. + * testsuite/gas/aarch64/morello_insn.s: Likewise. + 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operand): Reuse ADDR_UIMM12 code diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c17168098ef..97a5c0613c8 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6454,10 +6454,38 @@ parse_operands (char *str, const aarch64_opcode *opcode) } break; + /* ADRP variants. Clear the value as operand needs to be + relocated. */ + case AARCH64_OPND_A64C_ADDR_ADRDP: + if (!AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)) + { + as_bad (_("instruction not allowed on this processor")); + goto failure; + } + po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, + imm_reg_type)); + if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool) + { + info->imm.value = inst.reloc.exp.X_add_number; + inst.reloc.type = BFD_RELOC_UNUSED; + if (info->imm.value & 0xfff) + goto bad_adrdp; + + info->imm.value >>= 12; + break; + } +bad_adrdp: + set_syntax_error + (_("20-bit 4K page aligned integer constant expected")); + goto failure; + case AARCH64_OPND_ADDR_ADRP: + if (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)) + info->imm.value = 1UL << 20; + else + info->imm.value = 0; + po_misc_or_fail (parse_adrp (&str)); - /* Clear the value as operand needs to be relocated. */ - info->imm.value = 0; break; case AARCH64_OPND_ADDR_PCREL14: diff --git a/gas/testsuite/gas/aarch64/morello_insn-c64.d b/gas/testsuite/gas/aarch64/morello_insn-c64.d index 2456a5b598e..3663f457f00 100644 --- a/gas/testsuite/gas/aarch64/morello_insn-c64.d +++ b/gas/testsuite/gas/aarch64/morello_insn-c64.d @@ -1,4 +1,4 @@ -#as: -march=morello+c64 +#as: -march=morello+c64 --defsym C64MODE=1 #objdump: -dr #source: morello_insn.s @@ -7,7 +7,7 @@ Disassembly of section \.text: -.* <.text>: +.* <.*>: .*: c2c273e0 bx #4 .*: c2c253c0 ret c30 .*: c2c23280 blr c20 @@ -72,6 +72,12 @@ Disassembly of section \.text: .*: c2c053e6 gcvalue x6, csp .*: c2d4a7e1 chkeq csp, c20 .*: c2d4a661 chkeq c19, c20 + +.*