From: Robin Dapp Date: Mon, 22 May 2023 18:41:59 +0000 (+0200) Subject: RISC-V: Allow all const_vec_duplicates as constants. X-Git-Tag: basepoints/gcc-15~8736 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=32a0266cc54a404007fca0d44dc9a299bbe70c1f;p=thirdparty%2Fgcc.git RISC-V: Allow all const_vec_duplicates as constants. As we can always broadcast an integer constant to a vector register allow them in riscv_const_insns. We need as many instructions as it takes to generate the constant and one vmv.vx. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Allow const_vec_duplicates. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Add vmv.v.x tests. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Dito. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Dito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Dito. * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Dito. --- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 37e08c04ec6a..85db1e3c86b8 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1295,12 +1295,23 @@ riscv_const_insns (rtx x) * accurately according to BASE && STEP. */ return 1; } - /* Constants from -16 to 15 can be loaded with vmv.v.i. - The Wc0, Wc1 constraints are already covered by the - vi constraint so we do not need to check them here - separately. */ - if (satisfies_constraint_vi (x)) - return 1; + + rtx elt; + if (const_vec_duplicate_p (x, &elt)) + { + /* Constants from -16 to 15 can be loaded with vmv.v.i. + The Wc0, Wc1 constraints are already covered by the + vi constraint so we do not need to check them here + separately. */ + if (satisfies_constraint_vi (x)) + return 1; + + /* A const duplicate vector can always be broadcast from + a general-purpose register. This means we need as many + insns as it takes to load the constant into the GPR + and one vmv.v.x. */ + return 1 + riscv_integer_cost (INTVAL (elt)); + } } /* TODO: We may support more const vector in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c index 631ea3bf268e..e8d017f73399 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c @@ -3,4 +3,5 @@ #include "vmv-imm-template.h" -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c index 7ded6cc18d24..f85ad4117d3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c @@ -3,4 +3,5 @@ #include "vmv-imm-template.h" -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c index 6764110d4613..faa6c9073375 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c @@ -54,4 +54,12 @@ int main () TEST_POS(uint64_t, 13) TEST_POS(uint64_t, 14) TEST_POS(uint64_t, 15) + TEST_POS(uint32_t, 16) + TEST_POS(uint32_t, 123) + TEST_POS(uint32_t, 255) + TEST_POS(uint32_t, 999) + TEST_POS(uint32_t, 32701) + TEST_POS(uint32_t, 65535) + TEST_POS(uint32_t, 65536) + TEST_POS(uint32_t, 923423) } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c index c419256cd45c..6843bc6018d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c @@ -3,4 +3,5 @@ #include "vmv-imm-template.h" -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c index e386166f95e8..39fb2a6cc7be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c @@ -3,4 +3,5 @@ #include "vmv-imm-template.h" -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h index 855343d7e3e6..84b26e0f1c2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h @@ -17,38 +17,46 @@ dst[i] = -VAL; \ } -#define TEST_ALL() \ -VMV_NEG(int8_t,16) \ -VMV_NEG(int8_t,15) \ -VMV_NEG(int8_t,14) \ -VMV_NEG(int8_t,13) \ -VMV_NEG(int16_t,12) \ -VMV_NEG(int16_t,11) \ -VMV_NEG(int16_t,10) \ -VMV_NEG(int16_t,9) \ -VMV_NEG(int32_t,8) \ -VMV_NEG(int32_t,7) \ -VMV_NEG(int32_t,6) \ -VMV_NEG(int32_t,5) \ -VMV_NEG(int64_t,4) \ -VMV_NEG(int64_t,3) \ -VMV_NEG(int64_t,2) \ -VMV_NEG(int64_t,1) \ -VMV_POS(uint8_t,0) \ -VMV_POS(uint8_t,1) \ -VMV_POS(uint8_t,2) \ -VMV_POS(uint8_t,3) \ -VMV_POS(uint16_t,4) \ -VMV_POS(uint16_t,5) \ -VMV_POS(uint16_t,6) \ -VMV_POS(uint16_t,7) \ -VMV_POS(uint32_t,8) \ -VMV_POS(uint32_t,9) \ -VMV_POS(uint32_t,10) \ -VMV_POS(uint32_t,11) \ -VMV_POS(uint64_t,12) \ -VMV_POS(uint64_t,13) \ -VMV_POS(uint64_t,14) \ -VMV_POS(uint64_t,15) +#define TEST_ALL() \ +VMV_NEG(int8_t,16) \ +VMV_NEG(int8_t,15) \ +VMV_NEG(int8_t,14) \ +VMV_NEG(int8_t,13) \ +VMV_NEG(int16_t,12) \ +VMV_NEG(int16_t,11) \ +VMV_NEG(int16_t,10) \ +VMV_NEG(int16_t,9) \ +VMV_NEG(int32_t,8) \ +VMV_NEG(int32_t,7) \ +VMV_NEG(int32_t,6) \ +VMV_NEG(int32_t,5) \ +VMV_NEG(int64_t,4) \ +VMV_NEG(int64_t,3) \ +VMV_NEG(int64_t,2) \ +VMV_NEG(int64_t,1) \ +VMV_POS(uint8_t,0) \ +VMV_POS(uint8_t,1) \ +VMV_POS(uint8_t,2) \ +VMV_POS(uint8_t,3) \ +VMV_POS(uint16_t,4) \ +VMV_POS(uint16_t,5) \ +VMV_POS(uint16_t,6) \ +VMV_POS(uint16_t,7) \ +VMV_POS(uint32_t,8) \ +VMV_POS(uint32_t,9) \ +VMV_POS(uint32_t,10) \ +VMV_POS(uint32_t,11) \ +VMV_POS(uint64_t,12) \ +VMV_POS(uint64_t,13) \ +VMV_POS(uint64_t,14) \ +VMV_POS(uint64_t,15) \ +VMV_POS(uint32_t,16) \ +VMV_POS(uint32_t,123) \ +VMV_POS(uint32_t,255) \ +VMV_POS(uint32_t,999) \ +VMV_POS(uint32_t,32701) \ +VMV_POS(uint32_t,65535) \ +VMV_POS(uint32_t,65536) \ +VMV_POS(uint32_t,923423) \ TEST_ALL()