From: Greg Kroah-Hartman Date: Mon, 8 Jul 2024 12:58:33 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v6.6.38~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=338a8d819292d0a9b946aae3dbeb205728ff274f;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: arm64-dts-rockchip-fix-the-dcdc_reg2-minimum-voltage-on-quartz64-model-b.patch bnx2x-fix-multiple-ubsan-array-index-out-of-bounds.patch drm-amdgpu-atomfirmware-silence-ubsan-warning.patch drm-nouveau-fix-null-pointer-dereference-in-nouveau_connector_get_modes.patch drm-panel-orientation-quirks-add-quirk-for-valve-galileo.patch mtd-rawnand-bypass-a-couple-of-sanity-checks-during-nand-identification.patch mtd-rawnand-ensure-ecc-configuration-is-propagated-to-upper-layers.patch mtd-rawnand-rockchip-ensure-nvddr-timings-are-rejected.patch powerpc-pseries-fix-scv-instruction-crash-with-kexec.patch revert-mm-writeback-fix-possible-divide-by-zero-in-wb_dirty_limits-again.patch --- diff --git a/queue-6.1/arm64-dts-rockchip-fix-the-dcdc_reg2-minimum-voltage-on-quartz64-model-b.patch b/queue-6.1/arm64-dts-rockchip-fix-the-dcdc_reg2-minimum-voltage-on-quartz64-model-b.patch new file mode 100644 index 00000000000..014a0d62fe0 --- /dev/null +++ b/queue-6.1/arm64-dts-rockchip-fix-the-dcdc_reg2-minimum-voltage-on-quartz64-model-b.patch @@ -0,0 +1,56 @@ +From d201c92bff90f3d3d0b079fc955378c15c0483cc Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Mon, 20 May 2024 19:20:28 +0200 +Subject: arm64: dts: rockchip: Fix the DCDC_REG2 minimum voltage on Quartz64 Model B + +From: Dragan Simic + +commit d201c92bff90f3d3d0b079fc955378c15c0483cc upstream. + +Correct the specified regulator-min-microvolt value for the buck DCDC_REG2 +regulator, which is part of the Rockchip RK809 PMIC, in the Pine64 Quartz64 +Model B board dts. According to the RK809 datasheet, version 1.01, this +regulator is capable of producing voltages as low as 0.5 V on its output, +instead of going down to 0.9 V only, which is additionally confirmed by the +regulator-min-microvolt values found in the board dts files for the other +supported boards that use the same RK809 PMIC. + +This allows the DVFS to clock the GPU on the Quartz64 Model B below 700 MHz, +all the way down to 200 MHz, which saves some power and reduces the amount of +generated heat a bit, improving the thermal headroom and possibly improving +the bursty CPU and GPU performance on this board. + +This also eliminates the following warnings in the kernel log: + + core: _opp_supported_by_regulators: OPP minuV: 825000 maxuV: 825000, not supported by regulator + panfrost fde60000.gpu: _opp_add: OPP not supported by regulators (200000000) + core: _opp_supported_by_regulators: OPP minuV: 825000 maxuV: 825000, not supported by regulator + panfrost fde60000.gpu: _opp_add: OPP not supported by regulators (300000000) + core: _opp_supported_by_regulators: OPP minuV: 825000 maxuV: 825000, not supported by regulator + panfrost fde60000.gpu: _opp_add: OPP not supported by regulators (400000000) + core: _opp_supported_by_regulators: OPP minuV: 825000 maxuV: 825000, not supported by regulator + panfrost fde60000.gpu: _opp_add: OPP not supported by regulators (600000000) + +Fixes: dcc8c66bef79 ("arm64: dts: rockchip: add Pine64 Quartz64-B device tree") +Cc: stable@vger.kernel.org +Reported-By: Diederik de Haas +Signed-off-by: Dragan Simic +Tested-by: Diederik de Haas +Link: https://lore.kernel.org/r/e70742ea2df432bf57b3f7de542d81ca22b0da2f.1716225483.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +@@ -290,7 +290,7 @@ + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <900000>; ++ regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; diff --git a/queue-6.1/bnx2x-fix-multiple-ubsan-array-index-out-of-bounds.patch b/queue-6.1/bnx2x-fix-multiple-ubsan-array-index-out-of-bounds.patch new file mode 100644 index 00000000000..0a7d28b95ad --- /dev/null +++ b/queue-6.1/bnx2x-fix-multiple-ubsan-array-index-out-of-bounds.patch @@ -0,0 +1,185 @@ +From 134061163ee5ca4759de5c24ca3bd71608891ba7 Mon Sep 17 00:00:00 2001 +From: Ghadi Elie Rahme +Date: Thu, 27 Jun 2024 14:14:05 +0300 +Subject: bnx2x: Fix multiple UBSAN array-index-out-of-bounds + +From: Ghadi Elie Rahme + +commit 134061163ee5ca4759de5c24ca3bd71608891ba7 upstream. + +Fix UBSAN warnings that occur when using a system with 32 physical +cpu cores or more, or when the user defines a number of Ethernet +queues greater than or equal to FP_SB_MAX_E1x using the num_queues +module parameter. + +Currently there is a read/write out of bounds that occurs on the array +"struct stats_query_entry query" present inside the "bnx2x_fw_stats_req" +struct in "drivers/net/ethernet/broadcom/bnx2x/bnx2x.h". +Looking at the definition of the "struct stats_query_entry query" array: + +struct stats_query_entry query[FP_SB_MAX_E1x+ + BNX2X_FIRST_QUEUE_QUERY_IDX]; + +FP_SB_MAX_E1x is defined as the maximum number of fast path interrupts and +has a value of 16, while BNX2X_FIRST_QUEUE_QUERY_IDX has a value of 3 +meaning the array has a total size of 19. +Since accesses to "struct stats_query_entry query" are offset-ted by +BNX2X_FIRST_QUEUE_QUERY_IDX, that means that the total number of Ethernet +queues should not exceed FP_SB_MAX_E1x (16). However one of these queues +is reserved for FCOE and thus the number of Ethernet queues should be set +to [FP_SB_MAX_E1x -1] (15) if FCOE is enabled or [FP_SB_MAX_E1x] (16) if +it is not. + +This is also described in a comment in the source code in +drivers/net/ethernet/broadcom/bnx2x/bnx2x.h just above the Macro definition +of FP_SB_MAX_E1x. Below is the part of this explanation that it important +for this patch + +/* + * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is + * control by the number of fast-path status blocks supported by the + * device (HW/FW). Each fast-path status block (FP-SB) aka non-default + * status block represents an independent interrupts context that can + * serve a regular L2 networking queue. However special L2 queues such + * as the FCoE queue do not require a FP-SB and other components like + * the CNIC may consume FP-SB reducing the number of possible L2 queues + * + * If the maximum number of FP-SB available is X then: + * a. If CNIC is supported it consumes 1 FP-SB thus the max number of + * regular L2 queues is Y=X-1 + * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) + * c. If the FCoE L2 queue is supported the actual number of L2 queues + * is Y+1 + * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for + * slow-path interrupts) or Y+2 if CNIC is supported (one additional + * FP interrupt context for the CNIC). + * e. The number of HW context (CID count) is always X or X+1 if FCoE + * L2 queue is supported. The cid for the FCoE L2 queue is always X. + */ + +However this driver also supports NICs that use the E2 controller which can +handle more queues due to having more FP-SB represented by FP_SB_MAX_E2. +Looking at the commits when the E2 support was added, it was originally +using the E1x parameters: commit f2e0899f0f27 ("bnx2x: Add 57712 support"). +Back then FP_SB_MAX_E2 was set to 16 the same as E1x. However the driver +was later updated to take full advantage of the E2 instead of having it be +limited to the capabilities of the E1x. But as far as we can tell, the +array "stats_query_entry query" was still limited to using the FP-SB +available to the E1x cards as part of an oversignt when the driver was +updated to take full advantage of the E2, and now with the driver being +aware of the greater queue size supported by E2 NICs, it causes the UBSAN +warnings seen in the stack traces below. + +This patch increases the size of the "stats_query_entry query" array by +replacing FP_SB_MAX_E1x with FP_SB_MAX_E2 to be large enough to handle +both types of NICs. + +Stack traces: + +UBSAN: array-index-out-of-bounds in + drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c:1529:11 +index 20 is out of range for type 'stats_query_entry [19]' +CPU: 12 PID: 858 Comm: systemd-network Not tainted 6.9.0-060900rc7-generic + #202405052133 +Hardware name: HP ProLiant DL360 Gen9/ProLiant DL360 Gen9, + BIOS P89 10/21/2019 +Call Trace: + + dump_stack_lvl+0x76/0xa0 + dump_stack+0x10/0x20 + __ubsan_handle_out_of_bounds+0xcb/0x110 + bnx2x_prep_fw_stats_req+0x2e1/0x310 [bnx2x] + bnx2x_stats_init+0x156/0x320 [bnx2x] + bnx2x_post_irq_nic_init+0x81/0x1a0 [bnx2x] + bnx2x_nic_load+0x8e8/0x19e0 [bnx2x] + bnx2x_open+0x16b/0x290 [bnx2x] + __dev_open+0x10e/0x1d0 +RIP: 0033:0x736223927a0a +Code: d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 f3 0f 1e fa 41 89 ca + 64 8b 04 25 18 00 00 00 85 c0 75 15 b8 2c 00 00 00 0f 05 <48> 3d 00 + f0 ff ff 77 7e c3 0f 1f 44 00 00 41 54 48 83 ec 30 44 89 +RSP: 002b:00007ffc0bb2ada8 EFLAGS: 00000246 ORIG_RAX: 000000000000002c +RAX: ffffffffffffffda RBX: 0000583df50f9c78 RCX: 0000736223927a0a +RDX: 0000000000000020 RSI: 0000583df50ee510 RDI: 0000000000000003 +RBP: 0000583df50d4940 R08: 00007ffc0bb2adb0 R09: 0000000000000080 +R10: 0000000000000000 R11: 0000000000000246 R12: 0000583df5103ae0 +R13: 000000000000035a R14: 0000583df50f9c30 R15: 0000583ddddddf00 + +---[ end trace ]--- +------------[ cut here ]------------ +UBSAN: array-index-out-of-bounds in + drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c:1546:11 +index 28 is out of range for type 'stats_query_entry [19]' +CPU: 12 PID: 858 Comm: systemd-network Not tainted 6.9.0-060900rc7-generic + #202405052133 +Hardware name: HP ProLiant DL360 Gen9/ProLiant DL360 Gen9, + BIOS P89 10/21/2019 +Call Trace: + +dump_stack_lvl+0x76/0xa0 +dump_stack+0x10/0x20 +__ubsan_handle_out_of_bounds+0xcb/0x110 +bnx2x_prep_fw_stats_req+0x2fd/0x310 [bnx2x] +bnx2x_stats_init+0x156/0x320 [bnx2x] +bnx2x_post_irq_nic_init+0x81/0x1a0 [bnx2x] +bnx2x_nic_load+0x8e8/0x19e0 [bnx2x] +bnx2x_open+0x16b/0x290 [bnx2x] +__dev_open+0x10e/0x1d0 +RIP: 0033:0x736223927a0a +Code: d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 f3 0f 1e fa 41 89 ca + 64 8b 04 25 18 00 00 00 85 c0 75 15 b8 2c 00 00 00 0f 05 <48> 3d 00 + f0 ff ff 77 7e c3 0f 1f 44 00 00 41 54 48 83 ec 30 44 89 +RSP: 002b:00007ffc0bb2ada8 EFLAGS: 00000246 ORIG_RAX: 000000000000002c +RAX: ffffffffffffffda RBX: 0000583df50f9c78 RCX: 0000736223927a0a +RDX: 0000000000000020 RSI: 0000583df50ee510 RDI: 0000000000000003 +RBP: 0000583df50d4940 R08: 00007ffc0bb2adb0 R09: 0000000000000080 +R10: 0000000000000000 R11: 0000000000000246 R12: 0000583df5103ae0 +R13: 000000000000035a R14: 0000583df50f9c30 R15: 0000583ddddddf00 + +---[ end trace ]--- +------------[ cut here ]------------ +UBSAN: array-index-out-of-bounds in + drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c:1895:8 +index 29 is out of range for type 'stats_query_entry [19]' +CPU: 13 PID: 163 Comm: kworker/u96:1 Not tainted 6.9.0-060900rc7-generic + #202405052133 +Hardware name: HP ProLiant DL360 Gen9/ProLiant DL360 Gen9, + BIOS P89 10/21/2019 +Workqueue: bnx2x bnx2x_sp_task [bnx2x] +Call Trace: + + dump_stack_lvl+0x76/0xa0 + dump_stack+0x10/0x20 + __ubsan_handle_out_of_bounds+0xcb/0x110 + bnx2x_iov_adjust_stats_req+0x3c4/0x3d0 [bnx2x] + bnx2x_storm_stats_post.part.0+0x4a/0x330 [bnx2x] + ? bnx2x_hw_stats_post+0x231/0x250 [bnx2x] + bnx2x_stats_start+0x44/0x70 [bnx2x] + bnx2x_stats_handle+0x149/0x350 [bnx2x] + bnx2x_attn_int_asserted+0x998/0x9b0 [bnx2x] + bnx2x_sp_task+0x491/0x5c0 [bnx2x] + process_one_work+0x18d/0x3f0 + +---[ end trace ]--- + +Fixes: 50f0a562f8cc ("bnx2x: add fcoe statistics") +Signed-off-by: Ghadi Elie Rahme +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20240627111405.1037812-1-ghadi.rahme@canonical.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h ++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h +@@ -1262,7 +1262,7 @@ enum { + + struct bnx2x_fw_stats_req { + struct stats_query_header hdr; +- struct stats_query_entry query[FP_SB_MAX_E1x+ ++ struct stats_query_entry query[FP_SB_MAX_E2 + + BNX2X_FIRST_QUEUE_QUERY_IDX]; + }; + diff --git a/queue-6.1/drm-amdgpu-atomfirmware-silence-ubsan-warning.patch b/queue-6.1/drm-amdgpu-atomfirmware-silence-ubsan-warning.patch new file mode 100644 index 00000000000..7fcad809894 --- /dev/null +++ b/queue-6.1/drm-amdgpu-atomfirmware-silence-ubsan-warning.patch @@ -0,0 +1,31 @@ +From d0417264437a8fa05f894cabba5a26715b32d78e Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 1 Jul 2024 12:50:10 -0400 +Subject: drm/amdgpu/atomfirmware: silence UBSAN warning + +From: Alex Deucher + +commit d0417264437a8fa05f894cabba5a26715b32d78e upstream. + +This is a variable sized array. + +Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html +Tested-by: Jeff Layton +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/include/atomfirmware.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/include/atomfirmware.h ++++ b/drivers/gpu/drm/amd/include/atomfirmware.h +@@ -701,7 +701,7 @@ struct atom_gpio_pin_lut_v2_1 + { + struct atom_common_table_header table_header; + /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ +- struct atom_gpio_pin_assignment gpio_pin[8]; ++ struct atom_gpio_pin_assignment gpio_pin[]; + }; + + diff --git a/queue-6.1/drm-nouveau-fix-null-pointer-dereference-in-nouveau_connector_get_modes.patch b/queue-6.1/drm-nouveau-fix-null-pointer-dereference-in-nouveau_connector_get_modes.patch new file mode 100644 index 00000000000..49a25eaa1e6 --- /dev/null +++ b/queue-6.1/drm-nouveau-fix-null-pointer-dereference-in-nouveau_connector_get_modes.patch @@ -0,0 +1,35 @@ +From 80bec6825b19d95ccdfd3393cf8ec15ff2a749b4 Mon Sep 17 00:00:00 2001 +From: Ma Ke +Date: Thu, 27 Jun 2024 15:42:04 +0800 +Subject: drm/nouveau: fix null pointer dereference in nouveau_connector_get_modes + +From: Ma Ke + +commit 80bec6825b19d95ccdfd3393cf8ec15ff2a749b4 upstream. + +In nouveau_connector_get_modes(), the return value of drm_mode_duplicate() +is assigned to mode, which will lead to a possible NULL pointer +dereference on failure of drm_mode_duplicate(). Add a check to avoid npd. + +Cc: stable@vger.kernel.org +Fixes: 6ee738610f41 ("drm/nouveau: Add DRM driver for NVIDIA GPUs") +Signed-off-by: Ma Ke +Signed-off-by: Lyude Paul +Link: https://patchwork.freedesktop.org/patch/msgid/20240627074204.3023776-1-make24@iscas.ac.cn +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/nouveau/nouveau_connector.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/nouveau/nouveau_connector.c ++++ b/drivers/gpu/drm/nouveau/nouveau_connector.c +@@ -980,6 +980,9 @@ nouveau_connector_get_modes(struct drm_c + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(dev, nv_connector->native_mode); ++ if (!mode) ++ return 0; ++ + drm_mode_probed_add(connector, mode); + ret = 1; + } diff --git a/queue-6.1/drm-panel-orientation-quirks-add-quirk-for-valve-galileo.patch b/queue-6.1/drm-panel-orientation-quirks-add-quirk-for-valve-galileo.patch new file mode 100644 index 00000000000..49c215021d5 --- /dev/null +++ b/queue-6.1/drm-panel-orientation-quirks-add-quirk-for-valve-galileo.patch @@ -0,0 +1,37 @@ +From 26746ed40bb0e4ebe2b2bd61c04eaaa54e263c14 Mon Sep 17 00:00:00 2001 +From: John Schoenick +Date: Fri, 28 Jun 2024 13:58:21 -0700 +Subject: drm: panel-orientation-quirks: Add quirk for Valve Galileo + +From: John Schoenick + +commit 26746ed40bb0e4ebe2b2bd61c04eaaa54e263c14 upstream. + +Valve's Steam Deck Galileo revision has a 800x1280 OLED panel + +Cc: stable@vger.kernel.org # 6.1+ +Signed-off-by: John Schoenick +Signed-off-by: Matthew Schwartz +Signed-off-by: Hamza Mahfooz +Link: https://patchwork.freedesktop.org/patch/msgid/20240628205822.348402-2-mattschwartz@gwu.edu +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/drm_panel_orientation_quirks.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c ++++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c +@@ -421,6 +421,13 @@ static const struct dmi_system_id orient + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "1"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, ++ }, { /* Valve Steam Deck */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Valve"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Galileo"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "1"), ++ }, ++ .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* VIOS LTH17 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "VIOS"), diff --git a/queue-6.1/mtd-rawnand-bypass-a-couple-of-sanity-checks-during-nand-identification.patch b/queue-6.1/mtd-rawnand-bypass-a-couple-of-sanity-checks-during-nand-identification.patch new file mode 100644 index 00000000000..bb0b7cd658e --- /dev/null +++ b/queue-6.1/mtd-rawnand-bypass-a-couple-of-sanity-checks-during-nand-identification.patch @@ -0,0 +1,130 @@ +From 8754d9835683e8fab9a8305acdb38a3aeb9d20bd Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 May 2024 15:13:20 +0200 +Subject: mtd: rawnand: Bypass a couple of sanity checks during NAND identification + +From: Miquel Raynal + +commit 8754d9835683e8fab9a8305acdb38a3aeb9d20bd upstream. + +Early during NAND identification, mtd_info fields have not yet been +initialized (namely, writesize and oobsize) and thus cannot be used for +sanity checks yet. Of course if there is a misuse of +nand_change_read_column_op() so early we won't be warned, but there is +anyway no actual check to perform at this stage as we do not yet know +the NAND geometry. + +So, if the fields are empty, especially mtd->writesize which is *always* +set quite rapidly after identification, let's skip the sanity checks. + +nand_change_read_column_op() is subject to be used early for ONFI/JEDEC +identification in the very unlikely case of: +- bitflips appearing in the parameter page, +- the controller driver not supporting simple DATA_IN cycles. + +As nand_change_read_column_op() uses nand_fill_column_cycles() the logic +explaind above also applies in this secondary helper. + +Fixes: c27842e7e11f ("mtd: rawnand: onfi: Adapt the parameter page read to constraint controllers") +Fixes: daca31765e8b ("mtd: rawnand: jedec: Adapt the parameter page read to constraint controllers") +Cc: stable@vger.kernel.org +Reported-by: Alexander Dahl +Closes: https://lore.kernel.org/linux-mtd/20240306-shaky-bunion-d28b65ea97d7@thorsis.com/ +Reported-by: Steven Seeger +Closes: https://lore.kernel.org/linux-mtd/DM6PR05MB4506554457CF95191A670BDEF7062@DM6PR05MB4506.namprd05.prod.outlook.com/ +Signed-off-by: Miquel Raynal +Tested-by: Sascha Hauer +Link: https://lore.kernel.org/linux-mtd/20240516131320.579822-3-miquel.raynal@bootlin.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/nand_base.c | 57 +++++++++++++++++++++------------------ + 1 file changed, 32 insertions(+), 25 deletions(-) + +--- a/drivers/mtd/nand/raw/nand_base.c ++++ b/drivers/mtd/nand/raw/nand_base.c +@@ -1090,28 +1090,32 @@ static int nand_fill_column_cycles(struc + unsigned int offset_in_page) + { + struct mtd_info *mtd = nand_to_mtd(chip); ++ bool ident_stage = !mtd->writesize; + +- /* Make sure the offset is less than the actual page size. */ +- if (offset_in_page > mtd->writesize + mtd->oobsize) +- return -EINVAL; +- +- /* +- * On small page NANDs, there's a dedicated command to access the OOB +- * area, and the column address is relative to the start of the OOB +- * area, not the start of the page. Asjust the address accordingly. +- */ +- if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) +- offset_in_page -= mtd->writesize; +- +- /* +- * The offset in page is expressed in bytes, if the NAND bus is 16-bit +- * wide, then it must be divided by 2. +- */ +- if (chip->options & NAND_BUSWIDTH_16) { +- if (WARN_ON(offset_in_page % 2)) ++ /* Bypass all checks during NAND identification */ ++ if (likely(!ident_stage)) { ++ /* Make sure the offset is less than the actual page size. */ ++ if (offset_in_page > mtd->writesize + mtd->oobsize) + return -EINVAL; + +- offset_in_page /= 2; ++ /* ++ * On small page NANDs, there's a dedicated command to access the OOB ++ * area, and the column address is relative to the start of the OOB ++ * area, not the start of the page. Asjust the address accordingly. ++ */ ++ if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) ++ offset_in_page -= mtd->writesize; ++ ++ /* ++ * The offset in page is expressed in bytes, if the NAND bus is 16-bit ++ * wide, then it must be divided by 2. ++ */ ++ if (chip->options & NAND_BUSWIDTH_16) { ++ if (WARN_ON(offset_in_page % 2)) ++ return -EINVAL; ++ ++ offset_in_page /= 2; ++ } + } + + addrs[0] = offset_in_page; +@@ -1120,7 +1124,7 @@ static int nand_fill_column_cycles(struc + * Small page NANDs use 1 cycle for the columns, while large page NANDs + * need 2 + */ +- if (mtd->writesize <= 512) ++ if (!ident_stage && mtd->writesize <= 512) + return 1; + + addrs[1] = offset_in_page >> 8; +@@ -1316,16 +1320,19 @@ int nand_change_read_column_op(struct na + unsigned int len, bool force_8bit) + { + struct mtd_info *mtd = nand_to_mtd(chip); ++ bool ident_stage = !mtd->writesize; + + if (len && !buf) + return -EINVAL; + +- if (offset_in_page + len > mtd->writesize + mtd->oobsize) +- return -EINVAL; ++ if (!ident_stage) { ++ if (offset_in_page + len > mtd->writesize + mtd->oobsize) ++ return -EINVAL; + +- /* Small page NANDs do not support column change. */ +- if (mtd->writesize <= 512) +- return -ENOTSUPP; ++ /* Small page NANDs do not support column change. */ ++ if (mtd->writesize <= 512) ++ return -ENOTSUPP; ++ } + + if (nand_has_exec_op(chip)) { + const struct nand_interface_config *conf = diff --git a/queue-6.1/mtd-rawnand-ensure-ecc-configuration-is-propagated-to-upper-layers.patch b/queue-6.1/mtd-rawnand-ensure-ecc-configuration-is-propagated-to-upper-layers.patch new file mode 100644 index 00000000000..e94693f2378 --- /dev/null +++ b/queue-6.1/mtd-rawnand-ensure-ecc-configuration-is-propagated-to-upper-layers.patch @@ -0,0 +1,68 @@ +From 3a1b777eb9fb75d09c45ae5dd1d007eddcbebf1f Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Tue, 7 May 2024 10:58:42 +0200 +Subject: mtd: rawnand: Ensure ECC configuration is propagated to upper layers + +From: Miquel Raynal + +commit 3a1b777eb9fb75d09c45ae5dd1d007eddcbebf1f upstream. + +Until recently the "upper layer" was MTD. But following incremental +reworks to bring spi-nand support and more recently generic ECC support, +there is now an intermediate "generic NAND" layer that also needs to get +access to some values. When using "converted" ECC engines, like the +software ones, these values are already propagated correctly. But +otherwise when using good old raw NAND controller drivers, we need to +manually set these values ourselves at the end of the "scan" operation, +once these values have been negotiated. + +Without this propagation, later (generic) checks like the one warning +users that the ECC strength is not high enough might simply no longer +work. + +Fixes: 8c126720fe10 ("mtd: rawnand: Use the ECC framework nand_ecc_is_strong_enough() helper") +Cc: stable@vger.kernel.org +Reported-by: Sascha Hauer +Closes: https://lore.kernel.org/all/Zhe2JtvvN1M4Ompw@pengutronix.de/ +Signed-off-by: Miquel Raynal +Tested-by: Sascha Hauer +Link: https://lore.kernel.org/linux-mtd/20240507085842.108844-1-miquel.raynal@bootlin.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/nand_base.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/raw/nand_base.c ++++ b/drivers/mtd/nand/raw/nand_base.c +@@ -6062,6 +6062,7 @@ static const struct nand_ops rawnand_ops + static int nand_scan_tail(struct nand_chip *chip) + { + struct mtd_info *mtd = nand_to_mtd(chip); ++ struct nand_device *base = &chip->base; + struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret, i; + +@@ -6206,9 +6207,13 @@ static int nand_scan_tail(struct nand_ch + if (!ecc->write_oob_raw) + ecc->write_oob_raw = ecc->write_oob; + +- /* propagate ecc info to mtd_info */ ++ /* Propagate ECC info to the generic NAND and MTD layers */ + mtd->ecc_strength = ecc->strength; ++ if (!base->ecc.ctx.conf.strength) ++ base->ecc.ctx.conf.strength = ecc->strength; + mtd->ecc_step_size = ecc->size; ++ if (!base->ecc.ctx.conf.step_size) ++ base->ecc.ctx.conf.step_size = ecc->size; + + /* + * Set the number of read / write steps for one page depending on ECC +@@ -6216,6 +6221,8 @@ static int nand_scan_tail(struct nand_ch + */ + if (!ecc->steps) + ecc->steps = mtd->writesize / ecc->size; ++ if (!base->ecc.ctx.nsteps) ++ base->ecc.ctx.nsteps = ecc->steps; + if (ecc->steps * ecc->size != mtd->writesize) { + WARN(1, "Invalid ECC parameters\n"); + ret = -EINVAL; diff --git a/queue-6.1/mtd-rawnand-rockchip-ensure-nvddr-timings-are-rejected.patch b/queue-6.1/mtd-rawnand-rockchip-ensure-nvddr-timings-are-rejected.patch new file mode 100644 index 00000000000..961e7303b03 --- /dev/null +++ b/queue-6.1/mtd-rawnand-rockchip-ensure-nvddr-timings-are-rejected.patch @@ -0,0 +1,42 @@ +From b27d8946b5edd9827ee3c2f9ea1dd30022fb1ebe Mon Sep 17 00:00:00 2001 +From: Val Packett +Date: Sun, 19 May 2024 00:13:39 -0300 +Subject: mtd: rawnand: rockchip: ensure NVDDR timings are rejected + +From: Val Packett + +commit b27d8946b5edd9827ee3c2f9ea1dd30022fb1ebe upstream. + +.setup_interface first gets called with a "target" value of +NAND_DATA_IFACE_CHECK_ONLY, in which case an error is expected +if the controller driver does not support the timing mode (NVDDR). + +Fixes: a9ecc8c814e9 ("mtd: rawnand: Choose the best timings, NV-DDR included") +Signed-off-by: Val Packett +Cc: stable@vger.kernel.org +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240519031409.26464-1-val@packett.cool +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/rockchip-nand-controller.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/raw/rockchip-nand-controller.c ++++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c +@@ -421,13 +421,13 @@ static int rk_nfc_setup_interface(struct + u32 rate, tc2rw, trwpw, trw2c; + u32 temp; + +- if (target < 0) +- return 0; +- + timings = nand_get_sdr_timings(conf); + if (IS_ERR(timings)) + return -EOPNOTSUPP; + ++ if (target < 0) ++ return 0; ++ + if (IS_ERR(nfc->nfc_clk)) + rate = clk_get_rate(nfc->ahb_clk); + else diff --git a/queue-6.1/powerpc-pseries-fix-scv-instruction-crash-with-kexec.patch b/queue-6.1/powerpc-pseries-fix-scv-instruction-crash-with-kexec.patch new file mode 100644 index 00000000000..ba58108903c --- /dev/null +++ b/queue-6.1/powerpc-pseries-fix-scv-instruction-crash-with-kexec.patch @@ -0,0 +1,100 @@ +From 21a741eb75f80397e5f7d3739e24d7d75e619011 Mon Sep 17 00:00:00 2001 +From: Nicholas Piggin +Date: Tue, 25 Jun 2024 23:40:47 +1000 +Subject: powerpc/pseries: Fix scv instruction crash with kexec + +From: Nicholas Piggin + +commit 21a741eb75f80397e5f7d3739e24d7d75e619011 upstream. + +kexec on pseries disables AIL (reloc_on_exc), required for scv +instruction support, before other CPUs have been shut down. This means +they can execute scv instructions after AIL is disabled, which causes an +interrupt at an unexpected entry location that crashes the kernel. + +Change the kexec sequence to disable AIL after other CPUs have been +brought down. + +As a refresher, the real-mode scv interrupt vector is 0x17000, and the +fixed-location head code probably couldn't easily deal with implementing +such high addresses so it was just decided not to support that interrupt +at all. + +Fixes: 7fa95f9adaee ("powerpc/64s: system call support for scv/rfscv instructions") +Cc: stable@vger.kernel.org # v5.9+ +Reported-by: Sourabh Jain +Closes: https://lore.kernel.org/3b4b2943-49ad-4619-b195-bc416f1d1409@linux.ibm.com +Signed-off-by: Nicholas Piggin +Tested-by: Gautam Menghani +Tested-by: Sourabh Jain +Link: https://msgid.link/20240625134047.298759-1-npiggin@gmail.com +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman +--- + arch/powerpc/kexec/core_64.c | 11 +++++++++++ + arch/powerpc/platforms/pseries/kexec.c | 8 -------- + arch/powerpc/platforms/pseries/pseries.h | 1 - + arch/powerpc/platforms/pseries/setup.c | 1 - + 4 files changed, 11 insertions(+), 10 deletions(-) + +--- a/arch/powerpc/kexec/core_64.c ++++ b/arch/powerpc/kexec/core_64.c +@@ -26,6 +26,7 @@ + #include + #include + #include /* _end */ ++#include + #include + #include + #include +@@ -316,6 +317,16 @@ void default_machine_kexec(struct kimage + if (!kdump_in_progress()) + kexec_prepare_cpus(); + ++#ifdef CONFIG_PPC_PSERIES ++ /* ++ * This must be done after other CPUs have shut down, otherwise they ++ * could execute the 'scv' instruction, which is not supported with ++ * reloc disabled (see configure_exceptions()). ++ */ ++ if (firmware_has_feature(FW_FEATURE_SET_MODE)) ++ pseries_disable_reloc_on_exc(); ++#endif ++ + printk("kexec: Starting switchover sequence.\n"); + + /* switch to a staticly allocated stack. Based on irq stack code. +--- a/arch/powerpc/platforms/pseries/kexec.c ++++ b/arch/powerpc/platforms/pseries/kexec.c +@@ -61,11 +61,3 @@ void pseries_kexec_cpu_down(int crash_sh + } else + xics_kexec_teardown_cpu(secondary); + } +- +-void pseries_machine_kexec(struct kimage *image) +-{ +- if (firmware_has_feature(FW_FEATURE_SET_MODE)) +- pseries_disable_reloc_on_exc(); +- +- default_machine_kexec(image); +-} +--- a/arch/powerpc/platforms/pseries/pseries.h ++++ b/arch/powerpc/platforms/pseries/pseries.h +@@ -38,7 +38,6 @@ static inline void smp_init_pseries(void + #endif + + extern void pseries_kexec_cpu_down(int crash_shutdown, int secondary); +-void pseries_machine_kexec(struct kimage *image); + + extern void pSeries_final_fixup(void); + +--- a/arch/powerpc/platforms/pseries/setup.c ++++ b/arch/powerpc/platforms/pseries/setup.c +@@ -1149,7 +1149,6 @@ define_machine(pseries) { + .machine_check_exception = pSeries_machine_check_exception, + .machine_check_log_err = pSeries_machine_check_log_err, + #ifdef CONFIG_KEXEC_CORE +- .machine_kexec = pseries_machine_kexec, + .kexec_cpu_down = pseries_kexec_cpu_down, + #endif + #ifdef CONFIG_MEMORY_HOTPLUG diff --git a/queue-6.1/revert-mm-writeback-fix-possible-divide-by-zero-in-wb_dirty_limits-again.patch b/queue-6.1/revert-mm-writeback-fix-possible-divide-by-zero-in-wb_dirty_limits-again.patch new file mode 100644 index 00000000000..59ff9152cf9 --- /dev/null +++ b/queue-6.1/revert-mm-writeback-fix-possible-divide-by-zero-in-wb_dirty_limits-again.patch @@ -0,0 +1,53 @@ +From 30139c702048f1097342a31302cbd3d478f50c63 Mon Sep 17 00:00:00 2001 +From: Jan Kara +Date: Fri, 21 Jun 2024 16:42:37 +0200 +Subject: Revert "mm/writeback: fix possible divide-by-zero in wb_dirty_limits(), again" + +From: Jan Kara + +commit 30139c702048f1097342a31302cbd3d478f50c63 upstream. + +Patch series "mm: Avoid possible overflows in dirty throttling". + +Dirty throttling logic assumes dirty limits in page units fit into +32-bits. This patch series makes sure this is true (see patch 2/2 for +more details). + + +This patch (of 2): + +This reverts commit 9319b647902cbd5cc884ac08a8a6d54ce111fc78. + +The commit is broken in several ways. Firstly, the removed (u64) cast +from the multiplication will introduce a multiplication overflow on 32-bit +archs if wb_thresh * bg_thresh >= 1<<32 (which is actually common - the +default settings with 4GB of RAM will trigger this). Secondly, the +div64_u64() is unnecessarily expensive on 32-bit archs. We have +div64_ul() in case we want to be safe & cheap. Thirdly, if dirty +thresholds are larger than 1<<32 pages, then dirty balancing is going to +blow up in many other spectacular ways anyway so trying to fix one +possible overflow is just moot. + +Link: https://lkml.kernel.org/r/20240621144017.30993-1-jack@suse.cz +Link: https://lkml.kernel.org/r/20240621144246.11148-1-jack@suse.cz +Fixes: 9319b647902c ("mm/writeback: fix possible divide-by-zero in wb_dirty_limits(), again") +Signed-off-by: Jan Kara +Reviewed-By: Zach O'Keefe +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Greg Kroah-Hartman +--- + mm/page-writeback.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/mm/page-writeback.c ++++ b/mm/page-writeback.c +@@ -1548,7 +1548,7 @@ static inline void wb_dirty_limits(struc + */ + dtc->wb_thresh = __wb_calc_thresh(dtc); + dtc->wb_bg_thresh = dtc->thresh ? +- div64_u64(dtc->wb_thresh * dtc->bg_thresh, dtc->thresh) : 0; ++ div_u64((u64)dtc->wb_thresh * dtc->bg_thresh, dtc->thresh) : 0; + + /* + * In order to avoid the stacked BDI deadlock we need diff --git a/queue-6.1/series b/queue-6.1/series index 3b2d5fee946..a8e0758deee 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -79,3 +79,13 @@ scsi-mpi3mr-use-proper-format-specifier-in-mpi3mr_sas_port_add.patch bluetooth-qca-fix-bt-enable-failure-again-for-qca6390-after-warm-reboot.patch can-kvaser_usb-explicitly-initialize-family-in-leafimx-driver_info-struct.patch fsnotify-do-not-generate-events-for-o_path-file-descriptors.patch +revert-mm-writeback-fix-possible-divide-by-zero-in-wb_dirty_limits-again.patch +drm-nouveau-fix-null-pointer-dereference-in-nouveau_connector_get_modes.patch +drm-amdgpu-atomfirmware-silence-ubsan-warning.patch +drm-panel-orientation-quirks-add-quirk-for-valve-galileo.patch +powerpc-pseries-fix-scv-instruction-crash-with-kexec.patch +mtd-rawnand-ensure-ecc-configuration-is-propagated-to-upper-layers.patch +mtd-rawnand-bypass-a-couple-of-sanity-checks-during-nand-identification.patch +mtd-rawnand-rockchip-ensure-nvddr-timings-are-rejected.patch +bnx2x-fix-multiple-ubsan-array-index-out-of-bounds.patch +arm64-dts-rockchip-fix-the-dcdc_reg2-minimum-voltage-on-quartz64-model-b.patch