From: Greg Kroah-Hartman Date: Thu, 19 Dec 2019 15:05:39 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v4.4.207~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=33a89a0110df061ff00037ee0bc8a833c69689a0;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: drm-amdgpu-add-invalidate-semaphore-limit-for-sriov-and-picasso-in-gmc9.patch drm-amdgpu-avoid-using-invalidate-semaphore-for-picasso.patch --- diff --git a/queue-5.4/drm-amdgpu-add-invalidate-semaphore-limit-for-sriov-and-picasso-in-gmc9.patch b/queue-5.4/drm-amdgpu-add-invalidate-semaphore-limit-for-sriov-and-picasso-in-gmc9.patch new file mode 100644 index 00000000000..eade69375e2 --- /dev/null +++ b/queue-5.4/drm-amdgpu-add-invalidate-semaphore-limit-for-sriov-and-picasso-in-gmc9.patch @@ -0,0 +1,121 @@ +From 90f6452ca58d436de4f69b423ecd75a109aa9766 Mon Sep 17 00:00:00 2001 +From: changzhu +Date: Tue, 10 Dec 2019 22:00:59 +0800 +Subject: drm/amdgpu: add invalidate semaphore limit for SRIOV and picasso in gmc9 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: changzhu + +commit 90f6452ca58d436de4f69b423ecd75a109aa9766 upstream. + +It may fail to load guest driver in round 2 or cause Xstart problem +when using invalidate semaphore for SRIOV or picasso. So it needs avoid +using invalidate semaphore for SRIOV and picasso. + +Signed-off-by: changzhu +Reviewed-by: Christian König +Reviewed-by: Huang Rui +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 44 ++++++++++++++++++---------------- + 1 file changed, 24 insertions(+), 20 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -448,6 +448,24 @@ static uint32_t gmc_v9_0_get_invalidate_ + return req; + } + ++/** ++ * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore ++ * ++ * @adev: amdgpu_device pointer ++ * @vmhub: vmhub type ++ * ++ */ ++static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, ++ uint32_t vmhub) ++{ ++ return ((vmhub == AMDGPU_MMHUB_0 || ++ vmhub == AMDGPU_MMHUB_1) && ++ (!amdgpu_sriov_vf(adev)) && ++ (!(adev->asic_type == CHIP_RAVEN && ++ adev->rev_id < 0x8 && ++ adev->pdev->device == 0x15d8))); ++} ++ + /* + * GART + * VMID 0 is the physical GPU addresses as used by the kernel. +@@ -467,6 +485,7 @@ static uint32_t gmc_v9_0_get_invalidate_ + static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, + uint32_t vmhub, uint32_t flush_type) + { ++ bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); + const unsigned eng = 17; + u32 j, tmp; + struct amdgpu_vmhub *hub; +@@ -500,11 +519,7 @@ static void gmc_v9_0_flush_gpu_tlb(struc + */ + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if ((vmhub == AMDGPU_MMHUB_0 || +- vmhub == AMDGPU_MMHUB_1) && +- (!(adev->asic_type == CHIP_RAVEN && +- adev->rev_id < 0x8 && +- adev->pdev->device == 0x15d8))) { ++ if (use_semaphore) { + for (j = 0; j < adev->usec_timeout; j++) { + /* a read return value of 1 means semaphore acuqire */ + tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); +@@ -534,11 +549,7 @@ static void gmc_v9_0_flush_gpu_tlb(struc + } + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if ((vmhub == AMDGPU_MMHUB_0 || +- vmhub == AMDGPU_MMHUB_1) && +- (!(adev->asic_type == CHIP_RAVEN && +- adev->rev_id < 0x8 && +- adev->pdev->device == 0x15d8))) ++ if (use_semaphore) + /* + * add semaphore release after invalidation, + * write with 0 means semaphore release +@@ -556,6 +567,7 @@ static void gmc_v9_0_flush_gpu_tlb(struc + static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) + { ++ bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; + uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); +@@ -569,11 +581,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_ + */ + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 || +- ring->funcs->vmhub == AMDGPU_MMHUB_1) && +- (!(adev->asic_type == CHIP_RAVEN && +- adev->rev_id < 0x8 && +- adev->pdev->device == 0x15d8))) ++ if (use_semaphore) + /* a read return value of 1 means semaphore acuqire */ + amdgpu_ring_emit_reg_wait(ring, + hub->vm_inv_eng0_sem + eng, 0x1, 0x1); +@@ -589,11 +597,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_ + req, 1 << vmid); + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 || +- ring->funcs->vmhub == AMDGPU_MMHUB_1) && +- (!(adev->asic_type == CHIP_RAVEN && +- adev->rev_id < 0x8 && +- adev->pdev->device == 0x15d8))) ++ if (use_semaphore) + /* + * add semaphore release after invalidation, + * write with 0 means semaphore release diff --git a/queue-5.4/drm-amdgpu-avoid-using-invalidate-semaphore-for-picasso.patch b/queue-5.4/drm-amdgpu-avoid-using-invalidate-semaphore-for-picasso.patch new file mode 100644 index 00000000000..55a9c8a589a --- /dev/null +++ b/queue-5.4/drm-amdgpu-avoid-using-invalidate-semaphore-for-picasso.patch @@ -0,0 +1,80 @@ +From 413fc385a594ea6eb08843be33939057ddfdae76 Mon Sep 17 00:00:00 2001 +From: changzhu +Date: Tue, 10 Dec 2019 10:23:09 +0800 +Subject: drm/amdgpu: avoid using invalidate semaphore for picasso + +From: changzhu + +commit 413fc385a594ea6eb08843be33939057ddfdae76 upstream. + +It may cause timeout waiting for sem acquire in VM flush when using +invalidate semaphore for picasso. So it needs to avoid using invalidate +semaphore for piasso. + +Signed-off-by: changzhu +Reviewed-by: Huang Rui +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 ++++++++++++++++++++-------- + 1 file changed, 20 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -500,8 +500,11 @@ static void gmc_v9_0_flush_gpu_tlb(struc + */ + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if (vmhub == AMDGPU_MMHUB_0 || +- vmhub == AMDGPU_MMHUB_1) { ++ if ((vmhub == AMDGPU_MMHUB_0 || ++ vmhub == AMDGPU_MMHUB_1) && ++ (!(adev->asic_type == CHIP_RAVEN && ++ adev->rev_id < 0x8 && ++ adev->pdev->device == 0x15d8))) { + for (j = 0; j < adev->usec_timeout; j++) { + /* a read return value of 1 means semaphore acuqire */ + tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); +@@ -531,8 +534,11 @@ static void gmc_v9_0_flush_gpu_tlb(struc + } + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if (vmhub == AMDGPU_MMHUB_0 || +- vmhub == AMDGPU_MMHUB_1) ++ if ((vmhub == AMDGPU_MMHUB_0 || ++ vmhub == AMDGPU_MMHUB_1) && ++ (!(adev->asic_type == CHIP_RAVEN && ++ adev->rev_id < 0x8 && ++ adev->pdev->device == 0x15d8))) + /* + * add semaphore release after invalidation, + * write with 0 means semaphore release +@@ -563,8 +569,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_ + */ + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if (ring->funcs->vmhub == AMDGPU_MMHUB_0 || +- ring->funcs->vmhub == AMDGPU_MMHUB_1) ++ if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 || ++ ring->funcs->vmhub == AMDGPU_MMHUB_1) && ++ (!(adev->asic_type == CHIP_RAVEN && ++ adev->rev_id < 0x8 && ++ adev->pdev->device == 0x15d8))) + /* a read return value of 1 means semaphore acuqire */ + amdgpu_ring_emit_reg_wait(ring, + hub->vm_inv_eng0_sem + eng, 0x1, 0x1); +@@ -580,8 +589,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_ + req, 1 << vmid); + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ +- if (ring->funcs->vmhub == AMDGPU_MMHUB_0 || +- ring->funcs->vmhub == AMDGPU_MMHUB_1) ++ if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 || ++ ring->funcs->vmhub == AMDGPU_MMHUB_1) && ++ (!(adev->asic_type == CHIP_RAVEN && ++ adev->rev_id < 0x8 && ++ adev->pdev->device == 0x15d8))) + /* + * add semaphore release after invalidation, + * write with 0 means semaphore release diff --git a/queue-5.4/series b/queue-5.4/series index bdfe6e915bc..429b7e9b73a 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -76,3 +76,5 @@ drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-gmc9-gmc10.patch drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-halt-unhalt.patch drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gpu-reset.patch drm-i915-gvt-fix-cmd-length-check-for-mi_atomic.patch +drm-amdgpu-avoid-using-invalidate-semaphore-for-picasso.patch +drm-amdgpu-add-invalidate-semaphore-limit-for-sriov-and-picasso-in-gmc9.patch