From: Yuta Mukai Date: Fri, 23 May 2025 04:51:11 +0000 (+0000) Subject: aarch64: Enable newly implemented features for FUJITSU-MONAKA X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=33ee574a7444b238005d89fdfdf2f21f50b1fc6e;p=thirdparty%2Fgcc.git aarch64: Enable newly implemented features for FUJITSU-MONAKA This patch enables newly implemented features in GCC (FAMINMAX, FP8FMA, FP8DOT2, FP8DOT4, LUT) for FUJITSU-MONAKA processor (-mcpu=fujitsu-monaka). 2025-05-23 Yuta Mukai gcc/ChangeLog: * config/aarch64/aarch64-cores.def (fujitsu-monaka): Update ISA features. --- diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 12096300d01..24b7cd362aa 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -132,7 +132,7 @@ AARCH64_CORE("octeontx2f95mm", octeontx2f95mm, cortexa57, V8_2A, (CRYPTO, PROFI /* Fujitsu ('F') cores. */ AARCH64_CORE("a64fx", a64fx, a64fx, V8_2A, (F16, SVE), a64fx, 0x46, 0x001, -1) -AARCH64_CORE("fujitsu-monaka", fujitsu_monaka, cortexa57, V9_3A, (F16, FP8, LS64, RNG, CRYPTO, SVE2_AES, SVE2_BITPERM, SVE2_SHA3, SVE2_SM4), fujitsu_monaka, 0x46, 0x003, -1) +AARCH64_CORE("fujitsu-monaka", fujitsu_monaka, cortexa57, V9_3A, (F16, FAMINMAX, FP8FMA, FP8DOT2, FP8DOT4, LS64, LUT, RNG, CRYPTO, SVE2_AES, SVE2_BITPERM, SVE2_SHA3, SVE2_SM4), fujitsu_monaka, 0x46, 0x003, -1) /* HiSilicon ('H') cores. */ AARCH64_CORE("tsv110", tsv110, tsv110, V8_2A, (CRYPTO, F16), tsv110, 0x48, 0xd01, -1)