From: Greg Kroah-Hartman Date: Wed, 12 Apr 2023 10:15:48 +0000 (+0200) Subject: drop sifive ccache patches from 5.15 X-Git-Tag: v5.15.107~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=344d8ad1b5dde387d1ce4d1be2641753b89dd10d;p=thirdparty%2Fkernel%2Fstable-queue.git drop sifive ccache patches from 5.15 --- diff --git a/queue-5.15/series b/queue-5.15/series index 8c0f5bfbc20..4b65332e1ca 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -1,10 +1,3 @@ -soc-sifive-ccache-rename-sifive-l2-cache-to-composab.patch -soc-sifive-ccache-determine-the-cache-level-from-dts.patch -soc-sifive-ccache-reduce-printing-on-init.patch -soc-sifive-ccache-use-pr_fmt-to-remove-ccache-prefix.patch -soc-sifive-ccache-fix-missing-iounmap-in-error-path-.patch -soc-sifive-ccache-fix-missing-free_irq-in-error-path.patch -soc-sifive-ccache-fix-missing-of_node_put-in-sifive_.patch ocfs2-ocfs2_mount_volume-does-cleanup-job-before-ret.patch ocfs2-rewrite-error-handling-of-ocfs2_fill_super.patch ocfs2-fix-memory-leak-in-ocfs2_mount_volume.patch diff --git a/queue-5.15/soc-sifive-ccache-determine-the-cache-level-from-dts.patch b/queue-5.15/soc-sifive-ccache-determine-the-cache-level-from-dts.patch deleted file mode 100644 index 8c87f53e03f..00000000000 --- a/queue-5.15/soc-sifive-ccache-determine-the-cache-level-from-dts.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 30e750852bcb00d0ec038ae35846966131870d11 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 13 Sep 2022 06:18:13 +0000 -Subject: soc: sifive: ccache: determine the cache level from dts - -From: Zong Li - -[ Upstream commit 95f196f3212bbc258611c22865aef12b98304e1d ] - -Composable cache could be L2 or L3 cache, use 'cache-level' property of -device node to determine the level. - -Signed-off-by: Zong Li -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: 73e770f08502 ("soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()") -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index 949b824e89adf..b361b661ea09a 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -38,6 +38,7 @@ - static void __iomem *ccache_base; - static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; - static struct riscv_cacheinfo_ops ccache_cache_ops; -+static int level; - - enum { - DIR_CORR = 0, -@@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo - *this_leaf) - { - /* We want to use private group for composable cache only */ -- if (this_leaf->level == 2) -+ if (this_leaf->level == level) - return &priv_attr_group; - else - return NULL; -@@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) - if (!ccache_base) - return -ENOMEM; - -+ if (of_property_read_u32(np, "cache-level", &level)) -+ return -ENOENT; -+ - intr_num = of_property_count_u32_elems(np, "interrupts"); - if (!intr_num) { - pr_err("CCACHE: no interrupts property\n"); --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-fix-missing-free_irq-in-error-path.patch b/queue-5.15/soc-sifive-ccache-fix-missing-free_irq-in-error-path.patch deleted file mode 100644 index ff446b4c79e..00000000000 --- a/queue-5.15/soc-sifive-ccache-fix-missing-free_irq-in-error-path.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 42f02719f423d4256dcefc34c23b324bd5b57a0d Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 18 Oct 2022 10:31:48 +0800 -Subject: soc: sifive: ccache: fix missing free_irq() in error path in - sifive_ccache_init() - -From: Yang Yingliang - -[ Upstream commit 756344e7cb1afbb87da8705c20384dddd0dea233 ] - -Add missing free_irq() before return error from sifive_ccache_init(). - -Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") -Signed-off-by: Yang Yingliang -Reviewed-by: Conor Dooley -Signed-off-by: Conor Dooley -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index 335e4303fb928..4b9d0a656a979 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -234,7 +234,7 @@ static int __init sifive_ccache_init(void) - NULL); - if (rc) { - pr_err("Could not request IRQ %d\n", g_irq[i]); -- goto err_unmap; -+ goto err_free_irq; - } - } - -@@ -248,6 +248,9 @@ static int __init sifive_ccache_init(void) - #endif - return 0; - -+err_free_irq: -+ while (--i >= 0) -+ free_irq(g_irq[i], NULL); - err_unmap: - iounmap(ccache_base); - return rc; --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-fix-missing-iounmap-in-error-path-.patch b/queue-5.15/soc-sifive-ccache-fix-missing-iounmap-in-error-path-.patch deleted file mode 100644 index ac48ad3978e..00000000000 --- a/queue-5.15/soc-sifive-ccache-fix-missing-iounmap-in-error-path-.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 5b332dee87d3c4dfea42bd7e78baee82b8b7f571 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 18 Oct 2022 10:31:47 +0800 -Subject: soc: sifive: ccache: fix missing iounmap() in error path in - sifive_ccache_init() - -From: Yang Yingliang - -[ Upstream commit 73e770f085023da327dc9ffeb6cd96b0bb22d97e ] - -Add missing iounmap() before return error from sifive_ccache_init(). - -Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") -Signed-off-by: Yang Yingliang -Reviewed-by: Conor Dooley -Signed-off-by: Conor Dooley -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 15 +++++++++++---- - 1 file changed, 11 insertions(+), 4 deletions(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index 91f0c2b32ea2b..335e4303fb928 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -216,13 +216,16 @@ static int __init sifive_ccache_init(void) - if (!ccache_base) - return -ENOMEM; - -- if (of_property_read_u32(np, "cache-level", &level)) -- return -ENOENT; -+ if (of_property_read_u32(np, "cache-level", &level)) { -+ rc = -ENOENT; -+ goto err_unmap; -+ } - - intr_num = of_property_count_u32_elems(np, "interrupts"); - if (!intr_num) { - pr_err("No interrupts property\n"); -- return -ENODEV; -+ rc = -ENODEV; -+ goto err_unmap; - } - - for (i = 0; i < intr_num; i++) { -@@ -231,7 +234,7 @@ static int __init sifive_ccache_init(void) - NULL); - if (rc) { - pr_err("Could not request IRQ %d\n", g_irq[i]); -- return rc; -+ goto err_unmap; - } - } - -@@ -244,6 +247,10 @@ static int __init sifive_ccache_init(void) - setup_sifive_debug(); - #endif - return 0; -+ -+err_unmap: -+ iounmap(ccache_base); -+ return rc; - } - - device_initcall(sifive_ccache_init); --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-fix-missing-of_node_put-in-sifive_.patch b/queue-5.15/soc-sifive-ccache-fix-missing-of_node_put-in-sifive_.patch deleted file mode 100644 index ded5d536478..00000000000 --- a/queue-5.15/soc-sifive-ccache-fix-missing-of_node_put-in-sifive_.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 248910f3f21104746a7d140474645ed10409b383 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 18 Oct 2022 10:31:49 +0800 -Subject: soc: sifive: ccache: fix missing of_node_put() in - sifive_ccache_init() - -From: Yang Yingliang - -[ Upstream commit 8fbf94fea0b4e187ca9100936c5429f96b8a4e44 ] - -The device_node pointer returned by of_find_matching_node() with -refcount incremented, when finish using it, the refcount need be -decreased. - -Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") -Signed-off-by: Yang Yingliang -Reviewed-by: Conor Dooley -Signed-off-by: Conor Dooley -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 15 +++++++++++---- - 1 file changed, 11 insertions(+), 4 deletions(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index 4b9d0a656a979..09914cb4f0284 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -209,12 +209,16 @@ static int __init sifive_ccache_init(void) - if (!np) - return -ENODEV; - -- if (of_address_to_resource(np, 0, &res)) -- return -ENODEV; -+ if (of_address_to_resource(np, 0, &res)) { -+ rc = -ENODEV; -+ goto err_node_put; -+ } - - ccache_base = ioremap(res.start, resource_size(&res)); -- if (!ccache_base) -- return -ENOMEM; -+ if (!ccache_base) { -+ rc = -ENOMEM; -+ goto err_node_put; -+ } - - if (of_property_read_u32(np, "cache-level", &level)) { - rc = -ENOENT; -@@ -237,6 +241,7 @@ static int __init sifive_ccache_init(void) - goto err_free_irq; - } - } -+ of_node_put(np); - - ccache_config_read(); - -@@ -253,6 +258,8 @@ static int __init sifive_ccache_init(void) - free_irq(g_irq[i], NULL); - err_unmap: - iounmap(ccache_base); -+err_node_put: -+ of_node_put(np); - return rc; - } - --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-reduce-printing-on-init.patch b/queue-5.15/soc-sifive-ccache-reduce-printing-on-init.patch deleted file mode 100644 index e86a469b682..00000000000 --- a/queue-5.15/soc-sifive-ccache-reduce-printing-on-init.patch +++ /dev/null @@ -1,66 +0,0 @@ -From bf335099c9ba5205a878d54645790175661333d6 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 13 Sep 2022 06:18:14 +0000 -Subject: soc: sifive: ccache: reduce printing on init - -From: Ben Dooks - -[ Upstream commit 3fb787e5bad50687a65ded7f3bb805cab70dff59 ] - -The driver prints out 6 lines on startup, which can easily be redcued -to two lines without losing any information. - -Note, to make the types work better, uint64_t has been replaced with -ULL to make the unsigned long long match the format in the print -statement. - -Signed-off-by: Ben Dooks -Signed-off-by: Zong Li -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: 73e770f08502 ("soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()") -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- - 1 file changed, 11 insertions(+), 14 deletions(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index b361b661ea09a..17080af7dfa00 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -81,20 +81,17 @@ static void setup_sifive_debug(void) - - static void ccache_config_read(void) - { -- u32 regval, val; -- -- regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); -- val = regval & 0xFF; -- pr_info("CCACHE: No. of Banks in the cache: %d\n", val); -- val = (regval & 0xFF00) >> 8; -- pr_info("CCACHE: No. of ways per bank: %d\n", val); -- val = (regval & 0xFF0000) >> 16; -- pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); -- val = (regval & 0xFF000000) >> 24; -- pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); -- -- regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); -- pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); -+ u32 cfg; -+ -+ cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); -+ -+ pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", -+ (cfg & 0xff), (cfg >> 8) & 0xff, -+ BIT_ULL((cfg >> 16) & 0xff), -+ BIT_ULL((cfg >> 24) & 0xff)); -+ -+ cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); -+ pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); - } - - static const struct of_device_id sifive_ccache_ids[] = { --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-rename-sifive-l2-cache-to-composab.patch b/queue-5.15/soc-sifive-ccache-rename-sifive-l2-cache-to-composab.patch deleted file mode 100644 index e3d9dec7951..00000000000 --- a/queue-5.15/soc-sifive-ccache-rename-sifive-l2-cache-to-composab.patch +++ /dev/null @@ -1,673 +0,0 @@ -From 6f46e25b6cf3540adb412957ed3ee02d8be7bbff Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 13 Sep 2022 06:18:12 +0000 -Subject: soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. - -From: Greentime Hu - -[ Upstream commit ca120a79cf5a3323172c82e77efd70ae10d120ef ] - -Since composable cache may be L3 cache if there is a L2 cache, we should -use its original name composable cache to prevent confusion. - -There are some new lines were generated due to adding the compatible -"sifive,ccache0" into ID table and indent requirement. - -The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to -apply the change as well. - -Signed-off-by: Greentime Hu -Signed-off-by: Zong Li -Co-developed-by: Zong Li -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: 73e770f08502 ("soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()") -Signed-off-by: Sasha Levin ---- - drivers/edac/Kconfig | 2 +- - drivers/edac/sifive_edac.c | 12 +- - drivers/soc/sifive/Kconfig | 6 +- - drivers/soc/sifive/Makefile | 2 +- - drivers/soc/sifive/sifive_ccache.c | 245 +++++++++++++++++++++++++++ - drivers/soc/sifive/sifive_l2_cache.c | 237 -------------------------- - include/soc/sifive/sifive_ccache.h | 16 ++ - include/soc/sifive/sifive_l2_cache.h | 16 -- - 8 files changed, 272 insertions(+), 264 deletions(-) - create mode 100644 drivers/soc/sifive/sifive_ccache.c - delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c - create mode 100644 include/soc/sifive/sifive_ccache.h - delete mode 100644 include/soc/sifive/sifive_l2_cache.h - -diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig -index 2fc4c3f91fd54..0e1ed09ec5b72 100644 ---- a/drivers/edac/Kconfig -+++ b/drivers/edac/Kconfig -@@ -471,7 +471,7 @@ config EDAC_ALTERA_SDMMC - - config EDAC_SIFIVE - bool "Sifive platform EDAC driver" -- depends on EDAC=y && SIFIVE_L2 -+ depends on EDAC=y && SIFIVE_CCACHE - help - Support for error detection and correction on the SiFive SoCs. - -diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c -index 3a3dcb14ed99d..a759a56ad34de 100644 ---- a/drivers/edac/sifive_edac.c -+++ b/drivers/edac/sifive_edac.c -@@ -2,7 +2,7 @@ - /* - * SiFive Platform EDAC Driver - * -- * Copyright (C) 2018-2019 SiFive, Inc. -+ * Copyright (C) 2018-2022 SiFive, Inc. - * - * This driver is partially based on octeon_edac-pc.c - * -@@ -10,7 +10,7 @@ - #include - #include - #include "edac_module.h" --#include -+#include - - #define DRVNAME "sifive_edac" - -@@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) - - p = container_of(this, struct sifive_edac_priv, notifier); - -- if (event == SIFIVE_L2_ERR_TYPE_UE) -+ if (event == SIFIVE_CCACHE_ERR_TYPE_UE) - edac_device_handle_ue(p->dci, 0, 0, msg); -- else if (event == SIFIVE_L2_ERR_TYPE_CE) -+ else if (event == SIFIVE_CCACHE_ERR_TYPE_CE) - edac_device_handle_ce(p->dci, 0, 0, msg); - - return NOTIFY_OK; -@@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) - goto err; - } - -- register_sifive_l2_error_notifier(&p->notifier); -+ register_sifive_ccache_error_notifier(&p->notifier); - - return 0; - -@@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) - { - struct sifive_edac_priv *p = platform_get_drvdata(pdev); - -- unregister_sifive_l2_error_notifier(&p->notifier); -+ unregister_sifive_ccache_error_notifier(&p->notifier); - edac_device_del_device(&pdev->dev); - edac_device_free_ctl_info(p->dci); - -diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig -index 58cf8c40d08d5..ed4c571f8771b 100644 ---- a/drivers/soc/sifive/Kconfig -+++ b/drivers/soc/sifive/Kconfig -@@ -2,9 +2,9 @@ - - if SOC_SIFIVE - --config SIFIVE_L2 -- bool "Sifive L2 Cache controller" -+config SIFIVE_CCACHE -+ bool "Sifive Composable Cache controller" - help -- Support for the L2 cache controller on SiFive platforms. -+ Support for the composable cache controller on SiFive platforms. - - endif -diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile -index b5caff77938f6..1f5dc339bf827 100644 ---- a/drivers/soc/sifive/Makefile -+++ b/drivers/soc/sifive/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - --obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o -+obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -new file mode 100644 -index 0000000000000..949b824e89adf ---- /dev/null -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -0,0 +1,245 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * SiFive composable cache controller Driver -+ * -+ * Copyright (C) 2018-2022 SiFive, Inc. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 -+#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 -+#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 -+ -+#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 -+#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 -+#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 -+ -+#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 -+#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 -+#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 -+ -+#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 -+#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 -+#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 -+ -+#define SIFIVE_CCACHE_CONFIG 0x00 -+#define SIFIVE_CCACHE_WAYENABLE 0x08 -+#define SIFIVE_CCACHE_ECCINJECTERR 0x40 -+ -+#define SIFIVE_CCACHE_MAX_ECCINTR 4 -+ -+static void __iomem *ccache_base; -+static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; -+static struct riscv_cacheinfo_ops ccache_cache_ops; -+ -+enum { -+ DIR_CORR = 0, -+ DATA_CORR, -+ DATA_UNCORR, -+ DIR_UNCORR, -+}; -+ -+#ifdef CONFIG_DEBUG_FS -+static struct dentry *sifive_test; -+ -+static ssize_t ccache_write(struct file *file, const char __user *data, -+ size_t count, loff_t *ppos) -+{ -+ unsigned int val; -+ -+ if (kstrtouint_from_user(data, count, 0, &val)) -+ return -EINVAL; -+ if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) -+ writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); -+ else -+ return -EINVAL; -+ return count; -+} -+ -+static const struct file_operations ccache_fops = { -+ .owner = THIS_MODULE, -+ .open = simple_open, -+ .write = ccache_write -+}; -+ -+static void setup_sifive_debug(void) -+{ -+ sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); -+ -+ debugfs_create_file("sifive_debug_inject_error", 0200, -+ sifive_test, NULL, &ccache_fops); -+} -+#endif -+ -+static void ccache_config_read(void) -+{ -+ u32 regval, val; -+ -+ regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); -+ val = regval & 0xFF; -+ pr_info("CCACHE: No. of Banks in the cache: %d\n", val); -+ val = (regval & 0xFF00) >> 8; -+ pr_info("CCACHE: No. of ways per bank: %d\n", val); -+ val = (regval & 0xFF0000) >> 16; -+ pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); -+ val = (regval & 0xFF000000) >> 24; -+ pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); -+ -+ regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); -+ pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); -+} -+ -+static const struct of_device_id sifive_ccache_ids[] = { -+ { .compatible = "sifive,fu540-c000-ccache" }, -+ { .compatible = "sifive,fu740-c000-ccache" }, -+ { .compatible = "sifive,ccache0" }, -+ { /* end of table */ } -+}; -+ -+static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); -+ -+int register_sifive_ccache_error_notifier(struct notifier_block *nb) -+{ -+ return atomic_notifier_chain_register(&ccache_err_chain, nb); -+} -+EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); -+ -+int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) -+{ -+ return atomic_notifier_chain_unregister(&ccache_err_chain, nb); -+} -+EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); -+ -+static int ccache_largest_wayenabled(void) -+{ -+ return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; -+} -+ -+static ssize_t number_of_ways_enabled_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ return sprintf(buf, "%u\n", ccache_largest_wayenabled()); -+} -+ -+static DEVICE_ATTR_RO(number_of_ways_enabled); -+ -+static struct attribute *priv_attrs[] = { -+ &dev_attr_number_of_ways_enabled.attr, -+ NULL, -+}; -+ -+static const struct attribute_group priv_attr_group = { -+ .attrs = priv_attrs, -+}; -+ -+static const struct attribute_group *ccache_get_priv_group(struct cacheinfo -+ *this_leaf) -+{ -+ /* We want to use private group for composable cache only */ -+ if (this_leaf->level == 2) -+ return &priv_attr_group; -+ else -+ return NULL; -+} -+ -+static irqreturn_t ccache_int_handler(int irq, void *device) -+{ -+ unsigned int add_h, add_l; -+ -+ if (irq == g_irq[DIR_CORR]) { -+ add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); -+ add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); -+ pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); -+ /* Reading this register clears the DirError interrupt sig */ -+ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); -+ atomic_notifier_call_chain(&ccache_err_chain, -+ SIFIVE_CCACHE_ERR_TYPE_CE, -+ "DirECCFix"); -+ } -+ if (irq == g_irq[DIR_UNCORR]) { -+ add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); -+ add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); -+ /* Reading this register clears the DirFail interrupt sig */ -+ readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); -+ atomic_notifier_call_chain(&ccache_err_chain, -+ SIFIVE_CCACHE_ERR_TYPE_UE, -+ "DirECCFail"); -+ panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); -+ } -+ if (irq == g_irq[DATA_CORR]) { -+ add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); -+ add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); -+ pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); -+ /* Reading this register clears the DataError interrupt sig */ -+ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); -+ atomic_notifier_call_chain(&ccache_err_chain, -+ SIFIVE_CCACHE_ERR_TYPE_CE, -+ "DatECCFix"); -+ } -+ if (irq == g_irq[DATA_UNCORR]) { -+ add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); -+ add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); -+ pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); -+ /* Reading this register clears the DataFail interrupt sig */ -+ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); -+ atomic_notifier_call_chain(&ccache_err_chain, -+ SIFIVE_CCACHE_ERR_TYPE_UE, -+ "DatECCFail"); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int __init sifive_ccache_init(void) -+{ -+ struct device_node *np; -+ struct resource res; -+ int i, rc, intr_num; -+ -+ np = of_find_matching_node(NULL, sifive_ccache_ids); -+ if (!np) -+ return -ENODEV; -+ -+ if (of_address_to_resource(np, 0, &res)) -+ return -ENODEV; -+ -+ ccache_base = ioremap(res.start, resource_size(&res)); -+ if (!ccache_base) -+ return -ENOMEM; -+ -+ intr_num = of_property_count_u32_elems(np, "interrupts"); -+ if (!intr_num) { -+ pr_err("CCACHE: no interrupts property\n"); -+ return -ENODEV; -+ } -+ -+ for (i = 0; i < intr_num; i++) { -+ g_irq[i] = irq_of_parse_and_map(np, i); -+ rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", -+ NULL); -+ if (rc) { -+ pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); -+ return rc; -+ } -+ } -+ -+ ccache_config_read(); -+ -+ ccache_cache_ops.get_priv_group = ccache_get_priv_group; -+ riscv_set_cacheinfo_ops(&ccache_cache_ops); -+ -+#ifdef CONFIG_DEBUG_FS -+ setup_sifive_debug(); -+#endif -+ return 0; -+} -+ -+device_initcall(sifive_ccache_init); -diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c -deleted file mode 100644 -index 59640a1d0b28a..0000000000000 ---- a/drivers/soc/sifive/sifive_l2_cache.c -+++ /dev/null -@@ -1,237 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --/* -- * SiFive L2 cache controller Driver -- * -- * Copyright (C) 2018-2019 SiFive, Inc. -- * -- */ --#include --#include --#include --#include --#include --#include --#include -- --#define SIFIVE_L2_DIRECCFIX_LOW 0x100 --#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 --#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 -- --#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 --#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 --#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 -- --#define SIFIVE_L2_DATECCFIX_LOW 0x140 --#define SIFIVE_L2_DATECCFIX_HIGH 0x144 --#define SIFIVE_L2_DATECCFIX_COUNT 0x148 -- --#define SIFIVE_L2_DATECCFAIL_LOW 0x160 --#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 --#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 -- --#define SIFIVE_L2_CONFIG 0x00 --#define SIFIVE_L2_WAYENABLE 0x08 --#define SIFIVE_L2_ECCINJECTERR 0x40 -- --#define SIFIVE_L2_MAX_ECCINTR 4 -- --static void __iomem *l2_base; --static int g_irq[SIFIVE_L2_MAX_ECCINTR]; --static struct riscv_cacheinfo_ops l2_cache_ops; -- --enum { -- DIR_CORR = 0, -- DATA_CORR, -- DATA_UNCORR, -- DIR_UNCORR, --}; -- --#ifdef CONFIG_DEBUG_FS --static struct dentry *sifive_test; -- --static ssize_t l2_write(struct file *file, const char __user *data, -- size_t count, loff_t *ppos) --{ -- unsigned int val; -- -- if (kstrtouint_from_user(data, count, 0, &val)) -- return -EINVAL; -- if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) -- writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); -- else -- return -EINVAL; -- return count; --} -- --static const struct file_operations l2_fops = { -- .owner = THIS_MODULE, -- .open = simple_open, -- .write = l2_write --}; -- --static void setup_sifive_debug(void) --{ -- sifive_test = debugfs_create_dir("sifive_l2_cache", NULL); -- -- debugfs_create_file("sifive_debug_inject_error", 0200, -- sifive_test, NULL, &l2_fops); --} --#endif -- --static void l2_config_read(void) --{ -- u32 regval, val; -- -- regval = readl(l2_base + SIFIVE_L2_CONFIG); -- val = regval & 0xFF; -- pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); -- val = (regval & 0xFF00) >> 8; -- pr_info("L2CACHE: No. of ways per bank: %d\n", val); -- val = (regval & 0xFF0000) >> 16; -- pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); -- val = (regval & 0xFF000000) >> 24; -- pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); -- -- regval = readl(l2_base + SIFIVE_L2_WAYENABLE); -- pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); --} -- --static const struct of_device_id sifive_l2_ids[] = { -- { .compatible = "sifive,fu540-c000-ccache" }, -- { .compatible = "sifive,fu740-c000-ccache" }, -- { /* end of table */ }, --}; -- --static ATOMIC_NOTIFIER_HEAD(l2_err_chain); -- --int register_sifive_l2_error_notifier(struct notifier_block *nb) --{ -- return atomic_notifier_chain_register(&l2_err_chain, nb); --} --EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); -- --int unregister_sifive_l2_error_notifier(struct notifier_block *nb) --{ -- return atomic_notifier_chain_unregister(&l2_err_chain, nb); --} --EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); -- --static int l2_largest_wayenabled(void) --{ -- return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; --} -- --static ssize_t number_of_ways_enabled_show(struct device *dev, -- struct device_attribute *attr, -- char *buf) --{ -- return sprintf(buf, "%u\n", l2_largest_wayenabled()); --} -- --static DEVICE_ATTR_RO(number_of_ways_enabled); -- --static struct attribute *priv_attrs[] = { -- &dev_attr_number_of_ways_enabled.attr, -- NULL, --}; -- --static const struct attribute_group priv_attr_group = { -- .attrs = priv_attrs, --}; -- --static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) --{ -- /* We want to use private group for L2 cache only */ -- if (this_leaf->level == 2) -- return &priv_attr_group; -- else -- return NULL; --} -- --static irqreturn_t l2_int_handler(int irq, void *device) --{ -- unsigned int add_h, add_l; -- -- if (irq == g_irq[DIR_CORR]) { -- add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); -- add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); -- pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); -- /* Reading this register clears the DirError interrupt sig */ -- readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); -- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, -- "DirECCFix"); -- } -- if (irq == g_irq[DIR_UNCORR]) { -- add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); -- add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); -- /* Reading this register clears the DirFail interrupt sig */ -- readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); -- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, -- "DirECCFail"); -- panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); -- } -- if (irq == g_irq[DATA_CORR]) { -- add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); -- add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); -- pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); -- /* Reading this register clears the DataError interrupt sig */ -- readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); -- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, -- "DatECCFix"); -- } -- if (irq == g_irq[DATA_UNCORR]) { -- add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); -- add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); -- pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); -- /* Reading this register clears the DataFail interrupt sig */ -- readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); -- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, -- "DatECCFail"); -- } -- -- return IRQ_HANDLED; --} -- --static int __init sifive_l2_init(void) --{ -- struct device_node *np; -- struct resource res; -- int i, rc, intr_num; -- -- np = of_find_matching_node(NULL, sifive_l2_ids); -- if (!np) -- return -ENODEV; -- -- if (of_address_to_resource(np, 0, &res)) -- return -ENODEV; -- -- l2_base = ioremap(res.start, resource_size(&res)); -- if (!l2_base) -- return -ENOMEM; -- -- intr_num = of_property_count_u32_elems(np, "interrupts"); -- if (!intr_num) { -- pr_err("L2CACHE: no interrupts property\n"); -- return -ENODEV; -- } -- -- for (i = 0; i < intr_num; i++) { -- g_irq[i] = irq_of_parse_and_map(np, i); -- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); -- if (rc) { -- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); -- return rc; -- } -- } -- -- l2_config_read(); -- -- l2_cache_ops.get_priv_group = l2_get_priv_group; -- riscv_set_cacheinfo_ops(&l2_cache_ops); -- --#ifdef CONFIG_DEBUG_FS -- setup_sifive_debug(); --#endif -- return 0; --} --device_initcall(sifive_l2_init); -diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h -new file mode 100644 -index 0000000000000..4d4ed49388a0a ---- /dev/null -+++ b/include/soc/sifive/sifive_ccache.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * SiFive Composable Cache Controller header file -+ * -+ */ -+ -+#ifndef __SOC_SIFIVE_CCACHE_H -+#define __SOC_SIFIVE_CCACHE_H -+ -+extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); -+extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); -+ -+#define SIFIVE_CCACHE_ERR_TYPE_CE 0 -+#define SIFIVE_CCACHE_ERR_TYPE_UE 1 -+ -+#endif /* __SOC_SIFIVE_CCACHE_H */ -diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h -deleted file mode 100644 -index 92ade10ed67e9..0000000000000 ---- a/include/soc/sifive/sifive_l2_cache.h -+++ /dev/null -@@ -1,16 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* -- * SiFive L2 Cache Controller header file -- * -- */ -- --#ifndef __SOC_SIFIVE_L2_CACHE_H --#define __SOC_SIFIVE_L2_CACHE_H -- --extern int register_sifive_l2_error_notifier(struct notifier_block *nb); --extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); -- --#define SIFIVE_L2_ERR_TYPE_CE 0 --#define SIFIVE_L2_ERR_TYPE_UE 1 -- --#endif /* __SOC_SIFIVE_L2_CACHE_H */ --- -2.39.2 - diff --git a/queue-5.15/soc-sifive-ccache-use-pr_fmt-to-remove-ccache-prefix.patch b/queue-5.15/soc-sifive-ccache-use-pr_fmt-to-remove-ccache-prefix.patch deleted file mode 100644 index bc519a926ce..00000000000 --- a/queue-5.15/soc-sifive-ccache-use-pr_fmt-to-remove-ccache-prefix.patch +++ /dev/null @@ -1,102 +0,0 @@ -From a4eaebec7992c50b11bfa97a7976cf7e92bdc913 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 13 Sep 2022 06:18:15 +0000 -Subject: soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes - -From: Ben Dooks - -[ Upstream commit 696ab9bda22a770d079dc3a23bac9aaa553d98f4 ] - -Use the pr_fmt() macro to prefix all the output with "CCACHE:" -to avoid having to write it out each time, or make a large diff -when the next change comes along. - -Signed-off-by: Ben Dooks -Signed-off-by: Zong Li -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: 73e770f08502 ("soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()") -Signed-off-by: Sasha Levin ---- - drivers/soc/sifive/sifive_ccache.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - -diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c -index 17080af7dfa00..91f0c2b32ea2b 100644 ---- a/drivers/soc/sifive/sifive_ccache.c -+++ b/drivers/soc/sifive/sifive_ccache.c -@@ -5,6 +5,9 @@ - * Copyright (C) 2018-2022 SiFive, Inc. - * - */ -+ -+#define pr_fmt(fmt) "CCACHE: " fmt -+ - #include - #include - #include -@@ -85,13 +88,13 @@ static void ccache_config_read(void) - - cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - -- pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", -+ pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", - (cfg & 0xff), (cfg >> 8) & 0xff, - BIT_ULL((cfg >> 16) & 0xff), - BIT_ULL((cfg >> 24) & 0xff)); - - cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); -- pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); -+ pr_info("Index of the largest way enabled: %u\n", cfg); - } - - static const struct of_device_id sifive_ccache_ids[] = { -@@ -155,7 +158,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) - if (irq == g_irq[DIR_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); -- pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); -+ pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DirError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, -@@ -175,7 +178,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) - if (irq == g_irq[DATA_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); -- pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); -+ pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, -@@ -185,7 +188,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) - if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); -- pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); -+ pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataFail interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, -@@ -218,7 +221,7 @@ static int __init sifive_ccache_init(void) - - intr_num = of_property_count_u32_elems(np, "interrupts"); - if (!intr_num) { -- pr_err("CCACHE: no interrupts property\n"); -+ pr_err("No interrupts property\n"); - return -ENODEV; - } - -@@ -227,7 +230,7 @@ static int __init sifive_ccache_init(void) - rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", - NULL); - if (rc) { -- pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); -+ pr_err("Could not request IRQ %d\n", g_irq[i]); - return rc; - } - } --- -2.39.2 -