From: David S. Miller Date: Tue, 11 Oct 2011 18:35:26 +0000 (+0000) Subject: Fix regcache_restore() handling of unavailable regs. X-Git-Tag: sid-snapshot-20111101~208 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=349d138559111de9e0ee57120e267005ac27cb6e;p=thirdparty%2Fbinutils-gdb.git Fix regcache_restore() handling of unavailable regs. * regcache.c (regcache_restore): Do not write unavailable regs, mark static. * regcache.h (regcache_restore): Remove declaration. --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ccd0530e976..e871fb17fd4 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,9 @@ +2011-10-11 David S. Miller + + * regcache.c (regcache_restore): Do not write unavailable regs, mark + static. + * regcache.h (regcache_restore): Remove declaration. + 2011-10-11 Jan Kratochvil Revert this part of: diff --git a/gdb/regcache.c b/gdb/regcache.c index 37092f82551..ea8189e67db 100644 --- a/gdb/regcache.c +++ b/gdb/regcache.c @@ -331,7 +331,7 @@ regcache_save (struct regcache *dst, regcache_cooked_read_ftype *cooked_read, } } -void +static void regcache_restore (struct regcache *dst, regcache_cooked_read_ftype *cooked_read, void *cooked_read_context) @@ -351,9 +351,10 @@ regcache_restore (struct regcache *dst, { if (gdbarch_register_reggroup_p (gdbarch, regnum, restore_reggroup)) { - int valid = cooked_read (cooked_read_context, regnum, buf); + enum register_status status; - if (valid) + status = cooked_read (cooked_read_context, regnum, buf); + if (status == REG_VALID) regcache_cooked_write (dst, regnum, buf); } } diff --git a/gdb/regcache.h b/gdb/regcache.h index 5531f398cae..440fbe60947 100644 --- a/gdb/regcache.h +++ b/gdb/regcache.h @@ -174,9 +174,6 @@ typedef enum register_status (regcache_cooked_read_ftype) (void *src, extern void regcache_save (struct regcache *dst, regcache_cooked_read_ftype *cooked_read, void *cooked_read_context); -extern void regcache_restore (struct regcache *dst, - regcache_cooked_read_ftype *cooked_read, - void *cooked_read_context); /* Copy/duplicate the contents of a register cache. By default, the operation is pass-through. Writes to DST and reads from SRC will