From: Nelson Chu Date: Wed, 9 Jul 2025 04:53:40 +0000 (+0800) Subject: RISC-V: Clarify the imply rule of c X-Git-Tag: binutils-2_45~107 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=34fcc16e79b402e820f75ff376f0c8c5a185878f;p=thirdparty%2Fbinutils-gdb.git RISC-V: Clarify the imply rule of c This also fix the imply result for .option rvc. Imply zcf when c and f and rv32 Imply zcd when c and d Imply zca when c Changed INSN_CLASS_C to INSN_CLASS_ZCA Changed INSN_CLASS_F_AND_C to INSN_CLASS_ZCF Changed INSN_CLASS_D_AND_C to INSN_CLASS_ZCD Changed INSN_CLASS_ZIHINTNTL_AND_C to INSN_CLASS_ZIHINTNTL_AND_ZCA --- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 776bfd5cea0..bdec17c7d1c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1178,9 +1178,20 @@ static bool check_implicit_for_zcf (riscv_parse_subset_t *rps, const riscv_subset_t *subset ATTRIBUTE_UNUSED) { - riscv_subset_t *tmp = NULL; - return *rps->xlen == 32 - && riscv_lookup_subset (rps->subset_list, "f", &tmp); + return (rps != NULL + && rps->xlen != NULL + && *rps->xlen == 32 + && riscv_subset_supports (rps, "f")); +} + +/* Add the implicit only when 'd' extension is also available. */ + +static bool +check_implicit_for_zcd (riscv_parse_subset_t *rps, + const riscv_subset_t *subset ATTRIBUTE_UNUSED) +{ + return (rps != NULL + && riscv_subset_supports (rps, "d")); } /* Record all implicit information for the subsets. */ @@ -1275,6 +1286,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zfinx", "+zicsr", check_implicit_always}, {"f", "+zicsr", check_implicit_always}, + {"c", "+zcf", check_implicit_for_zcf}, + {"c", "+zcd", check_implicit_for_zcd}, + {"c", "+zca", check_implicit_always}, + {"b", "+zba,+zbb,+zbs", check_implicit_always}, {"zk", "+zkn,+zkr,+zkt", check_implicit_always}, @@ -2208,7 +2223,7 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) && riscv_subset_supports (rps, "zcd")) { rps->error_handler - (_("zcmp' is incompatible with `d/zcd' extension")); + (_("zcmp' is incompatible with `d' and `c', or `zcd' extension")); no_conflict = false; } if (riscv_lookup_subset (rps->subset_list, "zcf", &subset) @@ -2795,10 +2810,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zifencei"); case INSN_CLASS_ZIHINTNTL: return riscv_subset_supports (rps, "zihintntl"); - case INSN_CLASS_ZIHINTNTL_AND_C: - return (riscv_subset_supports (rps, "zihintntl") - && (riscv_subset_supports (rps, "c") - || riscv_subset_supports (rps, "zca"))); + case INSN_CLASS_ZIHINTNTL_AND_ZCA: + return riscv_subset_supports (rps, "zihintntl") + && riscv_subset_supports (rps, "zca"); case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports (rps, "zihintpause"); case INSN_CLASS_ZIMOP: @@ -2833,17 +2847,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "d"); case INSN_CLASS_Q: return riscv_subset_supports (rps, "q"); - case INSN_CLASS_C: - return (riscv_subset_supports (rps, "c") - || riscv_subset_supports (rps, "zca")); - case INSN_CLASS_F_AND_C: - return (riscv_subset_supports (rps, "f") - && (riscv_subset_supports (rps, "c") - || riscv_subset_supports (rps, "zcf"))); - case INSN_CLASS_D_AND_C: - return (riscv_subset_supports (rps, "d") - && (riscv_subset_supports (rps, "c") - || riscv_subset_supports (rps, "zcd"))); + case INSN_CLASS_ZCA: + return riscv_subset_supports (rps, "zca"); + case INSN_CLASS_ZCF: + return riscv_subset_supports (rps, "zcf"); + case INSN_CLASS_ZCD: + return riscv_subset_supports (rps, "zcd"); case INSN_CLASS_F_INX: return (riscv_subset_supports (rps, "f") || riscv_subset_supports (rps, "zfinx")); @@ -3090,11 +3099,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zicfilp"; case INSN_CLASS_ZIHINTNTL: return "zihintntl"; - case INSN_CLASS_ZIHINTNTL_AND_C: + case INSN_CLASS_ZIHINTNTL_AND_ZCA: if (!riscv_subset_supports (rps, "zihintntl")) { - if (!riscv_subset_supports (rps, "c") - && !riscv_subset_supports (rps, "zca")) + if (!riscv_subset_supports (rps, "zca")) return _("zihintntl' and `c', or `zihintntl' and `zca"); else return "zihintntl"; @@ -3125,30 +3133,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "d"; case INSN_CLASS_Q: return "q"; - case INSN_CLASS_C: + case INSN_CLASS_ZCA: return _("c' or `zca"); - case INSN_CLASS_F_AND_C: - if (!riscv_subset_supports (rps, "f")) - { - if (!riscv_subset_supports (rps, "c") - && !riscv_subset_supports (rps, "zcf")) - return _("f' and `c', or `f' and `zcf"); - else - return "f"; - } - else - return _("c' or `zcf"); - case INSN_CLASS_D_AND_C: - if (!riscv_subset_supports (rps, "d")) - { - if (!riscv_subset_supports (rps, "c") - && !riscv_subset_supports (rps, "zcd")) - return _("d' and `c', or `d' and `zcd"); - else - return "d"; - } - else - return _("c' or `zcd"); + case INSN_CLASS_ZCF: + return _("f' and `c', or `zcf"); + case INSN_CLASS_ZCD: + return _("d' and `c', or `zcd"); case INSN_CLASS_F_INX: return _("f' or `zfinx"); case INSN_CLASS_D_INX: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 1791b882567..ea4be32a8ff 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -199,9 +199,11 @@ command-line options are respected for the bulk of the file being assembled. @item rvc @itemx norvc -Enables or disables the generation of compressed instructions. Instructions -are opportunistically compressed by the RISC-V assembler when possible, but -sometimes this behavior is not desirable, especially when handling alignments. +Enable the generation of base compressed instructions (C extension), or +disable the generation of all compressed instructions (C and all Zc* +extensions). Instructions are opportunistically compressed by the RISC-V +assembler when possible, but sometimes this behavior is not desirable, +especially when handling alignments. @item pic @itemx nopic diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d index 04c322ab1dd..cb3ae5a897f 100644 --- a/gas/testsuite/gas/riscv/attribute-10.d +++ b/gas/testsuite/gas/riscv/attribute-10.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" + Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0" diff --git a/gas/testsuite/gas/riscv/attribute-17.d b/gas/testsuite/gas/riscv/attribute-17.d index 8e87e8e6995..f431b0441e4 100644 --- a/gas/testsuite/gas/riscv/attribute-17.d +++ b/gas/testsuite/gas/riscv/attribute-17.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0" + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0" diff --git a/gas/testsuite/gas/riscv/attribute-19.d b/gas/testsuite/gas/riscv/attribute-19.d index d73e3f00ed8..b9b5a4028ba 100644 --- a/gas/testsuite/gas/riscv/attribute-19.d +++ b/gas/testsuite/gas/riscv/attribute-19.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" diff --git a/gas/testsuite/gas/riscv/attribute-20.d b/gas/testsuite/gas/riscv/attribute-20.d index 22bcc13f207..7fbfda03be0 100644 --- a/gas/testsuite/gas/riscv/attribute-20.d +++ b/gas/testsuite/gas/riscv/attribute-20.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_supm1p0" + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_supm1p0" diff --git a/gas/testsuite/gas/riscv/attribute-rva23s.d b/gas/testsuite/gas/riscv/attribute-rva23s.d index 54e79aa28f2..b38b7b9f0a9 100644 --- a/gas/testsuite/gas/riscv/attribute-rva23s.d +++ b/gas/testsuite/gas/riscv/attribute-rva23s.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" diff --git a/gas/testsuite/gas/riscv/attribute-rvb23s.d b/gas/testsuite/gas/riscv/attribute-rvb23s.d index 5cee65afde9..87e243cab2c 100644 --- a/gas/testsuite/gas/riscv/attribute-rvb23s.d +++ b/gas/testsuite/gas/riscv/attribute-rvb23s.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d index b68da92b07c..b3b83b0af96 100644 --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -73,6 +73,11 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0 +[0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0 +[0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_c2p0_zca1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0 diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s index 35c68d3efbb..eba215d84a4 100644 --- a/gas/testsuite/gas/riscv/imply.s +++ b/gas/testsuite/gas/riscv/imply.s @@ -1,6 +1,6 @@ -.macro imply string base=i +.macro imply string base=i xlen=32 .option push -.option arch, rv32\base\string +.option arch, rv\xlen\base\string nop .option pop .endm @@ -85,6 +85,12 @@ imply zfhmin imply zfinx imply f +imply c,if,32 +imply c,if,64 +imply c,id,32 +imply c,id,64 +imply c + imply b imply zk diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d index ab1d4700e5f..ddc150274ad 100644 --- a/gas/testsuite/gas/riscv/mapping-symbols.d +++ b/gas/testsuite/gas/riscv/mapping-symbols.d @@ -9,43 +9,43 @@ SYMBOL TABLE: 0+00 l d .data 0+00 .data 0+00 l d .bss 0+00 .bss 0+00 l d .text.cross.section.A 0+00 .text.cross.section.A -0+00 l .text.cross.section.A 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.cross.section.A 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .text.cross.section.B 0+00 .text.cross.section.B -0+00 l .text.cross.section.B 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.cross.section.B 0+00 \$xrv32i2p1_c2p0_zca1p0 0+02 l .text.cross.section.B 0+00 \$xrv32i2p1 0+00 l d .text.data 0+00 .text.data 0+00 l .text.data 0+00 \$d -0+08 l .text.data 0+00 \$xrv32i2p1_c2p0 +0+08 l .text.data 0+00 \$xrv32i2p1_c2p0_zca1p0 0+0c l .text.data 0+00 \$d 0+00 l d .text.odd.align.start.insn 0+00 .text.odd.align.start.insn -0+00 l .text.odd.align.start.insn 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.odd.align.start.insn 0+00 \$xrv32i2p1_c2p0_zca1p0 0+02 l .text.odd.align.start.insn 0+00 \$d 0+00 l d .text.odd.align.start.data 0+00 .text.odd.align.start.data 0+00 l .text.odd.align.start.data 0+00 \$d 0+00 l d .text.zero.fill.first 0+00 .text.zero.fill.first -0+00 l .text.zero.fill.first 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.first 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .text.zero.fill.last 0+00 .text.zero.fill.last -0+00 l .text.zero.fill.last 0+00 \$xrv32i2p1_c2p0 -0+02 l .text.zero.fill.last 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.last 0+00 \$xrv32i2p1_c2p0_zca1p0 +0+02 l .text.zero.fill.last 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .text.zero.fill.align.A 0+00 .text.zero.fill.align.A -0+00 l .text.zero.fill.align.A 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.zero.fill.align.A 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .text.zero.fill.align.B 0+00 .text.zero.fill.align.B 0+00 l .text.zero.fill.align.B 0+00 \$xrv32i2p1 0+00 l d .text.last.section 0+00 .text.last.section 0+00 l .text.last.section 0+00 \$xrv32i2p1 0+04 l .text.last.section 0+00 \$d 0+00 l d .text.section.padding 0+00 .text.section.padding -0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0 -0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0 +0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0_zca1p0 +0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0_zca1p0 0+06 l .text.section.padding 0+00 \$d 0+00 l d .text.relax.align 0+00 .text.relax.align -0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 +0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0_zca1p0 0+08 l .text.relax.align 0+00 \$xrv32i2p1 -0+0a l .text.section.padding 0+00 \$xrv32i2p1_c2p0 +0+0a l .text.section.padding 0+00 \$xrv32i2p1_c2p0_zca1p0 0+03 l .text.odd.align.start.insn 0+00 \$d 0+04 l .text.odd.align.start.insn 0+00 \$xrv32i2p1 0+01 l .text.odd.align.start.data 0+00 \$d -0+02 l .text.odd.align.start.data 0+00 \$xrv32i2p1_c2p0 +0+02 l .text.odd.align.start.data 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .riscv.attributes 0+00 .riscv.attributes 0+00 g .text.cross.section.A 0+00 funcA 0+00 g .text.cross.section.B 0+00 funcB diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d b/gas/testsuite/gas/riscv/march-ok-reorder.d index 712c1bdff4d..883d6a2e1cd 100644 --- a/gas/testsuite/gas/riscv/march-ok-reorder.d +++ b/gas/testsuite/gas/riscv/march-ok-reorder.d @@ -4,4 +4,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zba1p0_xbar2p0_xfoo2p0" + Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_xbar2p0_xfoo2p0" diff --git a/gas/testsuite/gas/riscv/option-arch-attr.d b/gas/testsuite/gas/riscv/option-arch-attr.d index 8c1f6658796..27df69dc176 100644 --- a/gas/testsuite/gas/riscv/option-arch-attr.d +++ b/gas/testsuite/gas/riscv/option-arch-attr.d @@ -4,4 +4,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p0_c2p0" + Tag_RISCV_arch: "rv64i2p0_c2p0_zca1p0" diff --git a/gas/testsuite/gas/riscv/option-arch-dis.d b/gas/testsuite/gas/riscv/option-arch-dis.d index e4b603b83c6..bee01f1abd8 100644 --- a/gas/testsuite/gas/riscv/option-arch-dis.d +++ b/gas/testsuite/gas/riscv/option-arch-dis.d @@ -8,10 +8,10 @@ SYMBOL TABLE: 0+00 l d .text 0+00 .text 0+00 l d .data 0+00 .data 0+00 l d .bss 0+00 .bss -0+00 l .text 0+00 \$xrv64i2p0_c2p0 +0+00 l .text 0+00 \$xrv64i2p0_c2p0_zca1p0 0+02 l .text 0+00 \$xrv64i2p0_f2p0_d2p0_xvendor1p0 -0+0a l .text 0+00 \$xrv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0 -0+0c l .text 0+00 \$xrv32i2p1_c2p0 +0+0a l .text 0+00 \$xrv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_zca1p0_zcd1p0_xvendor32x3p0 +0+0c l .text 0+00 \$xrv32i2p1_c2p0_zca1p0 0+00 l d .riscv.attributes 0+00 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/option-norvc.d b/gas/testsuite/gas/riscv/option-norvc.d index 6f36ed6c085..5a4b97688a7 100644 --- a/gas/testsuite/gas/riscv/option-norvc.d +++ b/gas/testsuite/gas/riscv/option-norvc.d @@ -8,11 +8,11 @@ SYMBOL TABLE: 0+00 l d .text 0+00 .text 0+00 l d .data 0+00 .data 0+00 l d .bss 0+00 .bss -0+00 l .text 0+00 \$xrv64i2p0_c2p0 +0+00 l .text 0+00 \$xrv64i2p0_c2p0_zca1p0 0+02 l .text 0+00 \$xrv64i2p0 -0+06 l .text 0+00 \$xrv32i2p0_f2p0_c2p0 +0+06 l .text 0+00 \$xrv32i2p0_f2p0_c2p0_zca1p0_zcf1p0 0+08 l .text 0+00 \$xrv32i2p0_f2p0 -0+0c l .text 0+00 \$xrv64i2p0_f2p0_d2p0_c2p0 +0+0c l .text 0+00 \$xrv64i2p0_f2p0_d2p0_c2p0_zca1p0_zcd1p0 0+0e l .text 0+00 \$xrv64i2p0_f2p0_d2p0 0+12 l .text 0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0 0+14 l .text 0+00 \$xrv64i2p0_f2p0_d2p0 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2b146afd868..858fcce6871 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -493,18 +493,18 @@ enum riscv_insn_class INSN_CLASS_NONE, INSN_CLASS_I, - INSN_CLASS_C, + INSN_CLASS_ZCA, INSN_CLASS_M, INSN_CLASS_F, INSN_CLASS_D, INSN_CLASS_Q, - INSN_CLASS_F_AND_C, - INSN_CLASS_D_AND_C, + INSN_CLASS_ZCF, + INSN_CLASS_ZCD, INSN_CLASS_ZICOND, INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTNTL, - INSN_CLASS_ZIHINTNTL_AND_C, + INSN_CLASS_ZIHINTNTL_AND_ZCA, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZIMOP, INSN_CLASS_ZMMUL, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index f17d284ca6d..56ef62a622f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -464,34 +464,34 @@ const struct riscv_opcode riscv_opcodes[] = {"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, {"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, {"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, -{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, INSN_ALIAS }, +{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, INSN_ALIAS }, {"ntl.p1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_P1, MASK_NTL_P1, match_opcode, 0 }, -{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, INSN_ALIAS }, +{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, INSN_ALIAS }, {"ntl.pall", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_PALL, MASK_NTL_PALL, match_opcode, 0 }, -{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, INSN_ALIAS }, +{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, INSN_ALIAS }, {"ntl.s1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_S1, MASK_NTL_S1, match_opcode, 0 }, -{"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, INSN_ALIAS }, +{"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, INSN_ALIAS }, {"ntl.all", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_ALL, MASK_NTL_ALL, match_opcode, 0 }, -{"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, 0 }, -{"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, 0 }, -{"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 }, -{"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 }, +{"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, 0 }, +{"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, 0 }, +{"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 }, +{"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_ZCA, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 }, {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, /* Basic RVI instructions and aliases. */ -{"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, +{"unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ -{"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"ebreak", 0, INSN_CLASS_ZCA, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, {"ebreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, -{"sbreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"sbreak", 0, INSN_CLASS_ZCA, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, {"sbreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, -{"ret", 0, INSN_CLASS_C, "", MATCH_C_JR|(X_RA << OP_SH_RD), MASK_C_JR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"ret", 0, INSN_CLASS_ZCA, "", MATCH_C_JR|(X_RA << OP_SH_RD), MASK_C_JR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"ret", 0, INSN_CLASS_I, "", MATCH_JALR|(X_RA << OP_SH_RS1), MASK_JALR|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, -{"jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH }, +{"jr", 0, INSN_CLASS_ZCA, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH }, {"jr", 0, INSN_CLASS_I, "s", MATCH_JALR, MASK_JALR|MASK_RD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"jr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR, MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"jr", 0, INSN_CLASS_I, "s,j", MATCH_JALR, MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, -{"jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR }, +{"jalr", 0, INSN_CLASS_ZCA, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "s", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, @@ -499,9 +499,9 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, -{"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"j", 0, INSN_CLASS_ZCA, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, -{"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, +{"jal", 32, INSN_CLASS_ZCA, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, {"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, @@ -509,31 +509,31 @@ const struct riscv_opcode riscv_opcodes[] = {"tail", 0, INSN_CLASS_ZICFILP, "c", (X_T2 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, {"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_rs1_nonzero, INSN_MACRO }, -{"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"nop", 0, INSN_CLASS_ZCA, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, {"nop", 0, INSN_CLASS_I, "", MATCH_ADDI, MASK_ADDI|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, -{"lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"lui", 0, INSN_CLASS_ZCA, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, {"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, -{"li", 0, INSN_CLASS_C, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, -{"li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{"li", 0, INSN_CLASS_ZCA, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"li", 0, INSN_CLASS_ZCA, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, {"li", 0, INSN_CLASS_I, "d,j", MATCH_ADDI, MASK_ADDI|MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ {"li", 0, INSN_CLASS_I, "d,I", 0, (int) M_LI, NULL, INSN_MACRO }, -{"mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"mv", 0, INSN_CLASS_ZCA, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, -{"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"move", 0, INSN_CLASS_ZCA, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, {"zext.b", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, {"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS }, {"andi", 0, INSN_CLASS_ZCB, "Cs,Cw,Wcf",MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, -{"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"andi", 0, INSN_CLASS_ZCA, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, {"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, -{"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, -{"and", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, -{"and", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"and", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", 0, INSN_CLASS_ZCA, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", 0, INSN_CLASS_ZCA, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, {"and", 0, INSN_CLASS_I, "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, {"and", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, -{"beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"beqz", 0, INSN_CLASS_ZCA, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beqz", 0, INSN_CLASS_I, "s,p", MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, -{"beq", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"beq", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beq", 0, INSN_CLASS_I, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH }, {"blez", 0, INSN_CLASS_I, "t,p", MATCH_BGE, MASK_BGE|MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgez", 0, INSN_CLASS_I, "s,p", MATCH_BGE, MASK_BGE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, @@ -547,23 +547,23 @@ const struct riscv_opcode riscv_opcodes[] = {"bltu", 0, INSN_CLASS_I, "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_CONDBRANCH }, {"bgt", 0, INSN_CLASS_I, "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgtu", 0, INSN_CLASS_I, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, -{"bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"bnez", 0, INSN_CLASS_ZCA, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bnez", 0, INSN_CLASS_I, "s,p", MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, -{"bne", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"bne", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bne", 0, INSN_CLASS_I, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH }, -{"addi", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, -{"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, -{"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, -{"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, -{"addi", 0, INSN_CLASS_C, "d,CV,z", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_ZCA, "d,CV,z", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, -{"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, -{"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, -{"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, -{"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, -{"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"add", 0, INSN_CLASS_ZCA, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", 0, INSN_CLASS_I, "d,s,t,1", MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, @@ -577,22 +577,22 @@ const struct riscv_opcode riscv_opcodes[] = {"mips.ehb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_EHB, MASK_MIPS_EHB, match_opcode, 0 }, {"mips.ihb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_IHB, MASK_MIPS_IHB, match_opcode, 0 }, {"mips.pause", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE, match_opcode, 0 }, -{"slli", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, +{"slli", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, {"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, -{"sll", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, +{"sll", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, {"sll", 0, INSN_CLASS_I, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, {"sll", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, -{"srli", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, +{"srli", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srli", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, -{"srl", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, +{"srl", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srl", 0, INSN_CLASS_I, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, {"srl", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, -{"srai", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, +{"srai", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srai", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, -{"sra", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, +{"sra", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, {"sra", 0, INSN_CLASS_I, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, {"sra", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, -{"sub", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, +{"sub", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, {"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, {"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE }, {"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, @@ -605,16 +605,16 @@ const struct riscv_opcode riscv_opcodes[] = {"lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE }, {"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, {"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, -{"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"lw", 0, INSN_CLASS_ZCA, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"lw", 0, INSN_CLASS_ZCA, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, {"not", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_NOT, MASK_C_NOT, match_opcode, INSN_ALIAS }, {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, -{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, -{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", 0, INSN_CLASS_ZCA, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, /* Zicfilp instructions. */ @@ -639,8 +639,8 @@ const struct riscv_opcode riscv_opcodes[] = {"sh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE|INSN_ALIAS }, {"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, {"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, -{"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"sw", 0, INSN_CLASS_ZCA, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"sw", 0, INSN_CLASS_ZCA, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, @@ -657,34 +657,34 @@ const struct riscv_opcode riscv_opcodes[] = {"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, {"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, -{"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, -{"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", 0, INSN_CLASS_ZCA, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, {"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE }, {"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, -{"ld", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"ld", 64, INSN_CLASS_ZCA, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"ld", 64, INSN_CLASS_ZCA, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"ld", 64, INSN_CLASS_I, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, {"ld", 32, INSN_CLASS_ZCLSD, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_even_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"ld", 32, INSN_CLASS_ZCLSD, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_crs2s_even, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"ld", 32, INSN_CLASS_ZILSD, "d,o(s)", MATCH_LD, MASK_LD, match_rd_even, INSN_DREF|INSN_8_BYTE }, {"ld", 32, INSN_CLASS_ZILSD, "d,A", 0, (int) M_Lx, match_rd_even_nonzero, INSN_MACRO }, -{"sd", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"sd", 64, INSN_CLASS_ZCA, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"sd", 64, INSN_CLASS_ZCA, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, {"sd", 32, INSN_CLASS_ZCLSD, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_crs2_even, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"sd", 32, INSN_CLASS_ZCLSD, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_crs2s_even, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"sd", 32, INSN_CLASS_ZILSD, "t,q(s)", MATCH_SD, MASK_SD, match_rs2_even, INSN_DREF|INSN_8_BYTE }, {"sd", 32, INSN_CLASS_ZILSD, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero_rs2_even, INSN_MACRO }, -{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{"sext.w", 64, INSN_CLASS_ZCA, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, {"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS }, -{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addiw", 64, INSN_CLASS_ZCA, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, {"addiw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, -{"addw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, -{"addw", 64, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, -{"addw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addw", 64, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", 64, INSN_CLASS_ZCA, "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", 64, INSN_CLASS_ZCA, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, {"addw", 64, INSN_CLASS_I, "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, {"addw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, {"negw", 64, INSN_CLASS_I, "d,t", MATCH_SUBW, MASK_SUBW|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ @@ -697,7 +697,7 @@ const struct riscv_opcode riscv_opcodes[] = {"sraiw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, {"sraw", 64, INSN_CLASS_I, "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, {"sraw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, -{"subw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, +{"subw", 64, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, /* Atomic memory operation instruction subset. */ @@ -993,12 +993,12 @@ const struct riscv_opcode riscv_opcodes[] = {"fsflags", 0, INSN_CLASS_F_INX, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, {"fsflagsi", 0, INSN_CLASS_F_INX, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, {"fsflagsi", 0, INSN_CLASS_F_INX, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, -{"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"flw", 32, INSN_CLASS_ZCF, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"flw", 32, INSN_CLASS_ZCF, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, -{"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"fsw", 32, INSN_CLASS_ZCF, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"fsw", 32, INSN_CLASS_ZCF, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, {"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, @@ -1055,12 +1055,12 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, /* Double-precision floating-point instruction subset. */ -{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fld", 0, INSN_CLASS_ZCD, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fld", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, -{"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fsd", 0, INSN_CLASS_ZCD, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fsd", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, {"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, @@ -1174,57 +1174,57 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ -{"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -{"c.ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, -{"c.jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH }, -{"c.jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR }, -{"c.j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH }, -{"c.jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR }, -{"c.beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH }, -{"c.bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH }, -{"c.lwsp", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, -{"c.lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.swsp", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, -{"c.nop", 0, INSN_CLASS_C, "Cj", MATCH_C_ADDI, MASK_C_ADDI|MASK_RD, match_opcode, INSN_ALIAS }, -{"c.mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 }, -{"c.lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 }, -{"c.li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 }, -{"c.addi4spn", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, -{"c.addi16sp", 0, INSN_CLASS_C, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, -{"c.addi", 0, INSN_CLASS_C, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, -{"c.add", 0, INSN_CLASS_C, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 }, -{"c.sub", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, -{"c.and", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, -{"c.or", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, -{"c.xor", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, -{"c.slli", 0, INSN_CLASS_C, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 }, -{"c.srli", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 }, -{"c.srai", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 }, -{"c.slli64", 0, INSN_CLASS_C, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 }, -{"c.srli64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 }, -{"c.srai64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 }, -{"c.andi", 0, INSN_CLASS_C, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, -{"c.addiw", 64, INSN_CLASS_C, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, -{"c.addw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, -{"c.subw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, +{"c.unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, 0 }, +{"c.ebreak", 0, INSN_CLASS_ZCA, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, +{"c.jr", 0, INSN_CLASS_ZCA, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH }, +{"c.jalr", 0, INSN_CLASS_ZCA, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR }, +{"c.j", 0, INSN_CLASS_ZCA, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH }, +{"c.jal", 32, INSN_CLASS_ZCA, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR }, +{"c.beqz", 0, INSN_CLASS_ZCA, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH }, +{"c.bnez", 0, INSN_CLASS_ZCA, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH }, +{"c.lwsp", 0, INSN_CLASS_ZCA, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, +{"c.lw", 0, INSN_CLASS_ZCA, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.swsp", 0, INSN_CLASS_ZCA, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.sw", 0, INSN_CLASS_ZCA, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.nop", 0, INSN_CLASS_ZCA, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"c.nop", 0, INSN_CLASS_ZCA, "Cj", MATCH_C_ADDI, MASK_C_ADDI|MASK_RD, match_opcode, INSN_ALIAS }, +{"c.mv", 0, INSN_CLASS_ZCA, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 }, +{"c.lui", 0, INSN_CLASS_ZCA, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 }, +{"c.li", 0, INSN_CLASS_ZCA, "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 }, +{"c.addi4spn", 0, INSN_CLASS_ZCA, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, +{"c.addi16sp", 0, INSN_CLASS_ZCA, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, +{"c.addi", 0, INSN_CLASS_ZCA, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, +{"c.add", 0, INSN_CLASS_ZCA, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 }, +{"c.sub", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, +{"c.and", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, +{"c.or", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, +{"c.xor", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, +{"c.slli", 0, INSN_CLASS_ZCA, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 }, +{"c.srli", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 }, +{"c.srai", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 }, +{"c.slli64", 0, INSN_CLASS_ZCA, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 }, +{"c.srli64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 }, +{"c.srai64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 }, +{"c.andi", 0, INSN_CLASS_ZCA, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{"c.addiw", 64, INSN_CLASS_ZCA, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{"c.addw", 64, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, +{"c.subw", 64, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, {"c.ldsp", 32, INSN_CLASS_ZCLSD, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_even_nonzero, INSN_DREF|INSN_8_BYTE }, -{"c.ldsp", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE }, +{"c.ldsp", 64, INSN_CLASS_ZCA, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE }, {"c.ld", 32, INSN_CLASS_ZCLSD, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_crs2s_even, INSN_DREF|INSN_8_BYTE }, -{"c.ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.ld", 64, INSN_CLASS_ZCA, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sdsp", 32, INSN_CLASS_ZCLSD, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_crs2_even, INSN_DREF|INSN_8_BYTE }, -{"c.sdsp", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.sdsp", 64, INSN_CLASS_ZCA, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sd", 32, INSN_CLASS_ZCLSD, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_crs2s_even, INSN_DREF|INSN_8_BYTE }, -{"c.sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fldsp", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsdsp", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.flwsp", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.sd", 64, INSN_CLASS_ZCA, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fldsp", 0, INSN_CLASS_ZCD, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fld", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fsdsp", 0, INSN_CLASS_ZCD, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fsd", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.flwsp", 32, INSN_CLASS_ZCF, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.flw", 32, INSN_CLASS_ZCF, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fswsp", 32, INSN_CLASS_ZCF, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fsw", 32, INSN_CLASS_ZCF, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, /* Zicbom and Zicboz instructions. */ {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 }, @@ -3664,39 +3664,39 @@ const struct riscv_opcode riscv_insn_types[] = {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, NULL, 0 }, {"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, NULL, 0 }, -{"cr", 0, INSN_CLASS_C, "O2,CF4,d,CV", 0, 0, NULL, 0 }, -{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CV", 0, 0, NULL, 0 }, -{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,d,CT", 0, 0, NULL, 0 }, -{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CT", 0, 0, NULL, 0 }, +{"cr", 0, INSN_CLASS_ZCA, "O2,CF4,d,CV", 0, 0, NULL, 0 }, +{"cr", 0, INSN_CLASS_ZCF, "O2,CF4,D,CV", 0, 0, NULL, 0 }, +{"cr", 0, INSN_CLASS_ZCF, "O2,CF4,d,CT", 0, 0, NULL, 0 }, +{"cr", 0, INSN_CLASS_ZCF, "O2,CF4,D,CT", 0, 0, NULL, 0 }, -{"ci", 0, INSN_CLASS_C, "O2,CF3,d,Co", 0, 0, NULL, 0 }, -{"ci", 0, INSN_CLASS_F_AND_C, "O2,CF3,D,Co", 0, 0, NULL, 0 }, +{"ci", 0, INSN_CLASS_ZCA, "O2,CF3,d,Co", 0, 0, NULL, 0 }, +{"ci", 0, INSN_CLASS_ZCF, "O2,CF3,D,Co", 0, 0, NULL, 0 }, -{"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, NULL, 0 }, -{"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, NULL, 0 }, +{"ciw", 0, INSN_CLASS_ZCA, "O2,CF3,Ct,C8", 0, 0, NULL, 0 }, +{"ciw", 0, INSN_CLASS_ZCF, "O2,CF3,CD,C8", 0, 0, NULL, 0 }, -{"css", 0, INSN_CLASS_C, "O2,CF3,CV,C6", 0, 0, NULL, 0 }, -{"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, NULL, 0 }, +{"css", 0, INSN_CLASS_ZCA, "O2,CF3,CV,C6", 0, 0, NULL, 0 }, +{"css", 0, INSN_CLASS_ZCF, "O2,CF3,CT,C6", 0, 0, NULL, 0 }, -{"cl", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, NULL, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, NULL, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, NULL, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, NULL, 0 }, +{"cl", 0, INSN_CLASS_ZCA, "O2,CF3,Ct,C5(Cs)", 0, 0, NULL, 0 }, +{"cl", 0, INSN_CLASS_ZCF, "O2,CF3,CD,C5(Cs)", 0, 0, NULL, 0 }, +{"cl", 0, INSN_CLASS_ZCF, "O2,CF3,Ct,C5(CS)", 0, 0, NULL, 0 }, +{"cl", 0, INSN_CLASS_ZCF, "O2,CF3,CD,C5(CS)", 0, 0, NULL, 0 }, -{"cs", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, NULL, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, NULL, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, NULL, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, NULL, 0 }, +{"cs", 0, INSN_CLASS_ZCA, "O2,CF3,Ct,C5(Cs)", 0, 0, NULL, 0 }, +{"cs", 0, INSN_CLASS_ZCF, "O2,CF3,CD,C5(Cs)", 0, 0, NULL, 0 }, +{"cs", 0, INSN_CLASS_ZCF, "O2,CF3,Ct,C5(CS)", 0, 0, NULL, 0 }, +{"cs", 0, INSN_CLASS_ZCF, "O2,CF3,CD,C5(CS)", 0, 0, NULL, 0 }, -{"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, NULL, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, NULL, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, NULL, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,CD", 0, 0, NULL, 0 }, +{"ca", 0, INSN_CLASS_ZCA, "O2,CF6,CF2,Cs,Ct", 0, 0, NULL, 0 }, +{"ca", 0, INSN_CLASS_ZCF, "O2,CF6,CF2,CS,Ct", 0, 0, NULL, 0 }, +{"ca", 0, INSN_CLASS_ZCF, "O2,CF6,CF2,Cs,CD", 0, 0, NULL, 0 }, +{"ca", 0, INSN_CLASS_ZCF, "O2,CF6,CF2,CS,CD", 0, 0, NULL, 0 }, -{"cb", 0, INSN_CLASS_C, "O2,CF3,Cs,Cp", 0, 0, NULL, 0 }, -{"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, NULL, 0 }, +{"cb", 0, INSN_CLASS_ZCA, "O2,CF3,Cs,Cp", 0, 0, NULL, 0 }, +{"cb", 0, INSN_CLASS_ZCF, "O2,CF3,CS,Cp", 0, 0, NULL, 0 }, -{"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, NULL, 0 }, +{"cj", 0, INSN_CLASS_ZCA, "O2,CF3,Ca", 0, 0, NULL, 0 }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}