From: Sasha Levin Date: Sat, 14 Jun 2025 13:34:09 +0000 (-0400) Subject: Fixes for 6.12 X-Git-Tag: v6.6.94~71 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=352c264be2a5c991dd86f71e04c87c8888e9b5f5;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.12 Signed-off-by: Sasha Levin --- diff --git a/queue-6.12/alsa-hda-realtek-add-new-hp-zbook-laptop-with-micmut.patch b/queue-6.12/alsa-hda-realtek-add-new-hp-zbook-laptop-with-micmut.patch new file mode 100644 index 0000000000..f54162a422 --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-add-new-hp-zbook-laptop-with-micmut.patch @@ -0,0 +1,36 @@ +From 273c876cb993b1ad057c0c64eb6d2f3e96933727 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 May 2025 21:21:01 +0800 +Subject: ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup + +From: Chris Chiu + +[ Upstream commit f709b78aecab519dbcefa9a6603b94ad18c553e3 ] + +New HP ZBook with Realtek HDA codec ALC3247 needs the quirk +ALC236_FIXUP_HP_GPIO_LED to fix the micmute LED. + +Signed-off-by: Chris Chiu +Cc: +Link: https://patch.msgid.link/20250520132101.120685-1-chris.chiu@canonical.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index 8532de2fb8a55..a93ca54a913e5 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -10842,6 +10842,7 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8e1a, "HP ZBook Firefly 14 G12A", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), + SND_PCI_QUIRK(0x103c, 0x8e1b, "HP EliteBook G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), + SND_PCI_QUIRK(0x103c, 0x8e1c, "HP EliteBook G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e1d, "HP ZBook X Gli 16 G12", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e2c, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e36, "HP 14 Enstrom OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e37, "HP 16 Piston OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-realtek-add-support-for-hp-agusta-using-cs3.patch b/queue-6.12/alsa-hda-realtek-add-support-for-hp-agusta-using-cs3.patch new file mode 100644 index 0000000000..8a5da63145 --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-add-support-for-hp-agusta-using-cs3.patch @@ -0,0 +1,38 @@ +From 0d596b187c60eb7e66ba60dbc30b1baa83a3aaf1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 May 2025 13:47:43 +0100 +Subject: ALSA: hda/realtek: Add support for HP Agusta using CS35L41 HDA + +From: Stefan Binding + +[ Upstream commit 7150d57c370f9e61b7d0e82c58002f1c5a205ac4 ] + +Add support for HP Agusta. + +Laptops use 2 CS35L41 Amps with HDA, using Internal boost, with I2C + +Signed-off-by: Stefan Binding +Cc: +Link: https://patch.msgid.link/20250520124757.12597-1-sbinding@opensource.cirrus.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index a93ca54a913e5..961d1964de45f 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -10846,6 +10846,8 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8e2c, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e36, "HP 14 Enstrom OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e37, "HP 16 Piston OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e3a, "HP Agusta", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e3b, "HP Agusta", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e60, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e61, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e62, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-realtek-add-support-for-various-hp-laptops-.patch b/queue-6.12/alsa-hda-realtek-add-support-for-various-hp-laptops-.patch new file mode 100644 index 0000000000..1d5df2f770 --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-add-support-for-various-hp-laptops-.patch @@ -0,0 +1,69 @@ +From e4c58b8592ac652742c7fca20021a2e81ab4211a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 21 Mar 2025 23:16:36 +0000 +Subject: ALSA: hda/realtek: Add support for various HP Laptops using CS35L41 + HDA + +From: Stefan Binding + +[ Upstream commit 29951021367f3a6f10e5b7a11c666fc914746f0c ] + +Add support for HP Cadet, Clipper OmniBook, Turbine OmniBook, Trekker, +Enstrom Onmibook, Piston Omnibook + +Laptops use 2 CS35L41 Amps with HDA, using Internal boost, with I2C + +Signed-off-by: Stefan Binding +Link: https://patch.msgid.link/20250321231717.1232792-1-sbinding@opensource.cirrus.com +Signed-off-by: Takashi Iwai +Stable-dep-of: f709b78aecab ("ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup") +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index 4857c554f15b6..7bfab2c5d45ed 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -10791,6 +10791,15 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8d90, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d91, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d92, "HP ZBook Firefly 16 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d9b, "HP 17 Turbine OmniBook 7 UMA", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8d9c, "HP 17 Turbine OmniBook 7 DIS", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8d9d, "HP 17 Turbine OmniBook X UMA", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8d9e, "HP 17 Turbine OmniBook X DIS", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8d9f, "HP 14 Cadet (x360)", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8da0, "HP 16 Clipper OmniBook 7(X360)", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8da1, "HP 16 Clipper OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8da7, "HP 14 Enstrom OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8da8, "HP 16 Piston OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8de8, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), + SND_PCI_QUIRK(0x103c, 0x8de9, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), + SND_PCI_QUIRK(0x103c, 0x8dec, "HP EliteBook 640 G12", ALC236_FIXUP_HP_GPIO_LED), +@@ -10798,6 +10807,9 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8df0, "HP EliteBook 630 G12", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8dfc, "HP EliteBook 645 G12", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8dfe, "HP EliteBook 665 G12", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e11, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e12, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e13, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e14, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e15, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e16, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +@@ -10808,6 +10820,11 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8e1b, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e1c, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e2c, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e36, "HP 14 Enstrom OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e37, "HP 16 Piston OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e60, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e61, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), ++ SND_PCI_QUIRK(0x103c, 0x8e62, "HP Trekker ", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), + SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), + SND_PCI_QUIRK(0x1043, 0x1054, "ASUS G614FH/FM/FP", ALC287_FIXUP_CS35L41_I2C_2), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch b/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch new file mode 100644 index 0000000000..c2b44021a9 --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch @@ -0,0 +1,57 @@ +From eadb964fd400175bc94a1a1203b5d896272b0824 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 21 Mar 2025 18:49:13 +0800 +Subject: ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3315 + +From: Chris Chiu + +[ Upstream commit 0b1b5161648f35fb96967fb9d80965614657a84e ] + +More HP laptops with Realtek HDA codec ALC3315 with combined CS35L56 +Amplifiers need quirk ALC285_FIXUP_HP_GPIO_LED to fix the micmute LED. + +Signed-off-by: Chris Chiu +Reviewed-by: Simon Trimmer +Signed-off-by: Takashi Iwai +Link: https://patch.msgid.link/20250321104914.544233-1-chris.chiu@canonical.com +Stable-dep-of: f709b78aecab ("ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup") +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index 59cc5420e784a..d4bb8d471ea27 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -10782,13 +10782,27 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8cf5, "HP ZBook Studio 16", ALC245_FIXUP_CS35L41_SPI_4_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d01, "HP ZBook Power 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d84, "HP EliteBook X G1i", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d85, "HP EliteBook 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d86, "HP Elite X360 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d8c, "HP EliteBook 13 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d8d, "HP Elite X360 13 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d8e, "HP EliteBook 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d8f, "HP EliteBook 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8d90, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d91, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d92, "HP ZBook Firefly 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8de8, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), + SND_PCI_QUIRK(0x103c, 0x8de9, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), ++ SND_PCI_QUIRK(0x103c, 0x8e14, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e15, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e16, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e17, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e18, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e19, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e1a, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e1b, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e1c, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e2c, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), + SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), + SND_PCI_QUIRK(0x1043, 0x1054, "ASUS G614FH/FM/FP", ALC287_FIXUP_CS35L41_I2C_2), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch-23213 b/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch-23213 new file mode 100644 index 0000000000..08f00efa0e --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch-23213 @@ -0,0 +1,41 @@ +From d9f0ebd85c32c181eae5d53165c474270bea2a1a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 21 Mar 2025 18:49:14 +0800 +Subject: ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3247 + +From: Chris Chiu + +[ Upstream commit 78f4ca3c6f6fd305b9af8c51470643617df85e11 ] + +More HP EliteBook with Realtek HDA codec ALC3247 with combined CS35L56 +Amplifiers need quirk ALC236_FIXUP_HP_GPIO_LED to fix the micmute LED. + +Signed-off-by: Chris Chiu +Reviewed-by: Simon Trimmer +Signed-off-by: Takashi Iwai +Link: https://patch.msgid.link/20250321104914.544233-2-chris.chiu@canonical.com +Stable-dep-of: f709b78aecab ("ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup") +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index d4bb8d471ea27..4857c554f15b6 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -10793,6 +10793,11 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8d92, "HP ZBook Firefly 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8de8, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), + SND_PCI_QUIRK(0x103c, 0x8de9, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), ++ SND_PCI_QUIRK(0x103c, 0x8dec, "HP EliteBook 640 G12", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8dee, "HP EliteBook 660 G12", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8df0, "HP EliteBook 630 G12", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8dfc, "HP EliteBook 645 G12", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8dfe, "HP EliteBook 665 G12", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e14, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e15, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e16, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-realtek-support-mute-led-function-for-hp-pl.patch b/queue-6.12/alsa-hda-realtek-support-mute-led-function-for-hp-pl.patch new file mode 100644 index 0000000000..70b6ba9016 --- /dev/null +++ b/queue-6.12/alsa-hda-realtek-support-mute-led-function-for-hp-pl.patch @@ -0,0 +1,96 @@ +From 215f5ea9d2101117031aa57dece958b9fb3ec59e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Apr 2025 16:50:08 +0800 +Subject: ALSA: hda/realtek - Support mute led function for HP platform + +From: Kailang Yang + +[ Upstream commit 22c7f77247a84d27b785ec5b706f673421ab269d ] + +This patch was integrated CS Amp and support mute led function for HP platform. + +Signed-off-by: Kailang Yang +Link: https://lore.kernel.org/2c960ab58b4d4090ad4ee075f8cfdffd@realtek.com +Signed-off-by: Takashi Iwai +Stable-dep-of: f709b78aecab ("ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup") +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 41 +++++++++++++++++++++++++++-------- + 1 file changed, 32 insertions(+), 9 deletions(-) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index 7bfab2c5d45ed..8532de2fb8a55 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -7621,6 +7621,24 @@ static void alc245_fixup_hp_spectre_x360_16_aa0xxx(struct hda_codec *codec, + alc245_fixup_hp_gpio_led(codec, fix, action); + } + ++static void alc245_fixup_hp_zbook_firefly_g12a(struct hda_codec *codec, ++ const struct hda_fixup *fix, int action) ++{ ++ struct alc_spec *spec = codec->spec; ++ static const hda_nid_t conn[] = { 0x02 }; ++ ++ switch (action) { ++ case HDA_FIXUP_ACT_PRE_PROBE: ++ spec->gen.auto_mute_via_amp = 1; ++ snd_hda_override_conn_list(codec, 0x17, ARRAY_SIZE(conn), conn); ++ break; ++ } ++ ++ cs35l41_fixup_i2c_two(codec, fix, action); ++ alc245_fixup_hp_mute_led_coefbit(codec, fix, action); ++ alc285_fixup_hp_coef_micmute_led(codec, fix, action); ++} ++ + /* + * ALC287 PCM hooks + */ +@@ -7969,6 +7987,7 @@ enum { + ALC256_FIXUP_HEADPHONE_AMP_VOL, + ALC245_FIXUP_HP_SPECTRE_X360_EU0XXX, + ALC245_FIXUP_HP_SPECTRE_X360_16_AA0XXX, ++ ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A, + ALC285_FIXUP_ASUS_GA403U, + ALC285_FIXUP_ASUS_GA403U_HEADSET_MIC, + ALC285_FIXUP_ASUS_GA403U_I2C_SPEAKER2_TO_DAC1, +@@ -10263,6 +10282,10 @@ static const struct hda_fixup alc269_fixups[] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc245_fixup_hp_spectre_x360_16_aa0xxx, + }, ++ [ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A] = { ++ .type = HDA_FIXUP_FUNC, ++ .v.func = alc245_fixup_hp_zbook_firefly_g12a, ++ }, + [ALC285_FIXUP_ASUS_GA403U] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc285_fixup_asus_ga403u, +@@ -10810,15 +10833,15 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8e11, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e12, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e13, "HP Trekker", ALC287_FIXUP_CS35L41_I2C_2), +- SND_PCI_QUIRK(0x103c, 0x8e14, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e15, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e16, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e17, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e18, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e19, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e1a, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e1b, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), +- SND_PCI_QUIRK(0x103c, 0x8e1c, "HP EliteBook G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8e14, "HP ZBook Firefly 14 G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e15, "HP ZBook Firefly 14 G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e16, "HP ZBook Firefly 14 G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e17, "HP ZBook Firefly 14 G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e18, "HP ZBook Firefly 14 G12A", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e19, "HP ZBook Firefly 14 G12A", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e1a, "HP ZBook Firefly 14 G12A", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e1b, "HP EliteBook G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), ++ SND_PCI_QUIRK(0x103c, 0x8e1c, "HP EliteBook G12", ALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A), + SND_PCI_QUIRK(0x103c, 0x8e2c, "HP EliteBook 16 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e36, "HP 14 Enstrom OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), + SND_PCI_QUIRK(0x103c, 0x8e37, "HP 16 Piston OmniBook X", ALC287_FIXUP_CS35L41_I2C_2), +-- +2.39.5 + diff --git a/queue-6.12/alsa-hda-tas2781-add-tas2781-hda-spi-driver.patch b/queue-6.12/alsa-hda-tas2781-add-tas2781-hda-spi-driver.patch new file mode 100644 index 0000000000..028a57fe24 --- /dev/null +++ b/queue-6.12/alsa-hda-tas2781-add-tas2781-hda-spi-driver.patch @@ -0,0 +1,3643 @@ +From 6e133f320e9bbbf856ad25b2eb6c174eaa87e78f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Dec 2024 20:20:08 +0800 +Subject: ALSA: hda/tas2781: Add tas2781 hda SPI driver + +From: Baojun Xu + +[ Upstream commit bb5f86ea50ffb292f42eb1ebdb99991d5c5ac3ba ] + +This patch was used to add TAS2781 devices on SPI support in sound/pci/hda. +It use ACPI node descript about parameters of TAS2781 on SPI, it like: + Scope (_SB.PC00.SPI0) + { + Device (GSPK) + { + Name (_HID, "TXNW2781") // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + SpiSerialBusV2 (...) + SpiSerialBusV2 (...) + } + } + } + } + +And in platform/x86/serial-multi-instantiate.c, those spi devices will be +added into system as a single SPI device, so TAS2781 SPI driver will +probe twice for every single SPI device. And driver will also parser +mono DSP firmware binary and RCA binary for itself. +The code support Realtek as the primary codec. +In patch version-10, add multi devices firmware binary support, +to compatble with windows driver, they can share same firmware binary. + +Signed-off-by: Baojun Xu +Link: https://patch.msgid.link/20241216122008.15425-1-baojun.xu@ti.com +Signed-off-by: Takashi Iwai +Stable-dep-of: f709b78aecab ("ALSA: hda/realtek - Add new HP ZBook laptop with micmute led fixup") +Signed-off-by: Sasha Levin +--- + drivers/acpi/scan.c | 1 + + .../platform/x86/serial-multi-instantiate.c | 12 + + sound/pci/hda/Kconfig | 14 + + sound/pci/hda/Makefile | 2 + + sound/pci/hda/patch_realtek.c | 14 + + sound/pci/hda/tas2781-spi.h | 158 ++ + sound/pci/hda/tas2781_hda_spi.c | 1271 +++++++++++ + sound/pci/hda/tas2781_spi_fwlib.c | 2006 +++++++++++++++++ + 8 files changed, 3478 insertions(+) + create mode 100644 sound/pci/hda/tas2781-spi.h + create mode 100644 sound/pci/hda/tas2781_hda_spi.c + create mode 100644 sound/pci/hda/tas2781_spi_fwlib.c + +diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c +index 7ecc401fb97f9..21119f13e92a1 100644 +--- a/drivers/acpi/scan.c ++++ b/drivers/acpi/scan.c +@@ -1769,6 +1769,7 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device) + {"CSC3557", }, + {"INT33FE", }, + {"INT3515", }, ++ {"TXNW2781", }, + /* Non-conforming _HID for Cirrus Logic already released */ + {"CLSA0100", }, + {"CLSA0101", }, +diff --git a/drivers/platform/x86/serial-multi-instantiate.c b/drivers/platform/x86/serial-multi-instantiate.c +index 7c04cc9e5891b..20a8421a1edf3 100644 +--- a/drivers/platform/x86/serial-multi-instantiate.c ++++ b/drivers/platform/x86/serial-multi-instantiate.c +@@ -384,6 +384,17 @@ static const struct smi_node cs35l57_hda = { + .bus_type = SMI_AUTO_DETECT, + }; + ++static const struct smi_node tas2781_hda = { ++ .instances = { ++ { "tas2781-hda", IRQ_RESOURCE_AUTO, 0 }, ++ { "tas2781-hda", IRQ_RESOURCE_AUTO, 0 }, ++ { "tas2781-hda", IRQ_RESOURCE_AUTO, 0 }, ++ { "tas2781-hda", IRQ_RESOURCE_AUTO, 0 }, ++ {} ++ }, ++ .bus_type = SMI_AUTO_DETECT, ++}; ++ + /* + * Note new device-ids must also be added to ignore_serial_bus_ids in + * drivers/acpi/scan.c: acpi_device_enumeration_by_parent(). +@@ -396,6 +407,7 @@ static const struct acpi_device_id smi_acpi_ids[] = { + { "CSC3556", (unsigned long)&cs35l56_hda }, + { "CSC3557", (unsigned long)&cs35l57_hda }, + { "INT3515", (unsigned long)&int3515_data }, ++ { "TXNW2781", (unsigned long)&tas2781_hda }, + /* Non-conforming _HID for Cirrus Logic already released */ + { "CLSA0100", (unsigned long)&cs35l41_hda }, + { "CLSA0101", (unsigned long)&cs35l41_hda }, +diff --git a/sound/pci/hda/Kconfig b/sound/pci/hda/Kconfig +index fd9391e61b3d9..49ab7e48d8024 100644 +--- a/sound/pci/hda/Kconfig ++++ b/sound/pci/hda/Kconfig +@@ -204,6 +204,20 @@ config SND_HDA_SCODEC_TAS2781_I2C + comment "Set to Y if you want auto-loading the side codec driver" + depends on SND_HDA=y && SND_HDA_SCODEC_TAS2781_I2C=m + ++config SND_HDA_SCODEC_TAS2781_SPI ++ tristate "Build TAS2781 HD-audio side codec support for SPI Bus" ++ depends on SPI_MASTER ++ depends on ACPI ++ depends on EFI ++ depends on SND_SOC ++ select CRC32_SARWATE ++ help ++ Say Y or M here to include TAS2781 SPI HD-audio side codec support ++ in snd-hda-intel driver, such as ALC287. ++ ++comment "Set to Y if you want auto-loading the side codec driver" ++ depends on SND_HDA=y && SND_HDA_SCODEC_TAS2781_SPI=m ++ + config SND_HDA_CODEC_REALTEK + tristate "Build Realtek HD-audio codec support" + depends on INPUT +diff --git a/sound/pci/hda/Makefile b/sound/pci/hda/Makefile +index 80210f845df21..210c406dfbc50 100644 +--- a/sound/pci/hda/Makefile ++++ b/sound/pci/hda/Makefile +@@ -40,6 +40,7 @@ snd-hda-scodec-cs35l56-spi-y := cs35l56_hda_spi.o + snd-hda-cs-dsp-ctls-y := hda_cs_dsp_ctl.o + snd-hda-scodec-component-y := hda_component.o + snd-hda-scodec-tas2781-i2c-y := tas2781_hda_i2c.o ++snd-hda-scodec-tas2781-spi-y := tas2781_hda_spi.o tas2781_spi_fwlib.o + + # common driver + obj-$(CONFIG_SND_HDA) := snd-hda-codec.o +@@ -72,6 +73,7 @@ obj-$(CONFIG_SND_HDA_SCODEC_CS35L56_SPI) += snd-hda-scodec-cs35l56-spi.o + obj-$(CONFIG_SND_HDA_CS_DSP_CONTROLS) += snd-hda-cs-dsp-ctls.o + obj-$(CONFIG_SND_HDA_SCODEC_COMPONENT) += snd-hda-scodec-component.o + obj-$(CONFIG_SND_HDA_SCODEC_TAS2781_I2C) += snd-hda-scodec-tas2781-i2c.o ++obj-$(CONFIG_SND_HDA_SCODEC_TAS2781_SPI) += snd-hda-scodec-tas2781-spi.o + + # this must be the last entry after codec drivers; + # otherwise the codec patches won't be hooked before the PCI probe +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index dce5680912006..59cc5420e784a 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -7303,6 +7303,11 @@ static void tas2781_fixup_i2c(struct hda_codec *cdc, + comp_generic_fixup(cdc, action, "i2c", "TIAS2781", "-%s:00", 1); + } + ++static void tas2781_fixup_spi(struct hda_codec *cdc, const struct hda_fixup *fix, int action) ++{ ++ comp_generic_fixup(cdc, action, "spi", "TXNW2781", "-%s:00-tas2781-hda.%d", 2); ++} ++ + static void yoga7_14arb7_fixup_i2c(struct hda_codec *cdc, + const struct hda_fixup *fix, int action) + { +@@ -7950,6 +7955,7 @@ enum { + ALC236_FIXUP_DELL_DUAL_CODECS, + ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI, + ALC287_FIXUP_TAS2781_I2C, ++ ALC245_FIXUP_TAS2781_SPI_2, + ALC287_FIXUP_YOGA7_14ARB7_I2C, + ALC245_FIXUP_HP_MUTE_LED_COEFBIT, + ALC245_FIXUP_HP_MUTE_LED_V1_COEFBIT, +@@ -10189,6 +10195,12 @@ static const struct hda_fixup alc269_fixups[] = { + .chained = true, + .chain_id = ALC285_FIXUP_THINKPAD_HEADSET_JACK, + }, ++ [ALC245_FIXUP_TAS2781_SPI_2] = { ++ .type = HDA_FIXUP_FUNC, ++ .v.func = tas2781_fixup_spi, ++ .chained = true, ++ .chain_id = ALC285_FIXUP_HP_GPIO_LED, ++ }, + [ALC287_FIXUP_YOGA7_14ARB7_I2C] = { + .type = HDA_FIXUP_FUNC, + .v.func = yoga7_14arb7_fixup_i2c, +@@ -10772,6 +10784,8 @@ static const struct hda_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8d84, "HP EliteBook X G1i", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d91, "HP ZBook Firefly 14 G12", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8d92, "HP ZBook Firefly 16 G12", ALC285_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8de8, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), ++ SND_PCI_QUIRK(0x103c, 0x8de9, "HP Gemtree", ALC245_FIXUP_TAS2781_SPI_2), + SND_PCI_QUIRK(0x103c, 0x8e18, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e19, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x103c, 0x8e1a, "HP ZBook Firefly 14 G12A", ALC285_FIXUP_HP_GPIO_LED), +diff --git a/sound/pci/hda/tas2781-spi.h b/sound/pci/hda/tas2781-spi.h +new file mode 100644 +index 0000000000000..ecfc3c8bb8214 +--- /dev/null ++++ b/sound/pci/hda/tas2781-spi.h +@@ -0,0 +1,158 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++// ++// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier ++// ++// Copyright (C) 2024 Texas Instruments Incorporated ++// https://www.ti.com ++// ++// The TAS2781 driver implements a flexible and configurable ++// algo coefficient setting for TAS2781 chips. ++// ++// Author: Baojun Xu ++// ++ ++#ifndef __TAS2781_SPI_H__ ++#define __TAS2781_SPI_H__ ++ ++#define TASDEVICE_RATES \ ++ (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ ++ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200) ++ ++#define TASDEVICE_FORMATS \ ++ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ ++#define TASDEVICE_MAX_BOOK_NUM 256 ++#define TASDEVICE_MAX_PAGE 256 ++ ++#define TASDEVICE_MAX_SIZE (TASDEVICE_MAX_BOOK_NUM * TASDEVICE_MAX_PAGE) ++ ++/* PAGE Control Register (available in page0 of each book) */ ++#define TASDEVICE_PAGE_SELECT 0x00 ++#define TASDEVICE_BOOKCTL_PAGE 0x00 ++#define TASDEVICE_BOOKCTL_REG GENMASK(7, 1) ++#define TASDEVICE_BOOK_ID(reg) (((reg) & GENMASK(24, 16)) >> 16) ++#define TASDEVICE_PAGE_ID(reg) (((reg) & GENMASK(15, 8)) >> 8) ++#define TASDEVICE_REG_ID(reg) (((reg) & GENMASK(7, 1)) >> 1) ++#define TASDEVICE_PAGE_REG(reg) ((reg) & GENMASK(15, 1)) ++#define TASDEVICE_REG(book, page, reg) \ ++ (((book) << 16) | ((page) << 8) | ((reg) << 1)) ++ ++/* Software Reset */ ++#define TAS2781_REG_SWRESET TASDEVICE_REG(0x0, 0x0, 0x01) ++#define TAS2781_REG_SWRESET_RESET BIT(0) ++ ++/* System Reset Check Register */ ++#define TAS2781_REG_CLK_CONFIG TASDEVICE_REG(0x0, 0x0, 0x5c) ++#define TAS2781_REG_CLK_CONFIG_RESET (0x19) ++#define TAS2781_PRE_POST_RESET_CFG 3 ++ ++/* Block Checksum */ ++#define TASDEVICE_CHECKSUM TASDEVICE_REG(0x0, 0x0, 0x7e) ++ ++/* Volume control */ ++#define TAS2781_DVC_LVL TASDEVICE_REG(0x0, 0x0, 0x1a) ++#define TAS2781_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x03) ++#define TAS2781_AMP_LEVEL_MASK GENMASK(5, 1) ++ ++#define TASDEVICE_CMD_SING_W 0x1 ++#define TASDEVICE_CMD_BURST 0x2 ++#define TASDEVICE_CMD_DELAY 0x3 ++#define TASDEVICE_CMD_FIELD_W 0x4 ++ ++#define TAS2781_SPI_MAX_FREQ (4 * HZ_PER_MHZ) ++ ++#define TASDEVICE_CRC8_POLYNOMIAL 0x4d ++#define TASDEVICE_SPEAKER_CALIBRATION_SIZE 20 ++ ++/* Flag of calibration registers address. */ ++#define TASDEVICE_CALIBRATION_REG_ADDRESS BIT(7) ++ ++#define TASDEVICE_CALIBRATION_DATA_NAME L"CALI_DATA" ++#define TASDEVICE_CALIBRATION_DATA_SIZE 256 ++ ++enum calib_data { ++ R0_VAL = 0, ++ INV_R0, ++ R0LOW, ++ POWER, ++ TLIM, ++ CALIB_MAX ++}; ++ ++struct tasdevice_priv { ++ struct tasdevice_fw *cali_data_fmw; ++ struct tasdevice_rca rcabin; ++ struct tasdevice_fw *fmw; ++ struct gpio_desc *reset; ++ struct mutex codec_lock; ++ struct regmap *regmap; ++ struct device *dev; ++ struct tm tm; ++ ++ unsigned char crc8_lkp_tbl[CRC8_TABLE_SIZE]; ++ unsigned char coef_binaryname[64]; ++ unsigned char rca_binaryname[64]; ++ unsigned char dev_name[32]; ++ ++ bool force_fwload_status; ++ bool playback_started; ++ bool is_loading; ++ bool is_loaderr; ++ unsigned int cali_reg_array[CALIB_MAX]; ++ unsigned int cali_data[CALIB_MAX]; ++ unsigned int err_code; ++ void *codec; ++ int cur_book; ++ int cur_prog; ++ int cur_conf; ++ int fw_state; ++ int index; ++ int irq; ++ ++ int (*fw_parse_variable_header)(struct tasdevice_priv *tas_priv, ++ const struct firmware *fmw, ++ int offset); ++ int (*fw_parse_program_data)(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, ++ const struct firmware *fmw, int offset); ++ int (*fw_parse_configuration_data)(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, ++ const struct firmware *fmw, ++ int offset); ++ int (*tasdevice_load_block)(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block); ++ ++ int (*save_calibration)(struct tasdevice_priv *tas_priv); ++ void (*apply_calibration)(struct tasdevice_priv *tas_priv); ++}; ++ ++int tasdevice_spi_dev_read(struct tasdevice_priv *tas_priv, ++ unsigned int reg, unsigned int *value); ++int tasdevice_spi_dev_write(struct tasdevice_priv *tas_priv, ++ unsigned int reg, unsigned int value); ++int tasdevice_spi_dev_bulk_write(struct tasdevice_priv *tas_priv, ++ unsigned int reg, unsigned char *p_data, ++ unsigned int n_length); ++int tasdevice_spi_dev_bulk_read(struct tasdevice_priv *tas_priv, ++ unsigned int reg, unsigned char *p_data, ++ unsigned int n_length); ++int tasdevice_spi_dev_update_bits(struct tasdevice_priv *tasdevice, ++ unsigned int reg, unsigned int mask, ++ unsigned int value); ++ ++void tasdevice_spi_select_cfg_blk(void *context, int conf_no, ++ unsigned char block_type); ++void tasdevice_spi_config_info_remove(void *context); ++int tasdevice_spi_dsp_parser(void *context); ++int tasdevice_spi_rca_parser(void *context, const struct firmware *fmw); ++void tasdevice_spi_dsp_remove(void *context); ++void tasdevice_spi_calbin_remove(void *context); ++int tasdevice_spi_select_tuningprm_cfg(void *context, int prm, int cfg_no, ++ int rca_conf_no); ++int tasdevice_spi_prmg_load(void *context, int prm_no); ++int tasdevice_spi_prmg_calibdata_load(void *context, int prm_no); ++void tasdevice_spi_tuning_switch(void *context, int state); ++int tas2781_spi_load_calibration(void *context, char *file_name, ++ unsigned short i); ++#endif /* __TAS2781_SPI_H__ */ +diff --git a/sound/pci/hda/tas2781_hda_spi.c b/sound/pci/hda/tas2781_hda_spi.c +new file mode 100644 +index 0000000000000..8068c70b70147 +--- /dev/null ++++ b/sound/pci/hda/tas2781_hda_spi.c +@@ -0,0 +1,1271 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// TAS2781 HDA SPI driver ++// ++// Copyright 2024 Texas Instruments, Inc. ++// ++// Author: Baojun Xu ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "tas2781-spi.h" ++ ++#include "hda_local.h" ++#include "hda_auto_parser.h" ++#include "hda_component.h" ++#include "hda_jack.h" ++#include "hda_generic.h" ++ ++/* ++ * No standard control callbacks for SNDRV_CTL_ELEM_IFACE_CARD ++ * Define two controls, one is Volume control callbacks, the other is ++ * flag setting control callbacks. ++ */ ++ ++/* Volume control callbacks for tas2781 */ ++#define ACARD_SINGLE_RANGE_EXT_TLV(xname, xreg, xshift, xmin, xmax, xinvert, \ ++ xhandler_get, xhandler_put, tlv_array) { \ ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = (xname), \ ++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ ++ SNDRV_CTL_ELEM_ACCESS_READWRITE, \ ++ .tlv.p = (tlv_array), \ ++ .info = snd_soc_info_volsw_range, \ ++ .get = xhandler_get, .put = xhandler_put, \ ++ .private_value = (unsigned long)&(struct soc_mixer_control) { \ ++ .reg = xreg, .rreg = xreg, \ ++ .shift = xshift, .rshift = xshift,\ ++ .min = xmin, .max = xmax, .invert = xinvert, \ ++ } \ ++} ++ ++/* Flag control callbacks for tas2781 */ ++#define ACARD_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) { \ ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ ++ .name = xname, \ ++ .info = snd_ctl_boolean_mono_info, \ ++ .get = xhandler_get, \ ++ .put = xhandler_put, \ ++ .private_value = xdata, \ ++} ++ ++struct tas2781_hda { ++ struct tasdevice_priv *priv; ++ struct acpi_device *dacpi; ++ struct snd_kcontrol *dsp_prog_ctl; ++ struct snd_kcontrol *dsp_conf_ctl; ++ struct snd_kcontrol *snd_ctls[3]; ++ struct snd_kcontrol *prof_ctl; ++}; ++ ++static const struct regmap_range_cfg tasdevice_ranges[] = { ++ { ++ .range_min = 0, ++ .range_max = TASDEVICE_MAX_SIZE, ++ .selector_reg = TASDEVICE_PAGE_SELECT, ++ .selector_mask = GENMASK(7, 0), ++ .selector_shift = 0, ++ .window_start = 0, ++ .window_len = TASDEVICE_MAX_PAGE, ++ }, ++}; ++ ++static const struct regmap_config tasdevice_regmap = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .zero_flag_mask = true, ++ .cache_type = REGCACHE_NONE, ++ .ranges = tasdevice_ranges, ++ .num_ranges = ARRAY_SIZE(tasdevice_ranges), ++ .max_register = TASDEVICE_MAX_SIZE, ++}; ++ ++static int tasdevice_spi_switch_book(struct tasdevice_priv *tas_priv, int reg) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret; ++ ++ if (tas_priv->cur_book != TASDEVICE_BOOK_ID(reg)) { ++ ret = regmap_write(map, TASDEVICE_BOOKCTL_REG, ++ TASDEVICE_BOOK_ID(reg)); ++ if (ret < 0) { ++ dev_err(tas_priv->dev, "Switch Book E=%d\n", ret); ++ return ret; ++ } ++ tas_priv->cur_book = TASDEVICE_BOOK_ID(reg); ++ } ++ return ret; ++} ++ ++int tasdevice_spi_dev_read(struct tasdevice_priv *tas_priv, ++ unsigned int reg, ++ unsigned int *val) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret; ++ ++ ret = tasdevice_spi_switch_book(tas_priv, reg); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * In our TAS2781 SPI mode, if read from other book (not book 0), ++ * or read from page number larger than 1 in book 0, one more byte ++ * read is needed, and first byte is a dummy byte, need to be ignored. ++ */ ++ if ((TASDEVICE_BOOK_ID(reg) > 0) || (TASDEVICE_PAGE_ID(reg) > 1)) { ++ unsigned char data[2]; ++ ++ ret = regmap_bulk_read(map, TASDEVICE_PAGE_REG(reg) | 1, ++ data, sizeof(data)); ++ *val = data[1]; ++ } else { ++ ret = regmap_read(map, TASDEVICE_PAGE_REG(reg) | 1, val); ++ } ++ if (ret < 0) ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ ++ return ret; ++} ++ ++int tasdevice_spi_dev_write(struct tasdevice_priv *tas_priv, ++ unsigned int reg, ++ unsigned int value) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret; ++ ++ ret = tasdevice_spi_switch_book(tas_priv, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_write(map, TASDEVICE_PAGE_REG(reg), value); ++ if (ret < 0) ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ ++ return ret; ++} ++ ++int tasdevice_spi_dev_bulk_write(struct tasdevice_priv *tas_priv, ++ unsigned int reg, ++ unsigned char *data, ++ unsigned int len) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret; ++ ++ ret = tasdevice_spi_switch_book(tas_priv, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_bulk_write(map, TASDEVICE_PAGE_REG(reg), data, len); ++ if (ret < 0) ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ ++ return ret; ++} ++ ++int tasdevice_spi_dev_bulk_read(struct tasdevice_priv *tas_priv, ++ unsigned int reg, ++ unsigned char *data, ++ unsigned int len) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret; ++ ++ ret = tasdevice_spi_switch_book(tas_priv, reg); ++ if (ret < 0) ++ return ret; ++ ++ if (len > TASDEVICE_MAX_PAGE) ++ len = TASDEVICE_MAX_PAGE; ++ /* ++ * In our TAS2781 SPI mode, if read from other book (not book 0), ++ * or read from page number larger than 1 in book 0, one more byte ++ * read is needed, and first byte is a dummy byte, need to be ignored. ++ */ ++ if ((TASDEVICE_BOOK_ID(reg) > 0) || (TASDEVICE_PAGE_ID(reg) > 1)) { ++ unsigned char buf[TASDEVICE_MAX_PAGE+1]; ++ ++ ret = regmap_bulk_read(map, TASDEVICE_PAGE_REG(reg) | 1, buf, ++ len + 1); ++ memcpy(data, buf + 1, len); ++ } else { ++ ret = regmap_bulk_read(map, TASDEVICE_PAGE_REG(reg) | 1, data, ++ len); ++ } ++ if (ret < 0) ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ ++ return ret; ++} ++ ++int tasdevice_spi_dev_update_bits(struct tasdevice_priv *tas_priv, ++ unsigned int reg, ++ unsigned int mask, ++ unsigned int value) ++{ ++ struct regmap *map = tas_priv->regmap; ++ int ret, val; ++ ++ /* ++ * In our TAS2781 SPI mode, read/write was masked in last bit of ++ * address, it cause regmap_update_bits() not work as expected. ++ */ ++ ret = tasdevice_spi_dev_read(tas_priv, reg, &val); ++ if (ret < 0) { ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ return ret; ++ } ++ ret = regmap_write(map, TASDEVICE_PAGE_REG(reg), ++ (val & ~mask) | (mask & value)); ++ if (ret < 0) ++ dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); ++ ++ return ret; ++} ++ ++static void tas2781_spi_reset(struct tasdevice_priv *tas_dev) ++{ ++ int ret; ++ ++ if (tas_dev->reset) { ++ gpiod_set_value_cansleep(tas_dev->reset, 0); ++ fsleep(800); ++ gpiod_set_value_cansleep(tas_dev->reset, 1); ++ } ++ ret = tasdevice_spi_dev_write(tas_dev, TAS2781_REG_SWRESET, ++ TAS2781_REG_SWRESET_RESET); ++ if (ret < 0) ++ dev_err(tas_dev->dev, "dev sw-reset fail, %d\n", ret); ++ fsleep(1000); ++} ++ ++static int tascodec_spi_init(struct tasdevice_priv *tas_priv, ++ void *codec, struct module *module, ++ void (*cont)(const struct firmware *fw, void *context)) ++{ ++ int ret; ++ ++ /* ++ * Codec Lock Hold to ensure that codec_probe and firmware parsing and ++ * loading do not simultaneously execute. ++ */ ++ guard(mutex)(&tas_priv->codec_lock); ++ ++ ret = scnprintf(tas_priv->rca_binaryname, ++ sizeof(tas_priv->rca_binaryname), "%sRCA%d.bin", ++ tas_priv->dev_name, tas_priv->index); ++ if (ret <= 0) { ++ dev_err(tas_priv->dev, "rca name err:0x%08x\n", ret); ++ return ret; ++ } ++ crc8_populate_msb(tas_priv->crc8_lkp_tbl, TASDEVICE_CRC8_POLYNOMIAL); ++ tas_priv->codec = codec; ++ ret = request_firmware_nowait(module, FW_ACTION_UEVENT, ++ tas_priv->rca_binaryname, tas_priv->dev, GFP_KERNEL, tas_priv, ++ cont); ++ if (ret) ++ dev_err(tas_priv->dev, "request_firmware_nowait err:0x%08x\n", ++ ret); ++ ++ return ret; ++} ++ ++static void tasdevice_spi_init(struct tasdevice_priv *tas_priv) ++{ ++ tas_priv->cur_prog = -1; ++ tas_priv->cur_conf = -1; ++ ++ tas_priv->cur_book = -1; ++ tas_priv->cur_prog = -1; ++ tas_priv->cur_conf = -1; ++ ++ /* Store default registers address for calibration data. */ ++ tas_priv->cali_reg_array[0] = TASDEVICE_REG(0, 0x17, 0x74); ++ tas_priv->cali_reg_array[1] = TASDEVICE_REG(0, 0x18, 0x0c); ++ tas_priv->cali_reg_array[2] = TASDEVICE_REG(0, 0x18, 0x14); ++ tas_priv->cali_reg_array[3] = TASDEVICE_REG(0, 0x13, 0x70); ++ tas_priv->cali_reg_array[4] = TASDEVICE_REG(0, 0x18, 0x7c); ++ ++ mutex_init(&tas_priv->codec_lock); ++} ++ ++static int tasdevice_spi_amp_putvol(struct tasdevice_priv *tas_priv, ++ struct snd_ctl_elem_value *ucontrol, ++ struct soc_mixer_control *mc) ++{ ++ unsigned int invert = mc->invert; ++ unsigned char mask; ++ int max = mc->max; ++ int val, ret; ++ ++ mask = rounddown_pow_of_two(max); ++ mask <<= mc->shift; ++ val = clamp(invert ? max - ucontrol->value.integer.value[0] : ++ ucontrol->value.integer.value[0], 0, max); ++ ret = tasdevice_spi_dev_update_bits(tas_priv, ++ mc->reg, mask, (unsigned int)(val << mc->shift)); ++ if (ret) ++ dev_err(tas_priv->dev, "set AMP vol error in dev %d\n", ++ tas_priv->index); ++ ++ return ret; ++} ++ ++static int tasdevice_spi_amp_getvol(struct tasdevice_priv *tas_priv, ++ struct snd_ctl_elem_value *ucontrol, ++ struct soc_mixer_control *mc) ++{ ++ unsigned int invert = mc->invert; ++ unsigned char mask = 0; ++ int max = mc->max; ++ int ret, val; ++ ++ /* Read the primary device */ ++ ret = tasdevice_spi_dev_read(tas_priv, mc->reg, &val); ++ if (ret) { ++ dev_err(tas_priv->dev, "%s, get AMP vol error\n", __func__); ++ return ret; ++ } ++ ++ mask = rounddown_pow_of_two(max); ++ mask <<= mc->shift; ++ val = (val & mask) >> mc->shift; ++ val = clamp(invert ? max - val : val, 0, max); ++ ucontrol->value.integer.value[0] = val; ++ ++ return ret; ++} ++ ++static int tasdevice_spi_digital_putvol(struct tasdevice_priv *tas_priv, ++ struct snd_ctl_elem_value *ucontrol, ++ struct soc_mixer_control *mc) ++{ ++ unsigned int invert = mc->invert; ++ int max = mc->max; ++ int val, ret; ++ ++ val = clamp(invert ? max - ucontrol->value.integer.value[0] : ++ ucontrol->value.integer.value[0], 0, max); ++ ret = tasdevice_spi_dev_write(tas_priv, mc->reg, (unsigned int)val); ++ if (ret) ++ dev_err(tas_priv->dev, "set digital vol err in dev %d\n", ++ tas_priv->index); ++ ++ return ret; ++} ++ ++static int tasdevice_spi_digital_getvol(struct tasdevice_priv *tas_priv, ++ struct snd_ctl_elem_value *ucontrol, ++ struct soc_mixer_control *mc) ++{ ++ unsigned int invert = mc->invert; ++ int max = mc->max; ++ int ret, val; ++ ++ /* Read the primary device as the whole */ ++ ret = tasdevice_spi_dev_read(tas_priv, mc->reg, &val); ++ if (ret) { ++ dev_err(tas_priv->dev, "%s, get digital vol err\n", __func__); ++ return ret; ++ } ++ ++ val = clamp(invert ? max - val : val, 0, max); ++ ucontrol->value.integer.value[0] = val; ++ ++ return ret; ++} ++ ++static int tas2781_read_acpi(struct tas2781_hda *tas_hda, ++ const char *hid, ++ int id) ++{ ++ struct tasdevice_priv *p = tas_hda->priv; ++ struct acpi_device *adev; ++ struct device *physdev; ++ u32 values[HDA_MAX_COMPONENTS]; ++ const char *property; ++ size_t nval; ++ int ret, i; ++ ++ adev = acpi_dev_get_first_match_dev(hid, NULL, -1); ++ if (!adev) { ++ dev_err(p->dev, "Failed to find ACPI device: %s\n", hid); ++ return -ENODEV; ++ } ++ ++ strscpy(p->dev_name, hid, sizeof(p->dev_name)); ++ tas_hda->dacpi = adev; ++ physdev = get_device(acpi_get_first_physical_node(adev)); ++ acpi_dev_put(adev); ++ ++ property = "ti,dev-index"; ++ ret = device_property_count_u32(physdev, property); ++ if (ret <= 0 || ret > ARRAY_SIZE(values)) { ++ ret = -EINVAL; ++ goto err; ++ } ++ nval = ret; ++ ++ ret = device_property_read_u32_array(physdev, property, values, nval); ++ if (ret) ++ goto err; ++ ++ p->index = U8_MAX; ++ for (i = 0; i < nval; i++) { ++ if (values[i] == id) { ++ p->index = i; ++ break; ++ } ++ } ++ if (p->index == U8_MAX) { ++ dev_dbg(p->dev, "No index found in %s\n", property); ++ ret = -ENODEV; ++ goto err; ++ } ++ ++ if (p->index == 0) { ++ /* All of amps share same RESET pin. */ ++ p->reset = devm_gpiod_get_index_optional(physdev, "reset", ++ p->index, GPIOD_OUT_LOW); ++ if (IS_ERR(p->reset)) { ++ dev_err_probe(p->dev, ret, "Failed on reset GPIO\n"); ++ goto err; ++ } ++ } ++ put_device(physdev); ++ ++ return 0; ++err: ++ dev_err(p->dev, "read acpi error, ret: %d\n", ret); ++ put_device(physdev); ++ acpi_dev_put(adev); ++ ++ return ret; ++} ++ ++static void tas2781_hda_playback_hook(struct device *dev, int action) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ ++ if (action == HDA_GEN_PCM_ACT_OPEN) { ++ pm_runtime_get_sync(dev); ++ guard(mutex)(&tas_hda->priv->codec_lock); ++ tasdevice_spi_tuning_switch(tas_hda->priv, 0); ++ } else if (action == HDA_GEN_PCM_ACT_CLOSE) { ++ guard(mutex)(&tas_hda->priv->codec_lock); ++ tasdevice_spi_tuning_switch(tas_hda->priv, 1); ++ pm_runtime_mark_last_busy(dev); ++ pm_runtime_put_autosuspend(dev); ++ } ++} ++ ++static int tasdevice_info_profile(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = tas_priv->rcabin.ncfgs - 1; ++ ++ return 0; ++} ++ ++static int tasdevice_get_profile_id(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ ucontrol->value.integer.value[0] = tas_priv->rcabin.profile_cfg_id; ++ ++ return 0; ++} ++ ++static int tasdevice_set_profile_id(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ int max = tas_priv->rcabin.ncfgs - 1; ++ int val; ++ ++ val = clamp(ucontrol->value.integer.value[0], 0, max); ++ if (tas_priv->rcabin.profile_cfg_id != val) { ++ tas_priv->rcabin.profile_cfg_id = val; ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int tasdevice_info_programs(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = tas_priv->fmw->nr_programs - 1; ++ ++ return 0; ++} ++ ++static int tasdevice_info_config(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = tas_priv->fmw->nr_configurations - 1; ++ ++ return 0; ++} ++ ++static int tasdevice_program_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ ucontrol->value.integer.value[0] = tas_priv->cur_prog; ++ ++ return 0; ++} ++ ++static int tasdevice_program_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ int nr_program = ucontrol->value.integer.value[0]; ++ int max = tas_priv->fmw->nr_programs - 1; ++ int val; ++ ++ val = clamp(nr_program, 0, max); ++ ++ if (tas_priv->cur_prog != val) { ++ tas_priv->cur_prog = val; ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int tasdevice_config_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ ucontrol->value.integer.value[0] = tas_priv->cur_conf; ++ ++ return 0; ++} ++ ++static int tasdevice_config_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ int max = tas_priv->fmw->nr_configurations - 1; ++ int val; ++ ++ val = clamp(ucontrol->value.integer.value[0], 0, max); ++ ++ if (tas_priv->cur_conf != val) { ++ tas_priv->cur_conf = val; ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* ++ * tas2781_digital_getvol - get the volum control ++ * @kcontrol: control pointer ++ * @ucontrol: User data ++ * ++ * Customer Kcontrol for tas2781 is primarily for regmap booking, paging ++ * depends on internal regmap mechanism. ++ * tas2781 contains book and page two-level register map, especially ++ * book switching will set the register BXXP00R7F, after switching to the ++ * correct book, then leverage the mechanism for paging to access the ++ * register. ++ * ++ * Return 0 if succeeded. ++ */ ++static int tas2781_digital_getvol(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ struct soc_mixer_control *mc = ++ (struct soc_mixer_control *)kcontrol->private_value; ++ ++ return tasdevice_spi_digital_getvol(tas_priv, ucontrol, mc); ++} ++ ++static int tas2781_amp_getvol(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ struct soc_mixer_control *mc = ++ (struct soc_mixer_control *)kcontrol->private_value; ++ ++ return tasdevice_spi_amp_getvol(tas_priv, ucontrol, mc); ++} ++ ++static int tas2781_digital_putvol(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ struct soc_mixer_control *mc = ++ (struct soc_mixer_control *)kcontrol->private_value; ++ ++ /* The check of the given value is in tasdevice_digital_putvol. */ ++ return tasdevice_spi_digital_putvol(tas_priv, ucontrol, mc); ++} ++ ++static int tas2781_amp_putvol(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ struct soc_mixer_control *mc = ++ (struct soc_mixer_control *)kcontrol->private_value; ++ ++ /* The check of the given value is in tasdevice_amp_putvol. */ ++ return tasdevice_spi_amp_putvol(tas_priv, ucontrol, mc); ++} ++ ++static int tas2781_force_fwload_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ ++ ucontrol->value.integer.value[0] = (int)tas_priv->force_fwload_status; ++ dev_dbg(tas_priv->dev, "%s : Force FWload %s\n", __func__, ++ str_on_off(tas_priv->force_fwload_status)); ++ ++ return 0; ++} ++ ++static int tas2781_force_fwload_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct tasdevice_priv *tas_priv = snd_kcontrol_chip(kcontrol); ++ bool change, val = (bool)ucontrol->value.integer.value[0]; ++ ++ if (tas_priv->force_fwload_status == val) { ++ change = false; ++ } else { ++ change = true; ++ tas_priv->force_fwload_status = val; ++ } ++ dev_dbg(tas_priv->dev, "%s : Force FWload %s\n", __func__, ++ str_on_off(tas_priv->force_fwload_status)); ++ ++ return change; ++} ++ ++static const struct snd_kcontrol_new tas2781_snd_controls[] = { ++ ACARD_SINGLE_RANGE_EXT_TLV("Speaker Analog Gain 0", TAS2781_AMP_LEVEL, ++ 1, 0, 20, 0, tas2781_amp_getvol, ++ tas2781_amp_putvol, amp_vol_tlv), ++ ACARD_SINGLE_RANGE_EXT_TLV("Speaker Digital Gain 0", TAS2781_DVC_LVL, ++ 0, 0, 200, 1, tas2781_digital_getvol, ++ tas2781_digital_putvol, dvc_tlv), ++ ACARD_SINGLE_BOOL_EXT("Speaker Force Firmware Load 0", 0, ++ tas2781_force_fwload_get, tas2781_force_fwload_put), ++ ACARD_SINGLE_RANGE_EXT_TLV("Speaker Analog Gain 1", TAS2781_AMP_LEVEL, ++ 1, 0, 20, 0, tas2781_amp_getvol, ++ tas2781_amp_putvol, amp_vol_tlv), ++ ACARD_SINGLE_RANGE_EXT_TLV("Speaker Digital Gain 1", TAS2781_DVC_LVL, ++ 0, 0, 200, 1, tas2781_digital_getvol, ++ tas2781_digital_putvol, dvc_tlv), ++ ACARD_SINGLE_BOOL_EXT("Speaker Force Firmware Load 1", 0, ++ tas2781_force_fwload_get, tas2781_force_fwload_put), ++}; ++ ++static const struct snd_kcontrol_new tas2781_prof_ctrl[] = { ++{ ++ .name = "Speaker Profile Id - 0", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_profile, ++ .get = tasdevice_get_profile_id, ++ .put = tasdevice_set_profile_id, ++}, ++{ ++ .name = "Speaker Profile Id - 1", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_profile, ++ .get = tasdevice_get_profile_id, ++ .put = tasdevice_set_profile_id, ++}, ++}; ++static const struct snd_kcontrol_new tas2781_dsp_prog_ctrl[] = { ++{ ++ .name = "Speaker Program Id 0", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_programs, ++ .get = tasdevice_program_get, ++ .put = tasdevice_program_put, ++}, ++{ ++ .name = "Speaker Program Id 1", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_programs, ++ .get = tasdevice_program_get, ++ .put = tasdevice_program_put, ++}, ++}; ++ ++static const struct snd_kcontrol_new tas2781_dsp_conf_ctrl[] = { ++{ ++ .name = "Speaker Config Id 0", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_config, ++ .get = tasdevice_config_get, ++ .put = tasdevice_config_put, ++}, ++{ ++ .name = "Speaker Config Id 1", ++ .iface = SNDRV_CTL_ELEM_IFACE_CARD, ++ .info = tasdevice_info_config, ++ .get = tasdevice_config_get, ++ .put = tasdevice_config_put, ++}, ++}; ++ ++static void tas2781_apply_calib(struct tasdevice_priv *tas_priv) ++{ ++ int i, rc; ++ ++ /* ++ * If no calibration data exist in tasdevice_priv *tas_priv, ++ * calibration apply will be ignored, and use default values ++ * in firmware binary, which was loaded during firmware download. ++ */ ++ if (tas_priv->cali_data[0] == 0) ++ return; ++ /* ++ * Calibration data was saved in tasdevice_priv *tas_priv as: ++ * unsigned int cali_data[CALIB_MAX]; ++ * and every data (in 4 bytes) will be saved in register which in ++ * book 0, and page number in page_array[], offset was saved in ++ * rgno_array[]. ++ */ ++ for (i = 0; i < CALIB_MAX; i++) { ++ rc = tasdevice_spi_dev_bulk_write(tas_priv, ++ tas_priv->cali_reg_array[i], ++ (unsigned char *)&tas_priv->cali_data[i], 4); ++ if (rc < 0) ++ dev_err(tas_priv->dev, ++ "chn %d calib %d bulk_wr err = %d\n", ++ tas_priv->index, i, rc); ++ } ++} ++ ++/* ++ * Update the calibration data, including speaker impedance, f0, etc, ++ * into algo. Calibrate data is done by manufacturer in the factory. ++ * These data are used by Algo for calculating the speaker temperature, ++ * speaker membrane excursion and f0 in real time during playback. ++ * Calibration data format in EFI is V2, since 2024. ++ */ ++static int tas2781_save_calibration(struct tasdevice_priv *tas_priv) ++{ ++ /* ++ * GUID was used for data access in BIOS, it was provided by board ++ * manufactory, like HP: "{02f9af02-7734-4233-b43d-93fe5aa35db3}" ++ */ ++ efi_guid_t efi_guid = ++ EFI_GUID(0x02f9af02, 0x7734, 0x4233, ++ 0xb4, 0x3d, 0x93, 0xfe, 0x5a, 0xa3, 0x5d, 0xb3); ++ static efi_char16_t efi_name[] = TASDEVICE_CALIBRATION_DATA_NAME; ++ unsigned char data[TASDEVICE_CALIBRATION_DATA_SIZE], *buf; ++ unsigned int attr, crc, offset, *tmp_val; ++ struct tm *tm = &tas_priv->tm; ++ unsigned long total_sz = 0; ++ efi_status_t status; ++ ++ tas_priv->cali_data[0] = 0; ++ status = efi.get_variable(efi_name, &efi_guid, &attr, &total_sz, data); ++ if (status == EFI_BUFFER_TOO_SMALL) { ++ if (total_sz > TASDEVICE_CALIBRATION_DATA_SIZE) ++ return -ENOMEM; ++ /* Get variable contents into buffer */ ++ status = efi.get_variable(efi_name, &efi_guid, &attr, ++ &total_sz, data); ++ } ++ if (status != EFI_SUCCESS) ++ return status; ++ ++ tmp_val = (unsigned int *)data; ++ if (tmp_val[0] == 2781) { ++ /* ++ * New features were added in calibrated Data V3: ++ * 1. Added calibration registers address define in ++ * a node, marked as Device id == 0x80. ++ * New features were added in calibrated Data V2: ++ * 1. Added some the fields to store the link_id and ++ * uniqie_id for multi-link solutions ++ * 2. Support flexible number of devices instead of ++ * fixed one in V1. ++ * Layout of calibrated data V2 in UEFI(total 256 bytes): ++ * ChipID (2781, 4 bytes) ++ * Device-Sum (4 bytes) ++ * TimeStamp of Calibration (4 bytes) ++ * for (i = 0; i < Device-Sum; i++) { ++ * Device #i index_info () { ++ * SDW link id (2bytes) ++ * SDW unique_id (2bytes) ++ * } // if Device number is 0x80, mean it's ++ * calibration registers address. ++ * Calibrated Data of Device #i (20 bytes) ++ * } ++ * CRC (4 bytes) ++ * Reserved (the rest) ++ */ ++ crc = crc32(~0, data, (3 + tmp_val[1] * 6) * 4) ^ ~0; ++ ++ if (crc != tmp_val[3 + tmp_val[1] * 6]) ++ return 0; ++ ++ time64_to_tm(tmp_val[2], 0, tm); ++ for (int j = 0; j < tmp_val[1]; j++) { ++ offset = j * 6 + 3; ++ if (tmp_val[offset] == tas_priv->index) { ++ for (int i = 0; i < CALIB_MAX; i++) ++ tas_priv->cali_data[i] = ++ tmp_val[offset + i + 1]; ++ } else if (tmp_val[offset] == ++ TASDEVICE_CALIBRATION_REG_ADDRESS) { ++ for (int i = 0; i < CALIB_MAX; i++) { ++ buf = &data[(offset + i + 1) * 4]; ++ tas_priv->cali_reg_array[i] = ++ TASDEVICE_REG(buf[1], buf[2], ++ buf[3]); ++ } ++ } ++ tas_priv->apply_calibration(tas_priv); ++ } ++ } else { ++ /* ++ * Calibration data is in V1 format. ++ * struct cali_data { ++ * char cali_data[20]; ++ * } ++ * ++ * struct { ++ * struct cali_data cali_data[4]; ++ * int TimeStamp of Calibration (4 bytes) ++ * int CRC (4 bytes) ++ * } ueft; ++ */ ++ crc = crc32(~0, data, 84) ^ ~0; ++ if (crc == tmp_val[21]) { ++ time64_to_tm(tmp_val[20], 0, tm); ++ for (int i = 0; i < CALIB_MAX; i++) ++ tas_priv->cali_data[i] = ++ tmp_val[tas_priv->index * 5 + i]; ++ tas_priv->apply_calibration(tas_priv); ++ } ++ } ++ ++ return 0; ++} ++ ++static void tas2781_hda_remove_controls(struct tas2781_hda *tas_hda) ++{ ++ struct hda_codec *codec = tas_hda->priv->codec; ++ ++ snd_ctl_remove(codec->card, tas_hda->dsp_prog_ctl); ++ ++ snd_ctl_remove(codec->card, tas_hda->dsp_conf_ctl); ++ ++ for (int i = ARRAY_SIZE(tas_hda->snd_ctls) - 1; i >= 0; i--) ++ snd_ctl_remove(codec->card, tas_hda->snd_ctls[i]); ++ ++ snd_ctl_remove(codec->card, tas_hda->prof_ctl); ++} ++ ++static void tasdev_fw_ready(const struct firmware *fmw, void *context) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ struct tas2781_hda *tas_hda = dev_get_drvdata(tas_priv->dev); ++ struct hda_codec *codec = tas_priv->codec; ++ int i, j, ret; ++ ++ pm_runtime_get_sync(tas_priv->dev); ++ guard(mutex)(&tas_priv->codec_lock); ++ ++ ret = tasdevice_spi_rca_parser(tas_priv, fmw); ++ if (ret) ++ goto out; ++ ++ /* Add control one time only. */ ++ tas_hda->prof_ctl = snd_ctl_new1(&tas2781_prof_ctrl[tas_priv->index], ++ tas_priv); ++ ret = snd_ctl_add(codec->card, tas_hda->prof_ctl); ++ if (ret) { ++ dev_err(tas_priv->dev, "Failed to add KControl %s = %d\n", ++ tas2781_prof_ctrl[tas_priv->index].name, ret); ++ goto out; ++ } ++ j = tas_priv->index * ARRAY_SIZE(tas2781_snd_controls) / 2; ++ for (i = 0; i < 3; i++) { ++ tas_hda->snd_ctls[i] = snd_ctl_new1(&tas2781_snd_controls[i+j], ++ tas_priv); ++ ret = snd_ctl_add(codec->card, tas_hda->snd_ctls[i]); ++ if (ret) { ++ dev_err(tas_priv->dev, ++ "Failed to add KControl %s = %d\n", ++ tas2781_snd_controls[i+tas_priv->index*3].name, ++ ret); ++ goto out; ++ } ++ } ++ ++ tasdevice_spi_dsp_remove(tas_priv); ++ ++ tas_priv->fw_state = TASDEVICE_DSP_FW_PENDING; ++ scnprintf(tas_priv->coef_binaryname, 64, "TAS2XXX%08X-%01d.bin", ++ codec->core.subsystem_id, tas_priv->index); ++ ret = tasdevice_spi_dsp_parser(tas_priv); ++ if (ret) { ++ dev_err(tas_priv->dev, "dspfw load %s error\n", ++ tas_priv->coef_binaryname); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ goto out; ++ } ++ ++ /* Add control one time only. */ ++ tas_hda->dsp_prog_ctl = ++ snd_ctl_new1(&tas2781_dsp_prog_ctrl[tas_priv->index], ++ tas_priv); ++ ret = snd_ctl_add(codec->card, tas_hda->dsp_prog_ctl); ++ if (ret) { ++ dev_err(tas_priv->dev, ++ "Failed to add KControl %s = %d\n", ++ tas2781_dsp_prog_ctrl[tas_priv->index].name, ret); ++ goto out; ++ } ++ ++ tas_hda->dsp_conf_ctl = ++ snd_ctl_new1(&tas2781_dsp_conf_ctrl[tas_priv->index], ++ tas_priv); ++ ret = snd_ctl_add(codec->card, tas_hda->dsp_conf_ctl); ++ if (ret) { ++ dev_err(tas_priv->dev, "Failed to add KControl %s = %d\n", ++ tas2781_dsp_conf_ctrl[tas_priv->index].name, ret); ++ goto out; ++ } ++ ++ /* Perform AMP reset before firmware download. */ ++ tas_priv->rcabin.profile_cfg_id = TAS2781_PRE_POST_RESET_CFG; ++ tasdevice_spi_tuning_switch(tas_priv, 0); ++ tas2781_spi_reset(tas_priv); ++ tas_priv->rcabin.profile_cfg_id = 0; ++ tasdevice_spi_tuning_switch(tas_priv, 1); ++ ++ tas_priv->fw_state = TASDEVICE_DSP_FW_ALL_OK; ++ ret = tasdevice_spi_prmg_load(tas_priv, 0); ++ if (ret < 0) { ++ dev_err(tas_priv->dev, "FW download failed = %d\n", ret); ++ goto out; ++ } ++ if (tas_priv->fmw->nr_programs > 0) ++ tas_priv->cur_prog = 0; ++ if (tas_priv->fmw->nr_configurations > 0) ++ tas_priv->cur_conf = 0; ++ ++ /* ++ * If calibrated data occurs error, dsp will still works with default ++ * calibrated data inside algo. ++ */ ++ tas_priv->save_calibration(tas_priv); ++ ++out: ++ if (fmw) ++ release_firmware(fmw); ++ pm_runtime_mark_last_busy(tas_hda->priv->dev); ++ pm_runtime_put_autosuspend(tas_hda->priv->dev); ++} ++ ++static int tas2781_hda_bind(struct device *dev, struct device *master, ++ void *master_data) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ struct hda_component_parent *parent = master_data; ++ struct hda_component *comp; ++ struct hda_codec *codec; ++ int ret; ++ ++ comp = hda_component_from_index(parent, tas_hda->priv->index); ++ if (!comp) ++ return -EINVAL; ++ ++ if (comp->dev) ++ return -EBUSY; ++ ++ codec = parent->codec; ++ ++ pm_runtime_get_sync(dev); ++ ++ comp->dev = dev; ++ ++ strscpy(comp->name, dev_name(dev), sizeof(comp->name)); ++ ++ ret = tascodec_spi_init(tas_hda->priv, codec, THIS_MODULE, ++ tasdev_fw_ready); ++ if (!ret) ++ comp->playback_hook = tas2781_hda_playback_hook; ++ ++ pm_runtime_mark_last_busy(dev); ++ pm_runtime_put_autosuspend(dev); ++ ++ return ret; ++} ++ ++static void tas2781_hda_unbind(struct device *dev, struct device *master, ++ void *master_data) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ struct hda_component_parent *parent = master_data; ++ struct hda_component *comp; ++ ++ comp = hda_component_from_index(parent, tas_hda->priv->index); ++ if (comp && (comp->dev == dev)) { ++ comp->dev = NULL; ++ memset(comp->name, 0, sizeof(comp->name)); ++ comp->playback_hook = NULL; ++ } ++ ++ tas2781_hda_remove_controls(tas_hda); ++ ++ tasdevice_spi_config_info_remove(tas_hda->priv); ++ tasdevice_spi_dsp_remove(tas_hda->priv); ++ ++ tas_hda->priv->fw_state = TASDEVICE_DSP_FW_PENDING; ++} ++ ++static const struct component_ops tas2781_hda_comp_ops = { ++ .bind = tas2781_hda_bind, ++ .unbind = tas2781_hda_unbind, ++}; ++ ++static void tas2781_hda_remove(struct device *dev) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ ++ component_del(tas_hda->priv->dev, &tas2781_hda_comp_ops); ++ ++ pm_runtime_get_sync(tas_hda->priv->dev); ++ pm_runtime_disable(tas_hda->priv->dev); ++ ++ pm_runtime_put_noidle(tas_hda->priv->dev); ++ ++ mutex_destroy(&tas_hda->priv->codec_lock); ++} ++ ++static int tas2781_hda_spi_probe(struct spi_device *spi) ++{ ++ struct tasdevice_priv *tas_priv; ++ struct tas2781_hda *tas_hda; ++ const char *device_name; ++ int ret = 0; ++ ++ tas_hda = devm_kzalloc(&spi->dev, sizeof(*tas_hda), GFP_KERNEL); ++ if (!tas_hda) ++ return -ENOMEM; ++ ++ spi->max_speed_hz = TAS2781_SPI_MAX_FREQ; ++ ++ tas_priv = devm_kzalloc(&spi->dev, sizeof(*tas_priv), GFP_KERNEL); ++ if (!tas_priv) ++ goto err; ++ tas_priv->dev = &spi->dev; ++ tas_hda->priv = tas_priv; ++ tas_priv->regmap = devm_regmap_init_spi(spi, &tasdevice_regmap); ++ if (IS_ERR(tas_priv->regmap)) { ++ ret = PTR_ERR(tas_priv->regmap); ++ dev_err(tas_priv->dev, "Failed to allocate regmap: %d\n", ++ ret); ++ goto err; ++ } ++ if (strstr(dev_name(&spi->dev), "TXNW2781")) { ++ device_name = "TXNW2781"; ++ tas_priv->save_calibration = tas2781_save_calibration; ++ tas_priv->apply_calibration = tas2781_apply_calib; ++ } else { ++ goto err; ++ } ++ ++ tas_priv->irq = spi->irq; ++ dev_set_drvdata(&spi->dev, tas_hda); ++ ret = tas2781_read_acpi(tas_hda, device_name, ++ spi_get_chipselect(spi, 0)); ++ if (ret) ++ return dev_err_probe(tas_priv->dev, ret, ++ "Platform not supported\n"); ++ ++ tasdevice_spi_init(tas_priv); ++ ++ pm_runtime_set_autosuspend_delay(tas_priv->dev, 3000); ++ pm_runtime_use_autosuspend(tas_priv->dev); ++ pm_runtime_mark_last_busy(tas_priv->dev); ++ pm_runtime_set_active(tas_priv->dev); ++ pm_runtime_get_noresume(tas_priv->dev); ++ pm_runtime_enable(tas_priv->dev); ++ ++ pm_runtime_put_autosuspend(tas_priv->dev); ++ ++ ret = component_add(tas_priv->dev, &tas2781_hda_comp_ops); ++ if (ret) { ++ dev_err(tas_priv->dev, "Register component fail: %d\n", ret); ++ pm_runtime_disable(tas_priv->dev); ++ } ++ ++err: ++ if (ret) ++ tas2781_hda_remove(&spi->dev); ++ ++ return ret; ++} ++ ++static void tas2781_hda_spi_remove(struct spi_device *spi) ++{ ++ tas2781_hda_remove(&spi->dev); ++} ++ ++static int tas2781_runtime_suspend(struct device *dev) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ ++ guard(mutex)(&tas_hda->priv->codec_lock); ++ ++ tasdevice_spi_tuning_switch(tas_hda->priv, 1); ++ ++ tas_hda->priv->cur_book = -1; ++ tas_hda->priv->cur_conf = -1; ++ ++ return 0; ++} ++ ++static int tas2781_runtime_resume(struct device *dev) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ ++ guard(mutex)(&tas_hda->priv->codec_lock); ++ ++ tasdevice_spi_tuning_switch(tas_hda->priv, 0); ++ ++ return 0; ++} ++ ++static int tas2781_system_suspend(struct device *dev) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = pm_runtime_force_suspend(dev); ++ if (ret) ++ return ret; ++ ++ /* Shutdown chip before system suspend */ ++ tasdevice_spi_tuning_switch(tas_hda->priv, 1); ++ tas2781_spi_reset(tas_hda->priv); ++ /* ++ * Reset GPIO may be shared, so cannot reset here. ++ * However beyond this point, amps may be powered down. ++ */ ++ return 0; ++} ++ ++static int tas2781_system_resume(struct device *dev) ++{ ++ struct tas2781_hda *tas_hda = dev_get_drvdata(dev); ++ int ret, val; ++ ++ ret = pm_runtime_force_resume(dev); ++ if (ret) ++ return ret; ++ ++ guard(mutex)(&tas_hda->priv->codec_lock); ++ ret = tasdevice_spi_dev_read(tas_hda->priv, TAS2781_REG_CLK_CONFIG, ++ &val); ++ if (ret < 0) ++ return ret; ++ ++ if (val == TAS2781_REG_CLK_CONFIG_RESET) { ++ tas_hda->priv->cur_book = -1; ++ tas_hda->priv->cur_conf = -1; ++ tas_hda->priv->cur_prog = -1; ++ ++ ret = tasdevice_spi_prmg_load(tas_hda->priv, 0); ++ if (ret < 0) { ++ dev_err(tas_hda->priv->dev, ++ "FW download failed = %d\n", ret); ++ return ret; ++ } ++ ++ if (tas_hda->priv->playback_started) ++ tasdevice_spi_tuning_switch(tas_hda->priv, 0); ++ } ++ ++ return ret; ++} ++ ++static const struct dev_pm_ops tas2781_hda_pm_ops = { ++ RUNTIME_PM_OPS(tas2781_runtime_suspend, tas2781_runtime_resume, NULL) ++ SYSTEM_SLEEP_PM_OPS(tas2781_system_suspend, tas2781_system_resume) ++}; ++ ++static const struct spi_device_id tas2781_hda_spi_id[] = { ++ { "tas2781-hda", }, ++ {} ++}; ++ ++static const struct acpi_device_id tas2781_acpi_hda_match[] = { ++ {"TXNW2781", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(acpi, tas2781_acpi_hda_match); ++ ++static struct spi_driver tas2781_hda_spi_driver = { ++ .driver = { ++ .name = "tas2781-hda", ++ .acpi_match_table = tas2781_acpi_hda_match, ++ .pm = &tas2781_hda_pm_ops, ++ }, ++ .id_table = tas2781_hda_spi_id, ++ .probe = tas2781_hda_spi_probe, ++ .remove = tas2781_hda_spi_remove, ++}; ++module_spi_driver(tas2781_hda_spi_driver); ++ ++MODULE_DESCRIPTION("TAS2781 HDA SPI Driver"); ++MODULE_AUTHOR("Baojun, Xu, "); ++MODULE_LICENSE("GPL"); +diff --git a/sound/pci/hda/tas2781_spi_fwlib.c b/sound/pci/hda/tas2781_spi_fwlib.c +new file mode 100644 +index 0000000000000..0e2acbc3c9001 +--- /dev/null ++++ b/sound/pci/hda/tas2781_spi_fwlib.c +@@ -0,0 +1,2006 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// TAS2781 HDA SPI driver ++// ++// Copyright 2024 Texas Instruments, Inc. ++// ++// Author: Baojun Xu ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "tas2781-spi.h" ++ ++#define OFFSET_ERROR_BIT BIT(31) ++ ++#define ERROR_PRAM_CRCCHK 0x0000000 ++#define ERROR_YRAM_CRCCHK 0x0000001 ++#define PPC_DRIVER_CRCCHK 0x00000200 ++ ++#define TAS2781_SA_COEFF_SWAP_REG TASDEVICE_REG(0, 0x35, 0x2c) ++#define TAS2781_YRAM_BOOK1 140 ++#define TAS2781_YRAM1_PAGE 42 ++#define TAS2781_YRAM1_START_REG 88 ++ ++#define TAS2781_YRAM2_START_PAGE 43 ++#define TAS2781_YRAM2_END_PAGE 49 ++#define TAS2781_YRAM2_START_REG 8 ++#define TAS2781_YRAM2_END_REG 127 ++ ++#define TAS2781_YRAM3_PAGE 50 ++#define TAS2781_YRAM3_START_REG 8 ++#define TAS2781_YRAM3_END_REG 27 ++ ++/* should not include B0_P53_R44-R47 */ ++#define TAS2781_YRAM_BOOK2 0 ++#define TAS2781_YRAM4_START_PAGE 50 ++#define TAS2781_YRAM4_END_PAGE 60 ++ ++#define TAS2781_YRAM5_PAGE 61 ++#define TAS2781_YRAM5_START_REG TAS2781_YRAM3_START_REG ++#define TAS2781_YRAM5_END_REG TAS2781_YRAM3_END_REG ++ ++#define TASDEVICE_MAXPROGRAM_NUM_KERNEL 5 ++#define TASDEVICE_MAXCONFIG_NUM_KERNEL_MULTIPLE_AMPS 64 ++#define TASDEVICE_MAXCONFIG_NUM_KERNEL 10 ++#define MAIN_ALL_DEVICES_1X 0x01 ++#define MAIN_DEVICE_A_1X 0x02 ++#define MAIN_DEVICE_B_1X 0x03 ++#define MAIN_DEVICE_C_1X 0x04 ++#define MAIN_DEVICE_D_1X 0x05 ++#define COEFF_DEVICE_A_1X 0x12 ++#define COEFF_DEVICE_B_1X 0x13 ++#define COEFF_DEVICE_C_1X 0x14 ++#define COEFF_DEVICE_D_1X 0x15 ++#define PRE_DEVICE_A_1X 0x22 ++#define PRE_DEVICE_B_1X 0x23 ++#define PRE_DEVICE_C_1X 0x24 ++#define PRE_DEVICE_D_1X 0x25 ++#define PRE_SOFTWARE_RESET_DEVICE_A 0x41 ++#define PRE_SOFTWARE_RESET_DEVICE_B 0x42 ++#define PRE_SOFTWARE_RESET_DEVICE_C 0x43 ++#define PRE_SOFTWARE_RESET_DEVICE_D 0x44 ++#define POST_SOFTWARE_RESET_DEVICE_A 0x45 ++#define POST_SOFTWARE_RESET_DEVICE_B 0x46 ++#define POST_SOFTWARE_RESET_DEVICE_C 0x47 ++#define POST_SOFTWARE_RESET_DEVICE_D 0x48 ++ ++struct tas_crc { ++ unsigned char offset; ++ unsigned char len; ++}; ++ ++struct blktyp_devidx_map { ++ unsigned char blktyp; ++ unsigned char dev_idx; ++}; ++ ++/* fixed m68k compiling issue: mapping table can save code field */ ++static const struct blktyp_devidx_map ppc3_tas2781_mapping_table[] = { ++ { MAIN_ALL_DEVICES_1X, 0x80 }, ++ { MAIN_DEVICE_A_1X, 0x81 }, ++ { COEFF_DEVICE_A_1X, 0x81 }, ++ { PRE_DEVICE_A_1X, 0x81 }, ++ { PRE_SOFTWARE_RESET_DEVICE_A, 0xC1 }, ++ { POST_SOFTWARE_RESET_DEVICE_A, 0xC1 }, ++ { MAIN_DEVICE_B_1X, 0x82 }, ++ { COEFF_DEVICE_B_1X, 0x82 }, ++ { PRE_DEVICE_B_1X, 0x82 }, ++ { PRE_SOFTWARE_RESET_DEVICE_B, 0xC2 }, ++ { POST_SOFTWARE_RESET_DEVICE_B, 0xC2 }, ++ { MAIN_DEVICE_C_1X, 0x83 }, ++ { COEFF_DEVICE_C_1X, 0x83 }, ++ { PRE_DEVICE_C_1X, 0x83 }, ++ { PRE_SOFTWARE_RESET_DEVICE_C, 0xC3 }, ++ { POST_SOFTWARE_RESET_DEVICE_C, 0xC3 }, ++ { MAIN_DEVICE_D_1X, 0x84 }, ++ { COEFF_DEVICE_D_1X, 0x84 }, ++ { PRE_DEVICE_D_1X, 0x84 }, ++ { PRE_SOFTWARE_RESET_DEVICE_D, 0xC4 }, ++ { POST_SOFTWARE_RESET_DEVICE_D, 0xC4 }, ++}; ++ ++static const struct blktyp_devidx_map ppc3_mapping_table[] = { ++ { MAIN_ALL_DEVICES_1X, 0x80 }, ++ { MAIN_DEVICE_A_1X, 0x81 }, ++ { COEFF_DEVICE_A_1X, 0xC1 }, ++ { PRE_DEVICE_A_1X, 0xC1 }, ++ { MAIN_DEVICE_B_1X, 0x82 }, ++ { COEFF_DEVICE_B_1X, 0xC2 }, ++ { PRE_DEVICE_B_1X, 0xC2 }, ++ { MAIN_DEVICE_C_1X, 0x83 }, ++ { COEFF_DEVICE_C_1X, 0xC3 }, ++ { PRE_DEVICE_C_1X, 0xC3 }, ++ { MAIN_DEVICE_D_1X, 0x84 }, ++ { COEFF_DEVICE_D_1X, 0xC4 }, ++ { PRE_DEVICE_D_1X, 0xC4 }, ++}; ++ ++static const struct blktyp_devidx_map non_ppc3_mapping_table[] = { ++ { MAIN_ALL_DEVICES, 0x80 }, ++ { MAIN_DEVICE_A, 0x81 }, ++ { COEFF_DEVICE_A, 0xC1 }, ++ { PRE_DEVICE_A, 0xC1 }, ++ { MAIN_DEVICE_B, 0x82 }, ++ { COEFF_DEVICE_B, 0xC2 }, ++ { PRE_DEVICE_B, 0xC2 }, ++ { MAIN_DEVICE_C, 0x83 }, ++ { COEFF_DEVICE_C, 0xC3 }, ++ { PRE_DEVICE_C, 0xC3 }, ++ { MAIN_DEVICE_D, 0x84 }, ++ { COEFF_DEVICE_D, 0xC4 }, ++ { PRE_DEVICE_D, 0xC4 }, ++}; ++ ++/* ++ * Device support different configurations for different scene, ++ * like voice, music, calibration, was write in regbin file. ++ * Will be stored into tas_priv after regbin was loaded. ++ */ ++static struct tasdevice_config_info *tasdevice_add_config( ++ struct tasdevice_priv *tas_priv, unsigned char *config_data, ++ unsigned int config_size, int *status) ++{ ++ struct tasdevice_config_info *cfg_info; ++ struct tasdev_blk_data **bk_da; ++ unsigned int config_offset = 0; ++ unsigned int i; ++ ++ /* ++ * In most projects are many audio cases, such as music, handfree, ++ * receiver, games, audio-to-haptics, PMIC record, bypass mode, ++ * portrait, landscape, etc. Even in multiple audios, one or ++ * two of the chips will work for the special case, such as ++ * ultrasonic application. In order to support these variable-numbers ++ * of audio cases, flexible configs have been introduced in the ++ * DSP firmware. ++ */ ++ cfg_info = kzalloc(sizeof(*cfg_info), GFP_KERNEL); ++ if (!cfg_info) { ++ *status = -ENOMEM; ++ return NULL; ++ } ++ ++ if (tas_priv->rcabin.fw_hdr.binary_version_num >= 0x105) { ++ if ((config_offset + 64) > config_size) { ++ *status = -EINVAL; ++ dev_err(tas_priv->dev, "add conf: Out of boundary\n"); ++ goto config_err; ++ } ++ config_offset += 64; ++ } ++ ++ if ((config_offset + 4) > config_size) { ++ *status = -EINVAL; ++ dev_err(tas_priv->dev, "add config: Out of boundary\n"); ++ goto config_err; ++ } ++ ++ /* ++ * convert data[offset], data[offset + 1], data[offset + 2] and ++ * data[offset + 3] into host ++ */ ++ cfg_info->nblocks = get_unaligned_be32(&config_data[config_offset]); ++ config_offset += 4; ++ ++ /* ++ * Several kinds of dsp/algorithm firmwares can run on tas2781, ++ * the number and size of blk are not fixed and different among ++ * these firmwares. ++ */ ++ bk_da = cfg_info->blk_data = kcalloc(cfg_info->nblocks, ++ sizeof(*bk_da), GFP_KERNEL); ++ if (!bk_da) { ++ *status = -ENOMEM; ++ goto config_err; ++ } ++ cfg_info->real_nblocks = 0; ++ for (i = 0; i < cfg_info->nblocks; i++) { ++ if (config_offset + 12 > config_size) { ++ *status = -EINVAL; ++ dev_err(tas_priv->dev, ++ "%s: Out of boundary: i = %d nblocks = %u!\n", ++ __func__, i, cfg_info->nblocks); ++ goto block_err; ++ } ++ bk_da[i] = kzalloc(sizeof(*bk_da[i]), GFP_KERNEL); ++ if (!bk_da[i]) { ++ *status = -ENOMEM; ++ goto block_err; ++ } ++ ++ bk_da[i]->dev_idx = config_data[config_offset]; ++ config_offset++; ++ ++ bk_da[i]->block_type = config_data[config_offset]; ++ config_offset++; ++ ++ bk_da[i]->yram_checksum = ++ get_unaligned_be16(&config_data[config_offset]); ++ config_offset += 2; ++ bk_da[i]->block_size = ++ get_unaligned_be32(&config_data[config_offset]); ++ config_offset += 4; ++ ++ bk_da[i]->n_subblks = ++ get_unaligned_be32(&config_data[config_offset]); ++ ++ config_offset += 4; ++ ++ if (config_offset + bk_da[i]->block_size > config_size) { ++ *status = -EINVAL; ++ dev_err(tas_priv->dev, ++ "%s: Out of boundary: i = %d blks = %u!\n", ++ __func__, i, cfg_info->nblocks); ++ goto block_err; ++ } ++ /* instead of kzalloc+memcpy */ ++ bk_da[i]->regdata = kmemdup(&config_data[config_offset], ++ bk_da[i]->block_size, GFP_KERNEL); ++ if (!bk_da[i]->regdata) { ++ *status = -ENOMEM; ++ i++; ++ goto block_err; ++ } ++ ++ config_offset += bk_da[i]->block_size; ++ cfg_info->real_nblocks += 1; ++ } ++ ++ return cfg_info; ++block_err: ++ for (int j = 0; j < i; j++) ++ kfree(bk_da[j]); ++ kfree(bk_da); ++config_err: ++ kfree(cfg_info); ++ return NULL; ++} ++ ++/* Regbin file parser function. */ ++int tasdevice_spi_rca_parser(void *context, const struct firmware *fmw) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ struct tasdevice_config_info **cfg_info; ++ struct tasdevice_rca_hdr *fw_hdr; ++ struct tasdevice_rca *rca; ++ unsigned int total_config_sz = 0; ++ int offset = 0, ret = 0, i; ++ unsigned char *buf; ++ ++ rca = &tas_priv->rcabin; ++ fw_hdr = &rca->fw_hdr; ++ if (!fmw || !fmw->data) { ++ dev_err(tas_priv->dev, "Failed to read %s\n", ++ tas_priv->rca_binaryname); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -EINVAL; ++ } ++ buf = (unsigned char *)fmw->data; ++ fw_hdr->img_sz = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ if (fw_hdr->img_sz != fmw->size) { ++ dev_err(tas_priv->dev, ++ "File size not match, %d %u", (int)fmw->size, ++ fw_hdr->img_sz); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -EINVAL; ++ } ++ ++ fw_hdr->checksum = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ fw_hdr->binary_version_num = get_unaligned_be32(&buf[offset]); ++ if (fw_hdr->binary_version_num < 0x103) { ++ dev_err(tas_priv->dev, "File version 0x%04x is too low", ++ fw_hdr->binary_version_num); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -EINVAL; ++ } ++ offset += 4; ++ fw_hdr->drv_fw_version = get_unaligned_be32(&buf[offset]); ++ offset += 8; ++ fw_hdr->plat_type = buf[offset++]; ++ fw_hdr->dev_family = buf[offset++]; ++ fw_hdr->reserve = buf[offset++]; ++ fw_hdr->ndev = buf[offset++]; ++ if (offset + TASDEVICE_DEVICE_SUM > fw_hdr->img_sz) { ++ dev_err(tas_priv->dev, "rca_ready: Out of boundary!\n"); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < TASDEVICE_DEVICE_SUM; i++, offset++) ++ fw_hdr->devs[i] = buf[offset]; ++ ++ fw_hdr->nconfig = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ ++ for (i = 0; i < TASDEVICE_CONFIG_SUM; i++) { ++ fw_hdr->config_size[i] = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ total_config_sz += fw_hdr->config_size[i]; ++ } ++ ++ if (fw_hdr->img_sz - total_config_sz != (unsigned int)offset) { ++ dev_err(tas_priv->dev, "Bin file err %d - %d != %d!\n", ++ fw_hdr->img_sz, total_config_sz, (int)offset); ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -EINVAL; ++ } ++ ++ cfg_info = kcalloc(fw_hdr->nconfig, sizeof(*cfg_info), GFP_KERNEL); ++ if (!cfg_info) { ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return -ENOMEM; ++ } ++ rca->cfg_info = cfg_info; ++ rca->ncfgs = 0; ++ for (i = 0; i < (int)fw_hdr->nconfig; i++) { ++ rca->ncfgs += 1; ++ cfg_info[i] = tasdevice_add_config(tas_priv, &buf[offset], ++ fw_hdr->config_size[i], &ret); ++ if (ret) { ++ tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL; ++ return ret; ++ } ++ offset += (int)fw_hdr->config_size[i]; ++ } ++ ++ return ret; ++} ++ ++/* fixed m68k compiling issue: mapping table can save code field */ ++static unsigned char map_dev_idx(struct tasdevice_fw *tas_fmw, ++ struct tasdev_blk *block) ++{ ++ struct blktyp_devidx_map *p = ++ (struct blktyp_devidx_map *)non_ppc3_mapping_table; ++ struct tasdevice_dspfw_hdr *fw_hdr = &tas_fmw->fw_hdr; ++ struct tasdevice_fw_fixed_hdr *fw_fixed_hdr = &fw_hdr->fixed_hdr; ++ int i, n = ARRAY_SIZE(non_ppc3_mapping_table); ++ unsigned char dev_idx = 0; ++ ++ if (fw_fixed_hdr->ppcver >= PPC3_VERSION_TAS2781) { ++ p = (struct blktyp_devidx_map *)ppc3_tas2781_mapping_table; ++ n = ARRAY_SIZE(ppc3_tas2781_mapping_table); ++ } else if (fw_fixed_hdr->ppcver >= PPC3_VERSION) { ++ p = (struct blktyp_devidx_map *)ppc3_mapping_table; ++ n = ARRAY_SIZE(ppc3_mapping_table); ++ } ++ ++ for (i = 0; i < n; i++) { ++ if (block->type == p[i].blktyp) { ++ dev_idx = p[i].dev_idx; ++ break; ++ } ++ } ++ ++ return dev_idx; ++} ++ ++/* Block parser function. */ ++static int fw_parse_block_data_kernel(struct tasdevice_fw *tas_fmw, ++ struct tasdev_blk *block, const struct firmware *fmw, int offset) ++{ ++ const unsigned char *data = fmw->data; ++ ++ if (offset + 16 > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Convert data[offset], data[offset + 1], data[offset + 2] and ++ * data[offset + 3] into host. ++ */ ++ block->type = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ ++ block->is_pchksum_present = data[offset++]; ++ block->pchksum = data[offset++]; ++ block->is_ychksum_present = data[offset++]; ++ block->ychksum = data[offset++]; ++ block->blk_size = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ block->nr_subblocks = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ ++ /* ++ * Fixed m68k compiling issue: ++ * 1. mapping table can save code field. ++ * 2. storing the dev_idx as a member of block can reduce unnecessary ++ * time and system resource comsumption of dev_idx mapping every ++ * time the block data writing to the dsp. ++ */ ++ block->dev_idx = map_dev_idx(tas_fmw, block); ++ ++ if (offset + block->blk_size > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: nSublocks error\n", __func__); ++ return -EINVAL; ++ } ++ /* instead of kzalloc+memcpy */ ++ block->data = kmemdup(&data[offset], block->blk_size, GFP_KERNEL); ++ if (!block->data) ++ return -ENOMEM; ++ ++ offset += block->blk_size; ++ ++ return offset; ++} ++ ++/* Data of block parser function. */ ++static int fw_parse_data_kernel(struct tasdevice_fw *tas_fmw, ++ struct tasdevice_data *img_data, const struct firmware *fmw, ++ int offset) ++{ ++ const unsigned char *data = fmw->data; ++ struct tasdev_blk *blk; ++ unsigned int i; ++ ++ if (offset + 4 > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ img_data->nr_blk = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ ++ img_data->dev_blks = kcalloc(img_data->nr_blk, ++ sizeof(struct tasdev_blk), GFP_KERNEL); ++ if (!img_data->dev_blks) ++ return -ENOMEM; ++ ++ for (i = 0; i < img_data->nr_blk; i++) { ++ blk = &img_data->dev_blks[i]; ++ offset = fw_parse_block_data_kernel( ++ tas_fmw, blk, fmw, offset); ++ if (offset < 0) { ++ kfree(img_data->dev_blks); ++ return -EINVAL; ++ } ++ } ++ ++ return offset; ++} ++ ++/* Data of DSP program parser function. */ ++static int fw_parse_program_data_kernel( ++ struct tasdevice_priv *tas_priv, struct tasdevice_fw *tas_fmw, ++ const struct firmware *fmw, int offset) ++{ ++ struct tasdevice_prog *program; ++ unsigned int i; ++ ++ for (i = 0; i < tas_fmw->nr_programs; i++) { ++ program = &tas_fmw->programs[i]; ++ if (offset + 72 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: mpName error\n", __func__); ++ return -EINVAL; ++ } ++ /* skip 72 unused byts */ ++ offset += 72; ++ ++ offset = fw_parse_data_kernel(tas_fmw, &program->dev_data, ++ fmw, offset); ++ if (offset < 0) ++ break; ++ } ++ ++ return offset; ++} ++ ++/* Data of DSP configurations parser function. */ ++static int fw_parse_configuration_data_kernel(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset) ++{ ++ const unsigned char *data = fmw->data; ++ struct tasdevice_config *config; ++ unsigned int i; ++ ++ for (i = 0; i < tas_fmw->nr_configurations; i++) { ++ config = &tas_fmw->configs[i]; ++ if (offset + 80 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: mpName error\n", __func__); ++ return -EINVAL; ++ } ++ memcpy(config->name, &data[offset], 64); ++ /* skip extra 16 bytes */ ++ offset += 80; ++ ++ offset = fw_parse_data_kernel(tas_fmw, &config->dev_data, ++ fmw, offset); ++ if (offset < 0) ++ break; ++ } ++ ++ return offset; ++} ++ ++/* DSP firmware file header parser function for early PPC3 firmware binary. */ ++static int fw_parse_variable_header_kernel(struct tasdevice_priv *tas_priv, ++ const struct firmware *fmw, int offset) ++{ ++ struct tasdevice_fw *tas_fmw = tas_priv->fmw; ++ struct tasdevice_dspfw_hdr *fw_hdr = &tas_fmw->fw_hdr; ++ struct tasdevice_config *config; ++ struct tasdevice_prog *program; ++ const unsigned char *buf = fmw->data; ++ unsigned short max_confs; ++ unsigned int i; ++ ++ if (offset + 12 + 4 * TASDEVICE_MAXPROGRAM_NUM_KERNEL > fmw->size) { ++ dev_err(tas_priv->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ fw_hdr->device_family = get_unaligned_be16(&buf[offset]); ++ if (fw_hdr->device_family != 0) { ++ dev_err(tas_priv->dev, "%s:not TAS device\n", __func__); ++ return -EINVAL; ++ } ++ offset += 2; ++ fw_hdr->device = get_unaligned_be16(&buf[offset]); ++ if (fw_hdr->device >= TASDEVICE_DSP_TAS_MAX_DEVICE || ++ fw_hdr->device == 6) { ++ dev_err(tas_priv->dev, "Unsupported dev %d\n", fw_hdr->device); ++ return -EINVAL; ++ } ++ offset += 2; ++ ++ tas_fmw->nr_programs = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ ++ if (tas_fmw->nr_programs == 0 || ++ tas_fmw->nr_programs > TASDEVICE_MAXPROGRAM_NUM_KERNEL) { ++ dev_err(tas_priv->dev, "mnPrograms is invalid\n"); ++ return -EINVAL; ++ } ++ ++ tas_fmw->programs = kcalloc(tas_fmw->nr_programs, ++ sizeof(*tas_fmw->programs), GFP_KERNEL); ++ if (!tas_fmw->programs) ++ return -ENOMEM; ++ ++ for (i = 0; i < tas_fmw->nr_programs; i++) { ++ program = &tas_fmw->programs[i]; ++ program->prog_size = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ } ++ ++ /* Skip the unused prog_size */ ++ offset += 4 * (TASDEVICE_MAXPROGRAM_NUM_KERNEL - tas_fmw->nr_programs); ++ ++ tas_fmw->nr_configurations = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ ++ /* ++ * The max number of config in firmware greater than 4 pieces of ++ * tas2781s is different from the one lower than 4 pieces of ++ * tas2781s. ++ */ ++ max_confs = TASDEVICE_MAXCONFIG_NUM_KERNEL; ++ if (tas_fmw->nr_configurations == 0 || ++ tas_fmw->nr_configurations > max_confs) { ++ dev_err(tas_priv->dev, "%s: Conf is invalid\n", __func__); ++ kfree(tas_fmw->programs); ++ return -EINVAL; ++ } ++ ++ if (offset + 4 * max_confs > fmw->size) { ++ dev_err(tas_priv->dev, "%s: mpConfigurations err\n", __func__); ++ kfree(tas_fmw->programs); ++ return -EINVAL; ++ } ++ ++ tas_fmw->configs = kcalloc(tas_fmw->nr_configurations, ++ sizeof(*tas_fmw->configs), GFP_KERNEL); ++ if (!tas_fmw->configs) { ++ kfree(tas_fmw->programs); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < tas_fmw->nr_programs; i++) { ++ config = &tas_fmw->configs[i]; ++ config->cfg_size = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ } ++ ++ /* Skip the unused configs */ ++ offset += 4 * (max_confs - tas_fmw->nr_programs); ++ ++ return offset; ++} ++ ++/* ++ * In sub-block data, have three type sub-block: ++ * 1. Single byte write. ++ * 2. Multi-byte write. ++ * 3. Delay. ++ * 4. Bits update. ++ * This function perform single byte write to device. ++ */ ++static int tasdevice_single_byte_wr(void *context, int dev_idx, ++ unsigned char *data, int sublocksize) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ unsigned short len = get_unaligned_be16(&data[2]); ++ int i, subblk_offset, rc; ++ ++ subblk_offset = 4; ++ if (subblk_offset + 4 * len > sublocksize) { ++ dev_err(tas_priv->dev, "process_block: Out of boundary\n"); ++ return 0; ++ } ++ ++ for (i = 0; i < len; i++) { ++ if (dev_idx == (tas_priv->index + 1) || dev_idx == 0) { ++ rc = tasdevice_spi_dev_write(tas_priv, ++ TASDEVICE_REG(data[subblk_offset], ++ data[subblk_offset + 1], ++ data[subblk_offset + 2]), ++ data[subblk_offset + 3]); ++ if (rc < 0) { ++ dev_err(tas_priv->dev, ++ "process_block: single write error\n"); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ } ++ subblk_offset += 4; ++ } ++ ++ return subblk_offset; ++} ++ ++/* ++ * In sub-block data, have three type sub-block: ++ * 1. Single byte write. ++ * 2. Multi-byte write. ++ * 3. Delay. ++ * 4. Bits update. ++ * This function perform multi-write to device. ++ */ ++static int tasdevice_burst_wr(void *context, int dev_idx, unsigned char *data, ++ int sublocksize) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ unsigned short len = get_unaligned_be16(&data[2]); ++ int subblk_offset, rc; ++ ++ subblk_offset = 4; ++ if (subblk_offset + 4 + len > sublocksize) { ++ dev_err(tas_priv->dev, "%s: BST Out of boundary\n", __func__); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ if (len % 4) { ++ dev_err(tas_priv->dev, "%s:Bst-len(%u)not div by 4\n", ++ __func__, len); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ ++ if (dev_idx == (tas_priv->index + 1) || dev_idx == 0) { ++ rc = tasdevice_spi_dev_bulk_write(tas_priv, ++ TASDEVICE_REG(data[subblk_offset], ++ data[subblk_offset + 1], ++ data[subblk_offset + 2]), ++ &data[subblk_offset + 4], len); ++ if (rc < 0) { ++ dev_err(tas_priv->dev, "%s: bulk_write error = %d\n", ++ __func__, rc); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ } ++ subblk_offset += (len + 4); ++ ++ return subblk_offset; ++} ++ ++/* Just delay for ms.*/ ++static int tasdevice_delay(void *context, int dev_idx, unsigned char *data, ++ int sublocksize) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ unsigned int sleep_time, subblk_offset = 2; ++ ++ if (subblk_offset + 2 > sublocksize) { ++ dev_err(tas_priv->dev, "%s: delay Out of boundary\n", ++ __func__); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ if (dev_idx == (tas_priv->index + 1) || dev_idx == 0) { ++ sleep_time = get_unaligned_be16(&data[2]) * 1000; ++ fsleep(sleep_time); ++ } ++ subblk_offset += 2; ++ ++ return subblk_offset; ++} ++ ++/* ++ * In sub-block data, have three type sub-block: ++ * 1. Single byte write. ++ * 2. Multi-byte write. ++ * 3. Delay. ++ * 4. Bits update. ++ * This function perform bits update. ++ */ ++static int tasdevice_field_wr(void *context, int dev_idx, unsigned char *data, ++ int sublocksize) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ int rc, subblk_offset = 2; ++ ++ if (subblk_offset + 6 > sublocksize) { ++ dev_err(tas_priv->dev, "%s: bit write Out of boundary\n", ++ __func__); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ if (dev_idx == (tas_priv->index + 1) || dev_idx == 0) { ++ rc = tasdevice_spi_dev_update_bits(tas_priv, ++ TASDEVICE_REG(data[subblk_offset + 2], ++ data[subblk_offset + 3], ++ data[subblk_offset + 4]), ++ data[subblk_offset + 1], ++ data[subblk_offset + 5]); ++ if (rc < 0) { ++ dev_err(tas_priv->dev, "%s: update_bits error = %d\n", ++ __func__, rc); ++ subblk_offset |= OFFSET_ERROR_BIT; ++ } ++ } ++ subblk_offset += 6; ++ ++ return subblk_offset; ++} ++ ++/* Data block process function. */ ++static int tasdevice_process_block(void *context, unsigned char *data, ++ unsigned char dev_idx, int sublocksize) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ int blktyp = dev_idx & 0xC0, subblk_offset; ++ unsigned char subblk_typ = data[1]; ++ ++ switch (subblk_typ) { ++ case TASDEVICE_CMD_SING_W: ++ subblk_offset = tasdevice_single_byte_wr(tas_priv, ++ dev_idx & 0x4f, data, sublocksize); ++ break; ++ case TASDEVICE_CMD_BURST: ++ subblk_offset = tasdevice_burst_wr(tas_priv, ++ dev_idx & 0x4f, data, sublocksize); ++ break; ++ case TASDEVICE_CMD_DELAY: ++ subblk_offset = tasdevice_delay(tas_priv, ++ dev_idx & 0x4f, data, sublocksize); ++ break; ++ case TASDEVICE_CMD_FIELD_W: ++ subblk_offset = tasdevice_field_wr(tas_priv, ++ dev_idx & 0x4f, data, sublocksize); ++ break; ++ default: ++ subblk_offset = 2; ++ break; ++ } ++ if (((subblk_offset & OFFSET_ERROR_BIT) != 0) && blktyp != 0) { ++ if (blktyp == 0x80) { ++ tas_priv->cur_prog = -1; ++ tas_priv->cur_conf = -1; ++ } else ++ tas_priv->cur_conf = -1; ++ } ++ subblk_offset &= ~OFFSET_ERROR_BIT; ++ ++ return subblk_offset; ++} ++ ++/* ++ * Device support different configurations for different scene, ++ * this function was used for choose different config. ++ */ ++void tasdevice_spi_select_cfg_blk(void *pContext, int conf_no, ++ unsigned char block_type) ++{ ++ struct tasdevice_priv *tas_priv = pContext; ++ struct tasdevice_rca *rca = &tas_priv->rcabin; ++ struct tasdevice_config_info **cfg_info = rca->cfg_info; ++ struct tasdev_blk_data **blk_data; ++ unsigned int j, k; ++ ++ if (conf_no >= rca->ncfgs || conf_no < 0 || !cfg_info) { ++ dev_err(tas_priv->dev, "conf_no should be not more than %u\n", ++ rca->ncfgs); ++ return; ++ } ++ blk_data = cfg_info[conf_no]->blk_data; ++ ++ for (j = 0; j < cfg_info[conf_no]->real_nblocks; j++) { ++ unsigned int length = 0, rc = 0; ++ ++ if (block_type > 5 || block_type < 2) { ++ dev_err(tas_priv->dev, ++ "block_type should be in range from 2 to 5\n"); ++ break; ++ } ++ if (block_type != blk_data[j]->block_type) ++ continue; ++ ++ for (k = 0; k < blk_data[j]->n_subblks; k++) { ++ tas_priv->is_loading = true; ++ ++ rc = tasdevice_process_block(tas_priv, ++ blk_data[j]->regdata + length, ++ blk_data[j]->dev_idx, ++ blk_data[j]->block_size - length); ++ length += rc; ++ if (blk_data[j]->block_size < length) { ++ dev_err(tas_priv->dev, ++ "%s: %u %u out of boundary\n", ++ __func__, length, ++ blk_data[j]->block_size); ++ break; ++ } ++ } ++ if (length != blk_data[j]->block_size) ++ dev_err(tas_priv->dev, "%s: %u %u size is not same\n", ++ __func__, length, blk_data[j]->block_size); ++ } ++} ++ ++/* Block process function. */ ++static int tasdevice_load_block_kernel( ++ struct tasdevice_priv *tasdevice, struct tasdev_blk *block) ++{ ++ const unsigned int blk_size = block->blk_size; ++ unsigned char *data = block->data; ++ unsigned int i, length; ++ ++ for (i = 0, length = 0; i < block->nr_subblocks; i++) { ++ int rc = tasdevice_process_block(tasdevice, data + length, ++ block->dev_idx, blk_size - length); ++ if (rc < 0) { ++ dev_err(tasdevice->dev, ++ "%s: %u %u sublock write error\n", ++ __func__, length, blk_size); ++ return rc; ++ } ++ length += rc; ++ if (blk_size < length) { ++ dev_err(tasdevice->dev, "%s: %u %u out of boundary\n", ++ __func__, length, blk_size); ++ rc = -ENOMEM; ++ return rc; ++ } ++ } ++ ++ return 0; ++} ++ ++/* DSP firmware file header parser function. */ ++static int fw_parse_variable_hdr(struct tasdevice_priv *tas_priv, ++ struct tasdevice_dspfw_hdr *fw_hdr, ++ const struct firmware *fmw, int offset) ++{ ++ const unsigned char *buf = fmw->data; ++ int len = strlen((char *)&buf[offset]); ++ ++ len++; ++ ++ if (offset + len + 8 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ ++ offset += len; ++ ++ fw_hdr->device_family = get_unaligned_be32(&buf[offset]); ++ if (fw_hdr->device_family != 0) { ++ dev_err(tas_priv->dev, "%s: not TAS device\n", __func__); ++ return -EINVAL; ++ } ++ offset += 4; ++ ++ fw_hdr->device = get_unaligned_be32(&buf[offset]); ++ if (fw_hdr->device >= TASDEVICE_DSP_TAS_MAX_DEVICE || ++ fw_hdr->device == 6) { ++ dev_err(tas_priv->dev, "Unsupported dev %d\n", fw_hdr->device); ++ return -EINVAL; ++ } ++ offset += 4; ++ fw_hdr->ndev = 1; ++ ++ return offset; ++} ++ ++/* DSP firmware file header parser function for size variabled header. */ ++static int fw_parse_variable_header_git(struct tasdevice_priv ++ *tas_priv, const struct firmware *fmw, int offset) ++{ ++ struct tasdevice_fw *tas_fmw = tas_priv->fmw; ++ struct tasdevice_dspfw_hdr *fw_hdr = &tas_fmw->fw_hdr; ++ ++ offset = fw_parse_variable_hdr(tas_priv, fw_hdr, fmw, offset); ++ ++ return offset; ++} ++ ++/* DSP firmware file block parser function. */ ++static int fw_parse_block_data(struct tasdevice_fw *tas_fmw, ++ struct tasdev_blk *block, const struct firmware *fmw, int offset) ++{ ++ unsigned char *data = (unsigned char *)fmw->data; ++ int n; ++ ++ if (offset + 8 > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: Type error\n", __func__); ++ return -EINVAL; ++ } ++ block->type = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ ++ if (tas_fmw->fw_hdr.fixed_hdr.drv_ver >= PPC_DRIVER_CRCCHK) { ++ if (offset + 8 > fmw->size) { ++ dev_err(tas_fmw->dev, "PChkSumPresent error\n"); ++ return -EINVAL; ++ } ++ block->is_pchksum_present = data[offset]; ++ offset++; ++ ++ block->pchksum = data[offset]; ++ offset++; ++ ++ block->is_ychksum_present = data[offset]; ++ offset++; ++ ++ block->ychksum = data[offset]; ++ offset++; ++ } else { ++ block->is_pchksum_present = 0; ++ block->is_ychksum_present = 0; ++ } ++ ++ block->nr_cmds = get_unaligned_be32(&data[offset]); ++ offset += 4; ++ ++ n = block->nr_cmds * 4; ++ if (offset + n > fmw->size) { ++ dev_err(tas_fmw->dev, ++ "%s: File Size(%lu) error offset = %d n = %d\n", ++ __func__, (unsigned long)fmw->size, offset, n); ++ return -EINVAL; ++ } ++ /* instead of kzalloc+memcpy */ ++ block->data = kmemdup(&data[offset], n, GFP_KERNEL); ++ if (!block->data) ++ return -ENOMEM; ++ ++ offset += n; ++ ++ return offset; ++} ++ ++/* ++ * When parsing error occurs, all the memory resource will be released ++ * in the end of tasdevice_rca_ready. ++ */ ++static int fw_parse_data(struct tasdevice_fw *tas_fmw, ++ struct tasdevice_data *img_data, const struct firmware *fmw, ++ int offset) ++{ ++ const unsigned char *data = (unsigned char *)fmw->data; ++ struct tasdev_blk *blk; ++ unsigned int i, n; ++ ++ if (offset + 64 > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: Name error\n", __func__); ++ return -EINVAL; ++ } ++ memcpy(img_data->name, &data[offset], 64); ++ offset += 64; ++ ++ n = strlen((char *)&data[offset]); ++ n++; ++ if (offset + n + 2 > fmw->size) { ++ dev_err(tas_fmw->dev, "%s: Description error\n", __func__); ++ return -EINVAL; ++ } ++ offset += n; ++ img_data->nr_blk = get_unaligned_be16(&data[offset]); ++ offset += 2; ++ ++ img_data->dev_blks = kcalloc(img_data->nr_blk, ++ sizeof(*img_data->dev_blks), GFP_KERNEL); ++ if (!img_data->dev_blks) ++ return -ENOMEM; ++ ++ for (i = 0; i < img_data->nr_blk; i++) { ++ blk = &img_data->dev_blks[i]; ++ offset = fw_parse_block_data(tas_fmw, blk, fmw, offset); ++ if (offset < 0) ++ return -EINVAL; ++ } ++ ++ return offset; ++} ++ ++/* ++ * When parsing error occurs, all the memory resource will be released ++ * in the end of tasdevice_rca_ready. ++ */ ++static int fw_parse_program_data(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset) ++{ ++ unsigned char *buf = (unsigned char *)fmw->data; ++ struct tasdevice_prog *program; ++ int i; ++ ++ if (offset + 2 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ tas_fmw->nr_programs = get_unaligned_be16(&buf[offset]); ++ offset += 2; ++ ++ if (tas_fmw->nr_programs == 0) { ++ /* Not error in calibration Data file, return directly */ ++ dev_dbg(tas_priv->dev, "%s: No Programs data, maybe calbin\n", ++ __func__); ++ return offset; ++ } ++ ++ tas_fmw->programs = ++ kcalloc(tas_fmw->nr_programs, sizeof(*tas_fmw->programs), ++ GFP_KERNEL); ++ if (!tas_fmw->programs) ++ return -ENOMEM; ++ ++ for (i = 0; i < tas_fmw->nr_programs; i++) { ++ int n = 0; ++ ++ program = &tas_fmw->programs[i]; ++ if (offset + 64 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: mpName error\n", __func__); ++ return -EINVAL; ++ } ++ offset += 64; ++ ++ n = strlen((char *)&buf[offset]); ++ /* skip '\0' and 5 unused bytes */ ++ n += 6; ++ if (offset + n > fmw->size) { ++ dev_err(tas_priv->dev, "Description err\n"); ++ return -EINVAL; ++ } ++ ++ offset += n; ++ ++ offset = fw_parse_data(tas_fmw, &program->dev_data, fmw, ++ offset); ++ if (offset < 0) ++ return offset; ++ } ++ ++ return offset; ++} ++ ++/* ++ * When parsing error occurs, all the memory resource will be released ++ * in the end of tasdevice_rca_ready. ++ */ ++static int fw_parse_configuration_data(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset) ++{ ++ unsigned char *data = (unsigned char *)fmw->data; ++ struct tasdevice_config *config; ++ unsigned int i, n; ++ ++ if (offset + 2 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: File Size error\n", __func__); ++ return -EINVAL; ++ } ++ tas_fmw->nr_configurations = get_unaligned_be16(&data[offset]); ++ offset += 2; ++ ++ if (tas_fmw->nr_configurations == 0) { ++ dev_err(tas_priv->dev, "%s: Conf is zero\n", __func__); ++ /* Not error for calibration Data file, return directly */ ++ return offset; ++ } ++ tas_fmw->configs = kcalloc(tas_fmw->nr_configurations, ++ sizeof(*tas_fmw->configs), GFP_KERNEL); ++ if (!tas_fmw->configs) ++ return -ENOMEM; ++ for (i = 0; i < tas_fmw->nr_configurations; i++) { ++ config = &tas_fmw->configs[i]; ++ if (offset + 64 > fmw->size) { ++ dev_err(tas_priv->dev, "File Size err\n"); ++ return -EINVAL; ++ } ++ memcpy(config->name, &data[offset], 64); ++ offset += 64; ++ ++ n = strlen((char *)&data[offset]); ++ n += 15; ++ if (offset + n > fmw->size) { ++ dev_err(tas_priv->dev, "Description err\n"); ++ return -EINVAL; ++ } ++ offset += n; ++ offset = fw_parse_data(tas_fmw, &config->dev_data, ++ fmw, offset); ++ if (offset < 0) ++ break; ++ } ++ ++ return offset; ++} ++ ++/* yram5 page check. */ ++static bool check_inpage_yram_rg(struct tas_crc *cd, ++ unsigned char reg, unsigned char len) ++{ ++ bool in = false; ++ ++ if (reg <= TAS2781_YRAM5_END_REG && ++ reg >= TAS2781_YRAM5_START_REG) { ++ if (reg + len > TAS2781_YRAM5_END_REG) ++ cd->len = TAS2781_YRAM5_END_REG - reg + 1; ++ else ++ cd->len = len; ++ cd->offset = reg; ++ in = true; ++ } else if (reg < TAS2781_YRAM5_START_REG) { ++ if (reg + len > TAS2781_YRAM5_START_REG) { ++ cd->offset = TAS2781_YRAM5_START_REG; ++ cd->len = len - TAS2781_YRAM5_START_REG + reg; ++ in = true; ++ } ++ } ++ ++ return in; ++} ++ ++/* DSP firmware yram block check. */ ++static bool check_inpage_yram_bk1(struct tas_crc *cd, ++ unsigned char page, unsigned char reg, unsigned char len) ++{ ++ bool in = false; ++ ++ if (page == TAS2781_YRAM1_PAGE) { ++ if (reg >= TAS2781_YRAM1_START_REG) { ++ cd->offset = reg; ++ cd->len = len; ++ in = true; ++ } else if (reg + len > TAS2781_YRAM1_START_REG) { ++ cd->offset = TAS2781_YRAM1_START_REG; ++ cd->len = len - TAS2781_YRAM1_START_REG + reg; ++ in = true; ++ } ++ } else if (page == TAS2781_YRAM3_PAGE) { ++ in = check_inpage_yram_rg(cd, reg, len); ++ } ++ ++ return in; ++} ++ ++/* ++ * Return Code: ++ * true -- the registers are in the inpage yram ++ * false -- the registers are NOT in the inpage yram ++ */ ++static bool check_inpage_yram(struct tas_crc *cd, unsigned char book, ++ unsigned char page, unsigned char reg, unsigned char len) ++{ ++ bool in = false; ++ ++ if (book == TAS2781_YRAM_BOOK1) ++ in = check_inpage_yram_bk1(cd, page, reg, len); ++ else if (book == TAS2781_YRAM_BOOK2 && page == TAS2781_YRAM5_PAGE) ++ in = check_inpage_yram_rg(cd, reg, len); ++ ++ return in; ++} ++ ++/* yram4 page check. */ ++static bool check_inblock_yram_bk(struct tas_crc *cd, ++ unsigned char page, unsigned char reg, unsigned char len) ++{ ++ bool in = false; ++ ++ if ((page >= TAS2781_YRAM4_START_PAGE && ++ page <= TAS2781_YRAM4_END_PAGE) || ++ (page >= TAS2781_YRAM2_START_PAGE && ++ page <= TAS2781_YRAM2_END_PAGE)) { ++ if (reg <= TAS2781_YRAM2_END_REG && ++ reg >= TAS2781_YRAM2_START_REG) { ++ cd->offset = reg; ++ cd->len = len; ++ in = true; ++ } else if (reg < TAS2781_YRAM2_START_REG) { ++ if (reg + len - 1 >= TAS2781_YRAM2_START_REG) { ++ cd->offset = TAS2781_YRAM2_START_REG; ++ cd->len = reg + len - TAS2781_YRAM2_START_REG; ++ in = true; ++ } ++ } ++ } ++ ++ return in; ++} ++ ++/* ++ * Return Code: ++ * true -- the registers are in the inblock yram ++ * false -- the registers are NOT in the inblock yram ++ */ ++static bool check_inblock_yram(struct tas_crc *cd, unsigned char book, ++ unsigned char page, unsigned char reg, unsigned char len) ++{ ++ bool in = false; ++ ++ if (book == TAS2781_YRAM_BOOK1 || book == TAS2781_YRAM_BOOK2) ++ in = check_inblock_yram_bk(cd, page, reg, len); ++ ++ return in; ++} ++ ++/* yram page check. */ ++static bool check_yram(struct tas_crc *cd, unsigned char book, ++ unsigned char page, unsigned char reg, unsigned char len) ++{ ++ bool in; ++ ++ in = check_inpage_yram(cd, book, page, reg, len); ++ if (!in) ++ in = check_inblock_yram(cd, book, page, reg, len); ++ ++ return in; ++} ++ ++/* Checksum for data block. */ ++static int tasdev_multibytes_chksum(struct tasdevice_priv *tasdevice, ++ unsigned char book, unsigned char page, ++ unsigned char reg, unsigned int len) ++{ ++ struct tas_crc crc_data; ++ unsigned char crc_chksum = 0; ++ unsigned char nBuf1[128]; ++ int ret = 0, i; ++ bool in; ++ ++ if ((reg + len - 1) > 127) { ++ ret = -EINVAL; ++ dev_err(tasdevice->dev, "firmware error\n"); ++ goto end; ++ } ++ ++ if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (page == TASDEVICE_PAGE_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (reg == TASDEVICE_REG_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (len == 4)) { ++ /* DSP swap command, pass */ ++ ret = 0; ++ goto end; ++ } ++ ++ in = check_yram(&crc_data, book, page, reg, len); ++ if (!in) ++ goto end; ++ ++ if (len == 1) { ++ dev_err(tasdevice->dev, "firmware error\n"); ++ ret = -EINVAL; ++ goto end; ++ } ++ ++ ret = tasdevice_spi_dev_bulk_read(tasdevice, ++ TASDEVICE_REG(book, page, crc_data.offset), ++ nBuf1, crc_data.len); ++ if (ret < 0) ++ goto end; ++ ++ for (i = 0; i < crc_data.len; i++) { ++ if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (page == TASDEVICE_PAGE_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ ((i + crc_data.offset) >= ++ TASDEVICE_REG_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ ((i + crc_data.offset) <= ++ (TASDEVICE_REG_ID(TAS2781_SA_COEFF_SWAP_REG) + 4))) ++ /* DSP swap command, bypass */ ++ continue; ++ else ++ crc_chksum += crc8(tasdevice->crc8_lkp_tbl, &nBuf1[i], ++ 1, 0); ++ } ++ ++ ret = crc_chksum; ++ ++end: ++ return ret; ++} ++ ++/* Checksum for single register. */ ++static int do_singlereg_checksum(struct tasdevice_priv *tasdevice, ++ unsigned char book, unsigned char page, ++ unsigned char reg, unsigned char val) ++{ ++ struct tas_crc crc_data; ++ unsigned int nData1; ++ int ret = 0; ++ bool in; ++ ++ /* DSP swap command, pass */ ++ if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (page == TASDEVICE_PAGE_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (reg >= TASDEVICE_REG_ID(TAS2781_SA_COEFF_SWAP_REG)) && ++ (reg <= (TASDEVICE_REG_ID(TAS2781_SA_COEFF_SWAP_REG) + 4))) ++ return 0; ++ ++ in = check_yram(&crc_data, book, page, reg, 1); ++ if (!in) ++ return 0; ++ ret = tasdevice_spi_dev_read(tasdevice, ++ TASDEVICE_REG(book, page, reg), &nData1); ++ if (ret < 0) ++ return ret; ++ ++ if (nData1 != val) { ++ dev_err(tasdevice->dev, ++ "B[0x%x]P[0x%x]R[0x%x] W[0x%x], R[0x%x]\n", ++ book, page, reg, val, nData1); ++ tasdevice->err_code |= ERROR_YRAM_CRCCHK; ++ return -EAGAIN; ++ } ++ ++ ret = crc8(tasdevice->crc8_lkp_tbl, &val, 1, 0); ++ ++ return ret; ++} ++ ++/* Block type check. */ ++static void set_err_prg_cfg(unsigned int type, struct tasdevice_priv *p) ++{ ++ if ((type == MAIN_ALL_DEVICES) || (type == MAIN_DEVICE_A) || ++ (type == MAIN_DEVICE_B) || (type == MAIN_DEVICE_C) || ++ (type == MAIN_DEVICE_D)) ++ p->cur_prog = -1; ++ else ++ p->cur_conf = -1; ++} ++ ++/* Checksum for data bytes. */ ++static int tasdev_bytes_chksum(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block, unsigned char book, ++ unsigned char page, unsigned char reg, unsigned int len, ++ unsigned char val, unsigned char *crc_chksum) ++{ ++ int ret; ++ ++ if (len > 1) ++ ret = tasdev_multibytes_chksum(tas_priv, book, page, reg, ++ len); ++ else ++ ret = do_singlereg_checksum(tas_priv, book, page, reg, val); ++ ++ if (ret > 0) { ++ *crc_chksum += ret; ++ goto end; ++ } ++ ++ if (ret != -EAGAIN) ++ goto end; ++ ++ block->nr_retry--; ++ if (block->nr_retry > 0) ++ goto end; ++ ++ set_err_prg_cfg(block->type, tas_priv); ++ ++end: ++ return ret; ++} ++ ++/* Multi-data byte write. */ ++static int tasdev_multibytes_wr(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block, unsigned char book, ++ unsigned char page, unsigned char reg, unsigned char *data, ++ unsigned int len, unsigned int *nr_cmds, ++ unsigned char *crc_chksum) ++{ ++ int ret; ++ ++ if (len > 1) { ++ ret = tasdevice_spi_dev_bulk_write(tas_priv, ++ TASDEVICE_REG(book, page, reg), data + 3, len); ++ if (ret < 0) ++ return ret; ++ if (block->is_ychksum_present) ++ ret = tasdev_bytes_chksum(tas_priv, block, ++ book, page, reg, len, 0, crc_chksum); ++ } else { ++ ret = tasdevice_spi_dev_write(tas_priv, ++ TASDEVICE_REG(book, page, reg), data[3]); ++ if (ret < 0) ++ return ret; ++ if (block->is_ychksum_present) ++ ret = tasdev_bytes_chksum(tas_priv, block, book, ++ page, reg, 1, data[3], crc_chksum); ++ } ++ ++ if (!block->is_ychksum_present || ret >= 0) { ++ *nr_cmds += 1; ++ if (len >= 2) ++ *nr_cmds += ((len - 2) / 4) + 1; ++ } ++ ++ return ret; ++} ++ ++/* Checksum for block. */ ++static int tasdev_block_chksum(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block) ++{ ++ unsigned int nr_value; ++ int ret; ++ ++ ret = tasdevice_spi_dev_read(tas_priv, TASDEVICE_CHECKSUM, &nr_value); ++ if (ret < 0) { ++ dev_err(tas_priv->dev, "%s: read error %d.\n", __func__, ret); ++ set_err_prg_cfg(block->type, tas_priv); ++ return ret; ++ } ++ ++ if ((nr_value & 0xff) != block->pchksum) { ++ dev_err(tas_priv->dev, "%s: PChkSum err %d ", __func__, ret); ++ dev_err(tas_priv->dev, "PChkSum = 0x%x, Reg = 0x%x\n", ++ block->pchksum, (nr_value & 0xff)); ++ tas_priv->err_code |= ERROR_PRAM_CRCCHK; ++ ret = -EAGAIN; ++ block->nr_retry--; ++ ++ if (block->nr_retry <= 0) ++ set_err_prg_cfg(block->type, tas_priv); ++ } else { ++ tas_priv->err_code &= ~ERROR_PRAM_CRCCHK; ++ } ++ ++ return ret; ++} ++ ++/* Firmware block load function. */ ++static int tasdev_load_blk(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block) ++{ ++ unsigned int sleep_time, len, nr_cmds; ++ unsigned char offset, book, page, val; ++ unsigned char *data = block->data; ++ unsigned char crc_chksum = 0; ++ int ret = 0; ++ ++ while (block->nr_retry > 0) { ++ if (block->is_pchksum_present) { ++ ret = tasdevice_spi_dev_write(tas_priv, ++ TASDEVICE_CHECKSUM, 0); ++ if (ret < 0) ++ break; ++ } ++ ++ if (block->is_ychksum_present) ++ crc_chksum = 0; ++ ++ nr_cmds = 0; ++ ++ while (nr_cmds < block->nr_cmds) { ++ data = block->data + nr_cmds * 4; ++ ++ book = data[0]; ++ page = data[1]; ++ offset = data[2]; ++ val = data[3]; ++ ++ nr_cmds++; ++ /* Single byte write */ ++ if (offset <= 0x7F) { ++ ret = tasdevice_spi_dev_write(tas_priv, ++ TASDEVICE_REG(book, page, offset), ++ val); ++ if (ret < 0) ++ break; ++ if (block->is_ychksum_present) { ++ ret = tasdev_bytes_chksum(tas_priv, ++ block, book, page, offset, ++ 1, val, &crc_chksum); ++ if (ret < 0) ++ break; ++ } ++ continue; ++ } ++ /* sleep command */ ++ if (offset == 0x81) { ++ /* book -- data[0] page -- data[1] */ ++ sleep_time = ((book << 8) + page)*1000; ++ fsleep(sleep_time); ++ continue; ++ } ++ /* Multiple bytes write */ ++ if (offset == 0x85) { ++ data += 4; ++ len = (book << 8) + page; ++ book = data[0]; ++ page = data[1]; ++ offset = data[2]; ++ ret = tasdev_multibytes_wr(tas_priv, ++ block, book, page, offset, data, ++ len, &nr_cmds, &crc_chksum); ++ if (ret < 0) ++ break; ++ } ++ } ++ if (ret == -EAGAIN) { ++ if (block->nr_retry > 0) ++ continue; ++ } else if (ret < 0) { ++ /* err in current device, skip it */ ++ break; ++ } ++ ++ if (block->is_pchksum_present) { ++ ret = tasdev_block_chksum(tas_priv, block); ++ if (ret == -EAGAIN) { ++ if (block->nr_retry > 0) ++ continue; ++ } else if (ret < 0) { ++ /* err in current device, skip it */ ++ break; ++ } ++ } ++ ++ if (block->is_ychksum_present) { ++ /* TBD, open it when FW ready */ ++ dev_err(tas_priv->dev, ++ "Blk YChkSum: FW = 0x%x, YCRC = 0x%x\n", ++ block->ychksum, crc_chksum); ++ ++ tas_priv->err_code &= ++ ~ERROR_YRAM_CRCCHK; ++ ret = 0; ++ } ++ /* skip current blk */ ++ break; ++ } ++ ++ return ret; ++} ++ ++/* Firmware block load function. */ ++static int tasdevice_load_block(struct tasdevice_priv *tas_priv, ++ struct tasdev_blk *block) ++{ ++ int ret = 0; ++ ++ block->nr_retry = 6; ++ if (tas_priv->is_loading == false) ++ return 0; ++ ret = tasdev_load_blk(tas_priv, block); ++ if (ret < 0) ++ dev_err(tas_priv->dev, "Blk (%d) load error\n", block->type); ++ ++ return ret; ++} ++ ++/* ++ * Select firmware binary parser & load callback functions by ppc3 version ++ * and firmware binary version. ++ */ ++static int dspfw_default_callback(struct tasdevice_priv *tas_priv, ++ unsigned int drv_ver, unsigned int ppcver) ++{ ++ int rc = 0; ++ ++ if (drv_ver == 0x100) { ++ if (ppcver >= PPC3_VERSION) { ++ tas_priv->fw_parse_variable_header = ++ fw_parse_variable_header_kernel; ++ tas_priv->fw_parse_program_data = ++ fw_parse_program_data_kernel; ++ tas_priv->fw_parse_configuration_data = ++ fw_parse_configuration_data_kernel; ++ tas_priv->tasdevice_load_block = ++ tasdevice_load_block_kernel; ++ } else if (ppcver == 0x00) { ++ tas_priv->fw_parse_variable_header = ++ fw_parse_variable_header_git; ++ tas_priv->fw_parse_program_data = ++ fw_parse_program_data; ++ tas_priv->fw_parse_configuration_data = ++ fw_parse_configuration_data; ++ tas_priv->tasdevice_load_block = ++ tasdevice_load_block; ++ } else { ++ dev_err(tas_priv->dev, ++ "Wrong PPCVer :0x%08x\n", ppcver); ++ rc = -EINVAL; ++ } ++ } else { ++ dev_err(tas_priv->dev, "Wrong DrvVer : 0x%02x\n", drv_ver); ++ rc = -EINVAL; ++ } ++ ++ return rc; ++} ++ ++/* DSP firmware binary file header parser function. */ ++static int fw_parse_header(struct tasdevice_priv *tas_priv, ++ struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset) ++{ ++ struct tasdevice_dspfw_hdr *fw_hdr = &tas_fmw->fw_hdr; ++ struct tasdevice_fw_fixed_hdr *fw_fixed_hdr = &fw_hdr->fixed_hdr; ++ static const unsigned char magic_number[] = {0x35, 0x35, 0x35, 0x32, }; ++ const unsigned char *buf = (unsigned char *)fmw->data; ++ ++ if (offset + 92 > fmw->size) { ++ dev_err(tas_priv->dev, "%s: File Size error\n", __func__); ++ offset = -EINVAL; ++ goto out; ++ } ++ if (memcmp(&buf[offset], magic_number, 4)) { ++ dev_err(tas_priv->dev, "%s: Magic num NOT match\n", __func__); ++ offset = -EINVAL; ++ goto out; ++ } ++ offset += 4; ++ ++ /* ++ * Convert data[offset], data[offset + 1], data[offset + 2] and ++ * data[offset + 3] into host ++ */ ++ fw_fixed_hdr->fwsize = get_unaligned_be32(&buf[offset]); ++ offset += 4; ++ if (fw_fixed_hdr->fwsize != fmw->size) { ++ dev_err(tas_priv->dev, "File size not match, %lu %u", ++ (unsigned long)fmw->size, fw_fixed_hdr->fwsize); ++ offset = -EINVAL; ++ goto out; ++ } ++ offset += 4; ++ fw_fixed_hdr->ppcver = get_unaligned_be32(&buf[offset]); ++ offset += 8; ++ fw_fixed_hdr->drv_ver = get_unaligned_be32(&buf[offset]); ++ offset += 72; ++ ++out: ++ return offset; ++} ++ ++/* DSP firmware binary file parser function. */ ++static int tasdevice_dspfw_ready(const struct firmware *fmw, void *context) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ struct tasdevice_fw_fixed_hdr *fw_fixed_hdr; ++ struct tasdevice_fw *tas_fmw; ++ int offset = 0, ret = 0; ++ ++ if (!fmw || !fmw->data) { ++ dev_err(tas_priv->dev, "%s: Failed to read firmware %s\n", ++ __func__, tas_priv->coef_binaryname); ++ return -EINVAL; ++ } ++ ++ tas_priv->fmw = kzalloc(sizeof(*tas_priv->fmw), GFP_KERNEL); ++ if (!tas_priv->fmw) ++ return -ENOMEM; ++ tas_fmw = tas_priv->fmw; ++ tas_fmw->dev = tas_priv->dev; ++ offset = fw_parse_header(tas_priv, tas_fmw, fmw, offset); ++ ++ if (offset == -EINVAL) ++ return -EINVAL; ++ ++ fw_fixed_hdr = &tas_fmw->fw_hdr.fixed_hdr; ++ /* Support different versions of firmware */ ++ switch (fw_fixed_hdr->drv_ver) { ++ case 0x301: ++ case 0x302: ++ case 0x502: ++ case 0x503: ++ tas_priv->fw_parse_variable_header = ++ fw_parse_variable_header_kernel; ++ tas_priv->fw_parse_program_data = ++ fw_parse_program_data_kernel; ++ tas_priv->fw_parse_configuration_data = ++ fw_parse_configuration_data_kernel; ++ tas_priv->tasdevice_load_block = ++ tasdevice_load_block_kernel; ++ break; ++ case 0x202: ++ case 0x400: ++ tas_priv->fw_parse_variable_header = ++ fw_parse_variable_header_git; ++ tas_priv->fw_parse_program_data = ++ fw_parse_program_data; ++ tas_priv->fw_parse_configuration_data = ++ fw_parse_configuration_data; ++ tas_priv->tasdevice_load_block = ++ tasdevice_load_block; ++ break; ++ default: ++ ret = dspfw_default_callback(tas_priv, ++ fw_fixed_hdr->drv_ver, fw_fixed_hdr->ppcver); ++ if (ret) ++ return ret; ++ break; ++ } ++ ++ offset = tas_priv->fw_parse_variable_header(tas_priv, fmw, offset); ++ if (offset < 0) ++ return offset; ++ ++ offset = tas_priv->fw_parse_program_data(tas_priv, tas_fmw, fmw, ++ offset); ++ if (offset < 0) ++ return offset; ++ ++ offset = tas_priv->fw_parse_configuration_data(tas_priv, ++ tas_fmw, fmw, offset); ++ if (offset < 0) ++ ret = offset; ++ ++ return ret; ++} ++ ++/* DSP firmware binary file parser function. */ ++int tasdevice_spi_dsp_parser(void *context) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ const struct firmware *fw_entry; ++ int ret; ++ ++ ret = request_firmware(&fw_entry, tas_priv->coef_binaryname, ++ tas_priv->dev); ++ if (ret) { ++ dev_err(tas_priv->dev, "%s: load %s error\n", __func__, ++ tas_priv->coef_binaryname); ++ return ret; ++ } ++ ++ ret = tasdevice_dspfw_ready(fw_entry, tas_priv); ++ release_firmware(fw_entry); ++ fw_entry = NULL; ++ ++ return ret; ++} ++ ++/* DSP firmware program block data remove function. */ ++static void tasdev_dsp_prog_blk_remove(struct tasdevice_prog *prog) ++{ ++ struct tasdevice_data *tas_dt; ++ struct tasdev_blk *blk; ++ unsigned int i; ++ ++ if (!prog) ++ return; ++ ++ tas_dt = &prog->dev_data; ++ ++ if (!tas_dt->dev_blks) ++ return; ++ ++ for (i = 0; i < tas_dt->nr_blk; i++) { ++ blk = &tas_dt->dev_blks[i]; ++ kfree(blk->data); ++ } ++ kfree(tas_dt->dev_blks); ++} ++ ++/* DSP firmware program block data remove function. */ ++static void tasdev_dsp_prog_remove(struct tasdevice_prog *prog, ++ unsigned short nr) ++{ ++ int i; ++ ++ for (i = 0; i < nr; i++) ++ tasdev_dsp_prog_blk_remove(&prog[i]); ++ kfree(prog); ++} ++ ++/* DSP firmware config block data remove function. */ ++static void tasdev_dsp_cfg_blk_remove(struct tasdevice_config *cfg) ++{ ++ struct tasdevice_data *tas_dt; ++ struct tasdev_blk *blk; ++ unsigned int i; ++ ++ if (cfg) { ++ tas_dt = &cfg->dev_data; ++ ++ if (!tas_dt->dev_blks) ++ return; ++ ++ for (i = 0; i < tas_dt->nr_blk; i++) { ++ blk = &tas_dt->dev_blks[i]; ++ kfree(blk->data); ++ } ++ kfree(tas_dt->dev_blks); ++ } ++} ++ ++/* DSP firmware config remove function. */ ++static void tasdev_dsp_cfg_remove(struct tasdevice_config *config, ++ unsigned short nr) ++{ ++ int i; ++ ++ for (i = 0; i < nr; i++) ++ tasdev_dsp_cfg_blk_remove(&config[i]); ++ kfree(config); ++} ++ ++/* DSP firmware remove function. */ ++void tasdevice_spi_dsp_remove(void *context) ++{ ++ struct tasdevice_priv *tas_dev = context; ++ ++ if (!tas_dev->fmw) ++ return; ++ ++ if (tas_dev->fmw->programs) ++ tasdev_dsp_prog_remove(tas_dev->fmw->programs, ++ tas_dev->fmw->nr_programs); ++ if (tas_dev->fmw->configs) ++ tasdev_dsp_cfg_remove(tas_dev->fmw->configs, ++ tas_dev->fmw->nr_configurations); ++ kfree(tas_dev->fmw); ++ tas_dev->fmw = NULL; ++} ++ ++/* DSP firmware calibration data remove function. */ ++static void tas2781_clear_calfirmware(struct tasdevice_fw *tas_fmw) ++{ ++ struct tasdevice_calibration *calibration; ++ struct tasdev_blk *block; ++ unsigned int blks; ++ int i; ++ ++ if (!tas_fmw->calibrations) ++ goto out; ++ ++ for (i = 0; i < tas_fmw->nr_calibrations; i++) { ++ calibration = &tas_fmw->calibrations[i]; ++ if (!calibration) ++ continue; ++ ++ if (!calibration->dev_data.dev_blks) ++ continue; ++ ++ for (blks = 0; blks < calibration->dev_data.nr_blk; blks++) { ++ block = &calibration->dev_data.dev_blks[blks]; ++ if (!block) ++ continue; ++ kfree(block->data); ++ } ++ kfree(calibration->dev_data.dev_blks); ++ } ++ kfree(tas_fmw->calibrations); ++out: ++ kfree(tas_fmw); ++} ++ ++/* Calibration data from firmware remove function. */ ++void tasdevice_spi_calbin_remove(void *context) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ ++ if (tas_priv->cali_data_fmw) { ++ tas2781_clear_calfirmware(tas_priv->cali_data_fmw); ++ tas_priv->cali_data_fmw = NULL; ++ } ++} ++ ++/* Configuration remove function. */ ++void tasdevice_spi_config_info_remove(void *context) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ struct tasdevice_rca *rca = &tas_priv->rcabin; ++ struct tasdevice_config_info **ci = rca->cfg_info; ++ unsigned int i, j; ++ ++ if (!ci) ++ return; ++ for (i = 0; i < rca->ncfgs; i++) { ++ if (!ci[i]) ++ continue; ++ if (ci[i]->blk_data) { ++ for (j = 0; j < ci[i]->real_nblocks; j++) { ++ if (!ci[i]->blk_data[j]) ++ continue; ++ kfree(ci[i]->blk_data[j]->regdata); ++ kfree(ci[i]->blk_data[j]); ++ } ++ kfree(ci[i]->blk_data); ++ } ++ kfree(ci[i]); ++ } ++ kfree(ci); ++} ++ ++/* DSP firmware program block data load function. */ ++static int tasdevice_load_data(struct tasdevice_priv *tas_priv, ++ struct tasdevice_data *dev_data) ++{ ++ struct tasdev_blk *block; ++ unsigned int i; ++ int ret = 0; ++ ++ for (i = 0; i < dev_data->nr_blk; i++) { ++ block = &dev_data->dev_blks[i]; ++ ret = tas_priv->tasdevice_load_block(tas_priv, block); ++ if (ret < 0) ++ break; ++ } ++ ++ return ret; ++} ++ ++/* DSP firmware program load interface function. */ ++int tasdevice_spi_prmg_load(void *context, int prm_no) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ struct tasdevice_fw *tas_fmw = tas_priv->fmw; ++ struct tasdevice_prog *program; ++ struct tasdevice_config *conf; ++ int ret = 0; ++ ++ if (!tas_fmw) { ++ dev_err(tas_priv->dev, "%s: Firmware is NULL\n", __func__); ++ return -EINVAL; ++ } ++ if (prm_no >= 0 && prm_no <= tas_fmw->nr_programs) { ++ tas_priv->cur_conf = 0; ++ tas_priv->is_loading = true; ++ program = &tas_fmw->programs[prm_no]; ++ ret = tasdevice_load_data(tas_priv, &program->dev_data); ++ if (ret < 0) { ++ dev_err(tas_priv->dev, "Program failed %d.\n", ret); ++ return ret; ++ } ++ tas_priv->cur_prog = prm_no; ++ ++ conf = &tas_fmw->configs[tas_priv->cur_conf]; ++ ret = tasdevice_load_data(tas_priv, &conf->dev_data); ++ if (ret < 0) ++ dev_err(tas_priv->dev, "Config failed %d.\n", ret); ++ } else { ++ dev_err(tas_priv->dev, ++ "%s: prm(%d) is not in range of Programs %u\n", ++ __func__, prm_no, tas_fmw->nr_programs); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++/* RCABIN configuration switch interface function. */ ++void tasdevice_spi_tuning_switch(void *context, int state) ++{ ++ struct tasdevice_priv *tas_priv = context; ++ int profile_cfg_id = tas_priv->rcabin.profile_cfg_id; ++ ++ if (tas_priv->fw_state == TASDEVICE_DSP_FW_FAIL) { ++ dev_err(tas_priv->dev, "DSP bin file not loaded\n"); ++ return; ++ } ++ ++ if (state == 0) ++ tasdevice_spi_select_cfg_blk(tas_priv, profile_cfg_id, ++ TASDEVICE_BIN_BLK_PRE_POWER_UP); ++ else ++ tasdevice_spi_select_cfg_blk(tas_priv, profile_cfg_id, ++ TASDEVICE_BIN_BLK_PRE_SHUTDOWN); ++} +-- +2.39.5 + diff --git a/queue-6.12/arm64-dts-qcom-x1e80100-add-gpu-cooling.patch b/queue-6.12/arm64-dts-qcom-x1e80100-add-gpu-cooling.patch new file mode 100644 index 0000000000..953cf98424 --- /dev/null +++ b/queue-6.12/arm64-dts-qcom-x1e80100-add-gpu-cooling.patch @@ -0,0 +1,335 @@ +From c1ea929f598b8070c0fc542becf70b340f250e0a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 19 Feb 2025 12:36:20 +0100 +Subject: arm64: dts: qcom: x1e80100: Add GPU cooling +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Stephan Gerhold + +[ Upstream commit 5ba21fa11f473c9827f378ace8c9f983de9e0287 ] + +Unlike the CPU, the GPU does not throttle its speed automatically when it +reaches high temperatures. With certain high GPU loads it is possible to +reach the critical hardware shutdown temperature of 120°C, endangering the +hardware and making it impossible to run certain applications. + +Set up GPU cooling similar to the ACPI tables, by throttling the GPU speed +when reaching 95°C and polling every 200ms. + +Cc: stable@vger.kernel.org +Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support") +Signed-off-by: Stephan Gerhold +Reviewed-by: Johan Hovold +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-3-d110e44ac3f9@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++------------ + 1 file changed, 89 insertions(+), 80 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi +index edfea03366b46..5082ecb32089b 100644 +--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi ++++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&intc>; +@@ -7316,24 +7317,25 @@ nsp3-critical { + }; + + gpuss-0-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 5>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss0_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss0_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7342,24 +7344,25 @@ trip-point2 { + }; + + gpuss-1-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 6>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss1_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss1_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7368,24 +7371,25 @@ trip-point2 { + }; + + gpuss-2-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 7>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss2_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss2_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7394,24 +7398,25 @@ trip-point2 { + }; + + gpuss-3-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 8>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss3_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss3_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7420,24 +7425,25 @@ trip-point2 { + }; + + gpuss-4-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 9>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss4_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss4_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7446,24 +7452,25 @@ trip-point2 { + }; + + gpuss-5-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 10>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss5_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss5_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7472,24 +7479,25 @@ trip-point2 { + }; + + gpuss-6-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 11>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss6_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss6_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +@@ -7498,24 +7506,25 @@ trip-point2 { + }; + + gpuss-7-thermal { +- polling-delay-passive = <10>; ++ polling-delay-passive = <200>; + + thermal-sensors = <&tsens3 12>; + +- trips { +- trip-point0 { +- temperature = <85000>; +- hysteresis = <1000>; +- type = "passive"; ++ cooling-maps { ++ map0 { ++ trip = <&gpuss7_alert0>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; ++ }; + +- trip-point1 { +- temperature = <90000>; ++ trips { ++ gpuss7_alert0: trip-point0 { ++ temperature = <95000>; + hysteresis = <1000>; +- type = "hot"; ++ type = "passive"; + }; + +- trip-point2 { ++ gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; +-- +2.39.5 + diff --git a/queue-6.12/arm64-dts-qcom-x1e80100-apply-consistent-critical-th.patch b/queue-6.12/arm64-dts-qcom-x1e80100-apply-consistent-critical-th.patch new file mode 100644 index 0000000000..688b6d2771 --- /dev/null +++ b/queue-6.12/arm64-dts-qcom-x1e80100-apply-consistent-critical-th.patch @@ -0,0 +1,520 @@ +From 4ca29449186cf6dbaf6d9d14e4474d64b37c86ac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 19 Feb 2025 12:36:19 +0100 +Subject: arm64: dts: qcom: x1e80100: Apply consistent critical thermal + shutdown +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Stephan Gerhold + +[ Upstream commit 03f2b8eed73418269a158ccebad5d8d8f2f6daa1 ] + +The firmware configures the TSENS controller with a maximum temperature of +120°C. When reaching that temperature, the hardware automatically triggers +a reset of the entire platform. Some of the thermal zones in x1e80100.dtsi +use a critical trip point of 125°C. It's impossible to reach those. + +It's preferable to shut down the system cleanly before reaching the +hardware trip point. Make the critical temperature trip points consistent +by setting all of them to 115°C and apply a consistent hysteresis. +The ACPI tables also specify 115°C as critical shutdown temperature. + +Cc: stable@vger.kernel.org +Fixes: 4e915987ff5b ("arm64: dts: qcom: x1e80100: Enable tsens and thermal zone nodes") +Signed-off-by: Stephan Gerhold +Reviewed-by: Johan Hovold +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-2-d110e44ac3f9@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 128 ++++++++++++------------- + 1 file changed, 64 insertions(+), 64 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi +index 948ce7dd8b058..edfea03366b46 100644 +--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi ++++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi +@@ -6414,8 +6414,8 @@ trip-point0 { + }; + + aoss0-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6440,7 +6440,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6466,7 +6466,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6492,7 +6492,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6518,7 +6518,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6544,7 +6544,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6570,7 +6570,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6596,7 +6596,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6622,7 +6622,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6640,8 +6640,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6658,8 +6658,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6676,7 +6676,7 @@ trip-point0 { + }; + + mem-critical { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; +@@ -6694,7 +6694,7 @@ trip-point0 { + }; + + video-critical { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6712,8 +6712,8 @@ trip-point0 { + }; + + aoss0-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6738,7 +6738,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6764,7 +6764,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6790,7 +6790,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6816,7 +6816,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6842,7 +6842,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6868,7 +6868,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6894,7 +6894,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6920,7 +6920,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -6938,8 +6938,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6956,8 +6956,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -6974,8 +6974,8 @@ trip-point0 { + }; + + aoss0-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7000,7 +7000,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7026,7 +7026,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7052,7 +7052,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7078,7 +7078,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7104,7 +7104,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7130,7 +7130,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7156,7 +7156,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7182,7 +7182,7 @@ trip-point1 { + }; + + cpu-critical { +- temperature = <110000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7200,8 +7200,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7218,8 +7218,8 @@ trip-point0 { + }; + + cpuss2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7236,8 +7236,8 @@ trip-point0 { + }; + + aoss0-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7254,8 +7254,8 @@ trip-point0 { + }; + + nsp0-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7272,8 +7272,8 @@ trip-point0 { + }; + + nsp1-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7290,8 +7290,8 @@ trip-point0 { + }; + + nsp2-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7308,8 +7308,8 @@ trip-point0 { + }; + + nsp3-critical { +- temperature = <125000>; +- hysteresis = <0>; ++ temperature = <115000>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7334,7 +7334,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7360,7 +7360,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7386,7 +7386,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7412,7 +7412,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7438,7 +7438,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7464,7 +7464,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7490,7 +7490,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7516,7 +7516,7 @@ trip-point1 { + }; + + trip-point2 { +- temperature = <125000>; ++ temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; +@@ -7535,7 +7535,7 @@ trip-point0 { + + camera0-critical { + temperature = <115000>; +- hysteresis = <0>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +@@ -7553,7 +7553,7 @@ trip-point0 { + + camera0-critical { + temperature = <115000>; +- hysteresis = <0>; ++ hysteresis = <1000>; + type = "critical"; + }; + }; +-- +2.39.5 + diff --git a/queue-6.12/drm-amd-pm-add-inst-to-dpm_set_vcn_enable.patch b/queue-6.12/drm-amd-pm-add-inst-to-dpm_set_vcn_enable.patch new file mode 100644 index 0000000000..37a53faf39 --- /dev/null +++ b/queue-6.12/drm-amd-pm-add-inst-to-dpm_set_vcn_enable.patch @@ -0,0 +1,232 @@ +From 9742a9b41b5265371ebe4bcef38b1d59ac76f286 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 2 Oct 2024 20:51:53 -0400 +Subject: drm/amd/pm: add inst to dpm_set_vcn_enable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Boyuan Zhang + +[ Upstream commit 8b7f3529cd7bca239404d7279056e566639ac055 ] + +Add an instance parameter to the existing function dpm_set_vcn_enable() +for future implementation. Re-write all pptable functions accordingly. + +v2: Remove duplicated dpm_set_vcn_enable() functions in v1. Instead, +adding instance parameter to existing functions. + +Signed-off-by: Boyuan Zhang +Suggested-by: Christian König +Suggested-by: Alex Deucher +Acked-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: ee7360fc27d6 ("drm/amdgpu: read back register after written for VCN v4.0.5") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- + drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 ++- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 3 ++- + drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 4 +++- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 3 ++- + 13 files changed, 31 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +index 3fd8da5dc761e..59c083a16962d 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -255,7 +255,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu, + if (atomic_read(&power_gate->vcn_gated) ^ enable) + return 0; + +- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); ++ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff); + if (!ret) + atomic_set(&power_gate->vcn_gated, !enable); + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +index 2b8a18ce25d94..4e92295ac1b2d 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +@@ -744,7 +744,7 @@ struct pptable_funcs { + * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power + * management. + */ +- int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); ++ int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst); + + /** + * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +index 30178dde6d49f..6d46728e7627e 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +@@ -255,7 +255,8 @@ int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, + uint64_t event_arg); + + int smu_v13_0_set_vcn_enable(struct smu_context *smu, +- bool enable); ++ bool enable, ++ int inst); + + int smu_v13_0_set_jpeg_enable(struct smu_context *smu, + bool enable); +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +index 3c1b4aa4a68d7..d2289592accc0 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +@@ -210,7 +210,8 @@ int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, + uint64_t event_arg); + + int smu_v14_0_set_vcn_enable(struct smu_context *smu, +- bool enable); ++ bool enable, ++ int inst); + + int smu_v14_0_set_jpeg_enable(struct smu_context *smu, + bool enable); +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +index d4b954b22441c..4251c64d00dbe 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +@@ -2031,7 +2031,9 @@ static bool arcturus_is_dpm_running(struct smu_context *smu) + return !!(feature_enabled & SMC_DPM_FEATURE); + } + +-static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +index 27c1892b2c749..48b0eb6dd4ff4 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +@@ -1135,7 +1135,9 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) + return 0; + } + +-static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int navi10_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 1af90990d05c8..063bb60ff70f0 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -1152,7 +1152,9 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) + return 0; + } + +-static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + struct amdgpu_device *adev = smu->adev; + int i, ret = 0; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +index 9bca748ac2e94..6a7c5f60b3ada 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +@@ -461,7 +461,9 @@ static int vangogh_init_smc_tables(struct smu_context *smu) + return smu_v11_0_init_smc_tables(smu); + } + +-static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +index 1a8a42b176e52..a21be0971bb3f 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +@@ -645,7 +645,9 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context + return pm_type; + } + +-static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int renoir_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +index 4f78c84da780c..52da68bbaaf03 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -2088,7 +2088,8 @@ int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) + } + + int smu_v13_0_set_vcn_enable(struct smu_context *smu, +- bool enable) ++ bool enable, ++ int inst) + { + struct amdgpu_device *adev = smu->adev; + int i, ret = 0; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +index 9c2c43bfed0bb..3204917f91bf6 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +@@ -193,7 +193,9 @@ static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en) + return ret; + } + +-static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +index 260c339f89c5d..0890951351f97 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +@@ -220,7 +220,9 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en) + return ret; + } + +-static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable) ++static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, ++ bool enable, ++ int inst) + { + int ret = 0; + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +index e5f619c979d80..73bd75c34a76e 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +@@ -1492,7 +1492,8 @@ int smu_v14_0_set_single_dpm_table(struct smu_context *smu, + } + + int smu_v14_0_set_vcn_enable(struct smu_context *smu, +- bool enable) ++ bool enable, ++ int inst) + { + struct amdgpu_device *adev = smu->adev; + int i, ret = 0; +-- +2.39.5 + diff --git a/queue-6.12/drm-amd-pm-power-up-or-down-vcn-by-instance.patch b/queue-6.12/drm-amd-pm-power-up-or-down-vcn-by-instance.patch new file mode 100644 index 0000000000..7674e6893c --- /dev/null +++ b/queue-6.12/drm-amd-pm-power-up-or-down-vcn-by-instance.patch @@ -0,0 +1,176 @@ +From 086e935468922c353e6620a658a87f6355ae5fcd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 29 Sep 2024 15:17:29 -0400 +Subject: drm/amd/pm: power up or down vcn by instance +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Boyuan Zhang + +[ Upstream commit 8aaf166703751ffd9a9fbc4d8b996f538b278983 ] + +For smu ip with multiple vcn instances (smu 11/13/14), remove all the +for loop in dpm_set_vcn_enable() functions. And use the instance +argument to power up/down vcn for the given instance only, instead +of powering up/down for all vcn instances. + +v2: remove all duplicated functions in v1. + +remove for-loop from each ip, and temporarily move to dpm_set_vcn_enable, +in order to keep the exact same logic as before, until further separation +in the next patch. + +Signed-off-by: Boyuan Zhang +Acked-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: ee7360fc27d6 ("drm/amdgpu: read back register after written for VCN v4.0.5") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 +++-- + .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 20 +++++------ + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 16 ++++----- + .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 35 ++++++++----------- + 4 files changed, 35 insertions(+), 45 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +index 59c083a16962d..6535508d01e1f 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -241,6 +241,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu, + { + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_power_gate *power_gate = &smu_power->power_gate; ++ struct amdgpu_device *adev = smu->adev; + int ret = 0; + + /* +@@ -255,9 +256,11 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu, + if (atomic_read(&power_gate->vcn_gated) ^ enable) + return 0; + +- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff); +- if (!ret) +- atomic_set(&power_gate->vcn_gated, !enable); ++ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) { ++ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i); ++ if (ret) ++ return ret; ++ } + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 063bb60ff70f0..b2472bfa0c3bb 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -1157,19 +1157,15 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, + int inst) + { + struct amdgpu_device *adev = smu->adev; +- int i, ret = 0; ++ int ret = 0; + +- for (i = 0; i < adev->vcn.num_vcn_inst; i++) { +- if (adev->vcn.harvest_config & (1 << i)) +- continue; +- /* vcn dpm on is a prerequisite for vcn power gate messages */ +- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { +- ret = smu_cmn_send_smc_msg_with_param(smu, enable ? +- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, +- 0x10000 * i, NULL); +- if (ret) +- return ret; +- } ++ if (adev->vcn.harvest_config & (1 << inst)) ++ return ret; ++ /* vcn dpm on is a prerequisite for vcn power gate messages */ ++ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { ++ ret = smu_cmn_send_smc_msg_with_param(smu, enable ? ++ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, ++ 0x10000 * inst, NULL); + } + + return ret; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +index 52da68bbaaf03..8d0e215159fa6 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -2092,18 +2092,14 @@ int smu_v13_0_set_vcn_enable(struct smu_context *smu, + int inst) + { + struct amdgpu_device *adev = smu->adev; +- int i, ret = 0; ++ int ret = 0; + +- for (i = 0; i < adev->vcn.num_vcn_inst; i++) { +- if (adev->vcn.harvest_config & (1 << i)) +- continue; ++ if (adev->vcn.harvest_config & (1 << inst)) ++ return ret; + +- ret = smu_cmn_send_smc_msg_with_param(smu, enable ? +- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, +- i << 16U, NULL); +- if (ret) +- return ret; +- } ++ ret = smu_cmn_send_smc_msg_with_param(smu, enable ? ++ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, ++ inst << 16U, NULL); + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +index 73bd75c34a76e..47cee5a77107a 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +@@ -1496,29 +1496,24 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu, + int inst) + { + struct amdgpu_device *adev = smu->adev; +- int i, ret = 0; ++ int ret = 0; + +- for (i = 0; i < adev->vcn.num_vcn_inst; i++) { +- if (adev->vcn.harvest_config & (1 << i)) +- continue; ++ if (adev->vcn.harvest_config & (1 << inst)) ++ return ret; + +- if (smu->is_apu) { +- if (i == 0) +- ret = smu_cmn_send_smc_msg_with_param(smu, enable ? +- SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0, +- i << 16U, NULL); +- else if (i == 1) +- ret = smu_cmn_send_smc_msg_with_param(smu, enable ? +- SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1, +- i << 16U, NULL); +- } else { ++ if (smu->is_apu) { ++ if (inst == 0) + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? +- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, +- i << 16U, NULL); +- } +- +- if (ret) +- return ret; ++ SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0, ++ inst << 16U, NULL); ++ else if (inst == 1) ++ ret = smu_cmn_send_smc_msg_with_param(smu, enable ? ++ SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1, ++ inst << 16U, NULL); ++ } else { ++ ret = smu_cmn_send_smc_msg_with_param(smu, enable ? ++ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, ++ inst << 16U, NULL); + } + + return ret; +-- +2.39.5 + diff --git a/queue-6.12/drm-amdgpu-read-back-register-after-written-for-vcn-.patch b/queue-6.12/drm-amdgpu-read-back-register-after-written-for-vcn-.patch new file mode 100644 index 0000000000..993fb0a861 --- /dev/null +++ b/queue-6.12/drm-amdgpu-read-back-register-after-written-for-vcn-.patch @@ -0,0 +1,56 @@ +From 8185ec1cd181014bb78cd9e6b5a721f4ab71b843 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 May 2025 15:14:43 -0400 +Subject: drm/amdgpu: read back register after written for VCN v4.0.5 + +From: David (Ming Qiang) Wu + +[ Upstream commit 07c9db090b86e5211188e1b351303fbc673378cf ] + +On VCN v4.0.5 there is a race condition where the WPTR is not +updated after starting from idle when doorbell is used. Adding +register read-back after written at function end is to ensure +all register writes are done before they can be used. + +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528 +Signed-off-by: David (Ming Qiang) Wu +Reviewed-by: Mario Limonciello +Tested-by: Mario Limonciello +Reviewed-by: Alex Deucher +Reviewed-by: Ruijing Dong +Signed-off-by: Alex Deucher +Stable-dep-of: ee7360fc27d6 ("drm/amdgpu: read back register after written for VCN v4.0.5") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +index e0b02bf1c5639..db33a2b9109aa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +@@ -985,6 +985,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + ++ /* Keeping one read-back to ensure all register writes are done, otherwise ++ * it may introduce race conditions */ ++ RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL); ++ + return 0; + } + +@@ -1169,6 +1173,10 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev) + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); + } + ++ /* Keeping one read-back to ensure all register writes are done, otherwise ++ * it may introduce race conditions */ ++ RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); ++ + return 0; + } + +-- +2.39.5 + diff --git a/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-fix-clocks.patch b/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-fix-clocks.patch new file mode 100644 index 0000000000..d019324ba1 --- /dev/null +++ b/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-fix-clocks.patch @@ -0,0 +1,75 @@ +From d4521e5fe19f0ccb10936afbed016b4ca2d6ab57 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 May 2025 11:53:19 -0500 +Subject: dt-bindings: pwm: adi,axi-pwmgen: Fix clocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: David Lechner + +[ Upstream commit e683131e64f71e957ca77743cb3d313646157329 ] + +Fix a shortcoming in the bindings that doesn't allow for a separate +external clock. + +The AXI PWMGEN IP block has a compile option ASYNC_CLK_EN that allows +the use of an external clock for the PWM output separate from the AXI +clock that runs the peripheral. + +This was missed in the original bindings and so users were writing dts +files where the one and only clock specified would be the external +clock, if there was one, incorrectly missing the separate AXI clock. + +The correct bindings are that the AXI clock is always required and the +external clock is optional (must be given only when HDL compile option +ASYNC_CLK_EN=1). + +Fixes: 1edf2c2a2841 ("dt-bindings: pwm: Add AXI PWM generator") +Cc: stable@vger.kernel.org +Signed-off-by: David Lechner +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250529-pwm-axi-pwmgen-add-external-clock-v3-2-5d8809a7da91@baylibre.com +Signed-off-by: Uwe Kleine-König +Signed-off-by: Sasha Levin +--- + .../devicetree/bindings/pwm/adi,axi-pwmgen.yaml | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +index 45e112d0efb46..5575c58357d6e 100644 +--- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml ++++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +@@ -30,11 +30,19 @@ properties: + const: 3 + + clocks: +- maxItems: 1 ++ minItems: 1 ++ maxItems: 2 ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: axi ++ - const: ext + + required: + - reg + - clocks ++ - clock-names + + unevaluatedProperties: false + +@@ -43,6 +51,7 @@ examples: + pwm@44b00000 { + compatible = "adi,axi-pwmgen-2.00.a"; + reg = <0x44b00000 0x1000>; +- clocks = <&spi_clk>; ++ clocks = <&fpga_clk>, <&spi_clk>; ++ clock-names = "axi", "ext"; + #pwm-cells = <3>; + }; +-- +2.39.5 + diff --git a/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-increase-pwm-cells-to.patch b/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-increase-pwm-cells-to.patch new file mode 100644 index 0000000000..a86c09c0eb --- /dev/null +++ b/queue-6.12/dt-bindings-pwm-adi-axi-pwmgen-increase-pwm-cells-to.patch @@ -0,0 +1,51 @@ +From f1945242470015522c38d8011bd2ae3a56fd881a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 24 Oct 2024 12:25:54 +0200 +Subject: dt-bindings: pwm: adi,axi-pwmgen: Increase #pwm-cells to 3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit 664b5e466f915ad7fce87215ccfb038c47ace4fb ] + +Using 3 cells allows to pass additional flags and is the normal +abstraction for new PWM descriptions. There are no device trees yet to +adapt to this change. + +Signed-off-by: Uwe Kleine-König +Reviewed-by: Nuno Sa +Acked-by: Conor Dooley +Reviewed-by: Trevor Gamblin +Link: https://lore.kernel.org/r/20241024102554.711689-2-u.kleine-koenig@baylibre.com +Signed-off-by: Uwe Kleine-König +Stable-dep-of: e683131e64f7 ("dt-bindings: pwm: adi,axi-pwmgen: Fix clocks") +Signed-off-by: Sasha Levin +--- + Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +index ec6115d3796ba..aa35209f74cfa 100644 +--- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml ++++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +@@ -27,7 +27,7 @@ properties: + maxItems: 1 + + "#pwm-cells": +- const: 2 ++ const: 3 + + clocks: + maxItems: 1 +@@ -44,5 +44,5 @@ examples: + compatible = "adi,axi-pwmgen-2.00.a"; + reg = <0x44b00000 0x1000>; + clocks = <&spi_clk>; +- #pwm-cells = <2>; ++ #pwm-cells = <3>; + }; +-- +2.39.5 + diff --git a/queue-6.12/dt-bindings-pwm-correct-indentation-and-style-in-dts.patch b/queue-6.12/dt-bindings-pwm-correct-indentation-and-style-in-dts.patch new file mode 100644 index 0000000000..f8c78ae284 --- /dev/null +++ b/queue-6.12/dt-bindings-pwm-correct-indentation-and-style-in-dts.patch @@ -0,0 +1,86 @@ +From f14493ba6c6f60a7cf3b002f205bb3443ac34662 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Jan 2025 13:58:30 +0100 +Subject: dt-bindings: pwm: Correct indentation and style in DTS example +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Krzysztof Kozlowski + +[ Upstream commit 78dcad6daa405b8a939cd08f6ccd6c4e2cb50a9c ] + +DTS example in the bindings should be indented with 2- or 4-spaces and +aligned with opening '- |', so correct any differences like 3-spaces or +mixtures 2- and 4-spaces in one binding. + +No functional changes here, but saves some comments during reviews of +new patches built on existing code. + +Signed-off-by: Krzysztof Kozlowski +Acked-by: Nuno Sa +Link: https://lore.kernel.org/r/20250107125831.225068-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Uwe Kleine-König +Stable-dep-of: e683131e64f7 ("dt-bindings: pwm: adi,axi-pwmgen: Fix clocks") +Signed-off-by: Sasha Levin +--- + Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml | 8 ++++---- + .../devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml | 8 ++++---- + Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml | 8 ++++---- + 3 files changed, 12 insertions(+), 12 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +index aa35209f74cfa..45e112d0efb46 100644 +--- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml ++++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +@@ -41,8 +41,8 @@ unevaluatedProperties: false + examples: + - | + pwm@44b00000 { +- compatible = "adi,axi-pwmgen-2.00.a"; +- reg = <0x44b00000 0x1000>; +- clocks = <&spi_clk>; +- #pwm-cells = <3>; ++ compatible = "adi,axi-pwmgen-2.00.a"; ++ reg = <0x44b00000 0x1000>; ++ clocks = <&spi_clk>; ++ #pwm-cells = <3>; + }; +diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml +index 119de3d7f9dd7..44548a9da1580 100644 +--- a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml ++++ b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml +@@ -35,8 +35,8 @@ additionalProperties: false + examples: + - | + pwm: pwm@f0408000 { +- compatible = "brcm,bcm7038-pwm"; +- reg = <0xf0408000 0x28>; +- #pwm-cells = <2>; +- clocks = <&upg_fixed>; ++ compatible = "brcm,bcm7038-pwm"; ++ reg = <0xf0408000 0x28>; ++ #pwm-cells = <2>; ++ clocks = <&upg_fixed>; + }; +diff --git a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml +index e86c8053b366a..fd785da5d3d73 100644 +--- a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml ++++ b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml +@@ -43,9 +43,9 @@ examples: + #include + + pwm@3e01a000 { +- compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; +- reg = <0x3e01a000 0xcc>; +- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; +- #pwm-cells = <3>; ++ compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; ++ reg = <0x3e01a000 0xcc>; ++ clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; ++ #pwm-cells = <3>; + }; + ... +-- +2.39.5 + diff --git a/queue-6.12/input-synaptics-rmi-fix-crash-with-unsupported-versi.patch b/queue-6.12/input-synaptics-rmi-fix-crash-with-unsupported-versi.patch new file mode 100644 index 0000000000..7a21b24616 --- /dev/null +++ b/queue-6.12/input-synaptics-rmi-fix-crash-with-unsupported-versi.patch @@ -0,0 +1,262 @@ +From 62206a165a3e7dcfa159ef1c97151d3c04a1d176 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 May 2025 15:49:59 -0700 +Subject: Input: synaptics-rmi - fix crash with unsupported versions of F34 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Dmitry Torokhov + +[ Upstream commit ca39500f6af9cfe6823dc5aa8fbaed788d6e35b2 ] + +Sysfs interface for updating firmware for RMI devices is available even +when F34 probe fails. The code checks for presence of F34 "container" +pointer and then tries to use the function data attached to the +sub-device. F34 assigns the function data early, before it knows if +probe will succeed, leaving behind a stale pointer. + +Fix this by expanding checks to not only test for presence of F34 +"container" but also check if there is driver data assigned to the +sub-device, and call dev_set_drvdata() only after we are certain that +probe is successful. + +This is not a complete fix, since F34 will be freed during firmware +update, so there is still a race when fetching and accessing this +pointer. This race will be addressed in follow-up changes. + +Reported-by: Hanno Böck +Fixes: 29fd0ec2bdbe ("Input: synaptics-rmi4 - add support for F34 device reflash") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/aBlAl6sGulam-Qcx@google.com +Signed-off-by: Dmitry Torokhov +Signed-off-by: Sasha Levin +--- + drivers/input/rmi4/rmi_f34.c | 135 ++++++++++++++++++++--------------- + 1 file changed, 76 insertions(+), 59 deletions(-) + +diff --git a/drivers/input/rmi4/rmi_f34.c b/drivers/input/rmi4/rmi_f34.c +index e2468bc04a5cb..c2516c7549582 100644 +--- a/drivers/input/rmi4/rmi_f34.c ++++ b/drivers/input/rmi4/rmi_f34.c +@@ -4,6 +4,7 @@ + * Copyright (C) 2016 Zodiac Inflight Innovations + */ + ++#include "linux/device.h" + #include + #include + #include +@@ -298,39 +299,30 @@ static int rmi_f34_update_firmware(struct f34_data *f34, + return ret; + } + +-static int rmi_f34_status(struct rmi_function *fn) +-{ +- struct f34_data *f34 = dev_get_drvdata(&fn->dev); +- +- /* +- * The status is the percentage complete, or once complete, +- * zero for success or a negative return code. +- */ +- return f34->update_status; +-} +- + static ssize_t rmi_driver_bootloader_id_show(struct device *dev, + struct device_attribute *dattr, + char *buf) + { + struct rmi_driver_data *data = dev_get_drvdata(dev); +- struct rmi_function *fn = data->f34_container; ++ struct rmi_function *fn; + struct f34_data *f34; + +- if (fn) { +- f34 = dev_get_drvdata(&fn->dev); +- +- if (f34->bl_version == 5) +- return sysfs_emit(buf, "%c%c\n", +- f34->bootloader_id[0], +- f34->bootloader_id[1]); +- else +- return sysfs_emit(buf, "V%d.%d\n", +- f34->bootloader_id[1], +- f34->bootloader_id[0]); +- } ++ fn = data->f34_container; ++ if (!fn) ++ return -ENODEV; + +- return 0; ++ f34 = dev_get_drvdata(&fn->dev); ++ if (!f34) ++ return -ENODEV; ++ ++ if (f34->bl_version == 5) ++ return sysfs_emit(buf, "%c%c\n", ++ f34->bootloader_id[0], ++ f34->bootloader_id[1]); ++ else ++ return sysfs_emit(buf, "V%d.%d\n", ++ f34->bootloader_id[1], ++ f34->bootloader_id[0]); + } + + static DEVICE_ATTR(bootloader_id, 0444, rmi_driver_bootloader_id_show, NULL); +@@ -343,13 +335,16 @@ static ssize_t rmi_driver_configuration_id_show(struct device *dev, + struct rmi_function *fn = data->f34_container; + struct f34_data *f34; + +- if (fn) { +- f34 = dev_get_drvdata(&fn->dev); ++ fn = data->f34_container; ++ if (!fn) ++ return -ENODEV; + +- return sysfs_emit(buf, "%s\n", f34->configuration_id); +- } ++ f34 = dev_get_drvdata(&fn->dev); ++ if (!f34) ++ return -ENODEV; + +- return 0; ++ ++ return sysfs_emit(buf, "%s\n", f34->configuration_id); + } + + static DEVICE_ATTR(configuration_id, 0444, +@@ -365,10 +360,14 @@ static int rmi_firmware_update(struct rmi_driver_data *data, + + if (!data->f34_container) { + dev_warn(dev, "%s: No F34 present!\n", __func__); +- return -EINVAL; ++ return -ENODEV; + } + + f34 = dev_get_drvdata(&data->f34_container->dev); ++ if (!f34) { ++ dev_warn(dev, "%s: No valid F34 present!\n", __func__); ++ return -ENODEV; ++ } + + if (f34->bl_version >= 7) { + if (data->pdt_props & HAS_BSR) { +@@ -494,10 +493,18 @@ static ssize_t rmi_driver_update_fw_status_show(struct device *dev, + char *buf) + { + struct rmi_driver_data *data = dev_get_drvdata(dev); +- int update_status = 0; ++ struct f34_data *f34; ++ int update_status = -ENODEV; + +- if (data->f34_container) +- update_status = rmi_f34_status(data->f34_container); ++ /* ++ * The status is the percentage complete, or once complete, ++ * zero for success or a negative return code. ++ */ ++ if (data->f34_container) { ++ f34 = dev_get_drvdata(&data->f34_container->dev); ++ if (f34) ++ update_status = f34->update_status; ++ } + + return sysfs_emit(buf, "%d\n", update_status); + } +@@ -517,33 +524,21 @@ static const struct attribute_group rmi_firmware_attr_group = { + .attrs = rmi_firmware_attrs, + }; + +-static int rmi_f34_probe(struct rmi_function *fn) ++static int rmi_f34v5_probe(struct f34_data *f34) + { +- struct f34_data *f34; +- unsigned char f34_queries[9]; ++ struct rmi_function *fn = f34->fn; ++ u8 f34_queries[9]; + bool has_config_id; +- u8 version = fn->fd.function_version; +- int ret; +- +- f34 = devm_kzalloc(&fn->dev, sizeof(struct f34_data), GFP_KERNEL); +- if (!f34) +- return -ENOMEM; +- +- f34->fn = fn; +- dev_set_drvdata(&fn->dev, f34); +- +- /* v5 code only supported version 0, try V7 probe */ +- if (version > 0) +- return rmi_f34v7_probe(f34); ++ int error; + + f34->bl_version = 5; + +- ret = rmi_read_block(fn->rmi_dev, fn->fd.query_base_addr, +- f34_queries, sizeof(f34_queries)); +- if (ret) { ++ error = rmi_read_block(fn->rmi_dev, fn->fd.query_base_addr, ++ f34_queries, sizeof(f34_queries)); ++ if (error) { + dev_err(&fn->dev, "%s: Failed to query properties\n", + __func__); +- return ret; ++ return error; + } + + snprintf(f34->bootloader_id, sizeof(f34->bootloader_id), +@@ -569,11 +564,11 @@ static int rmi_f34_probe(struct rmi_function *fn) + f34->v5.config_blocks); + + if (has_config_id) { +- ret = rmi_read_block(fn->rmi_dev, fn->fd.control_base_addr, +- f34_queries, sizeof(f34_queries)); +- if (ret) { ++ error = rmi_read_block(fn->rmi_dev, fn->fd.control_base_addr, ++ f34_queries, sizeof(f34_queries)); ++ if (error) { + dev_err(&fn->dev, "Failed to read F34 config ID\n"); +- return ret; ++ return error; + } + + snprintf(f34->configuration_id, sizeof(f34->configuration_id), +@@ -582,12 +577,34 @@ static int rmi_f34_probe(struct rmi_function *fn) + f34_queries[2], f34_queries[3]); + + rmi_dbg(RMI_DEBUG_FN, &fn->dev, "Configuration ID: %s\n", +- f34->configuration_id); ++ f34->configuration_id); + } + + return 0; + } + ++static int rmi_f34_probe(struct rmi_function *fn) ++{ ++ struct f34_data *f34; ++ u8 version = fn->fd.function_version; ++ int error; ++ ++ f34 = devm_kzalloc(&fn->dev, sizeof(struct f34_data), GFP_KERNEL); ++ if (!f34) ++ return -ENOMEM; ++ ++ f34->fn = fn; ++ ++ /* v5 code only supported version 0 */ ++ error = version == 0 ? rmi_f34v5_probe(f34) : rmi_f34v7_probe(f34); ++ if (error) ++ return error; ++ ++ dev_set_drvdata(&fn->dev, f34); ++ ++ return 0; ++} ++ + int rmi_f34_create_sysfs(struct rmi_device *rmi_dev) + { + return sysfs_create_group(&rmi_dev->dev.kobj, &rmi_firmware_attr_group); +-- +2.39.5 + diff --git a/queue-6.12/kasan-avoid-sleepable-page-allocation-from-atomic-co.patch b/queue-6.12/kasan-avoid-sleepable-page-allocation-from-atomic-co.patch new file mode 100644 index 0000000000..739e0bd85f --- /dev/null +++ b/queue-6.12/kasan-avoid-sleepable-page-allocation-from-atomic-co.patch @@ -0,0 +1,199 @@ +From 0645280b7cdbde92040f5a35817e56324c8a310a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 May 2025 15:55:38 +0200 +Subject: kasan: avoid sleepable page allocation from atomic context + +From: Alexander Gordeev + +[ Upstream commit b6ea95a34cbd014ab6ade4248107b86b0aaf2d6c ] + +apply_to_pte_range() enters the lazy MMU mode and then invokes +kasan_populate_vmalloc_pte() callback on each page table walk iteration. +However, the callback can go into sleep when trying to allocate a single +page, e.g. if an architecutre disables preemption on lazy MMU mode enter. + +On s390 if make arch_enter_lazy_mmu_mode() -> preempt_enable() and +arch_leave_lazy_mmu_mode() -> preempt_disable(), such crash occurs: + +[ 0.663336] BUG: sleeping function called from invalid context at ./include/linux/sched/mm.h:321 +[ 0.663348] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 2, name: kthreadd +[ 0.663358] preempt_count: 1, expected: 0 +[ 0.663366] RCU nest depth: 0, expected: 0 +[ 0.663375] no locks held by kthreadd/2. +[ 0.663383] Preemption disabled at: +[ 0.663386] [<0002f3284cbb4eda>] apply_to_pte_range+0xfa/0x4a0 +[ 0.663405] CPU: 0 UID: 0 PID: 2 Comm: kthreadd Not tainted 6.15.0-rc5-gcc-kasan-00043-gd76bb1ebb558-dirty #162 PREEMPT +[ 0.663408] Hardware name: IBM 3931 A01 701 (KVM/Linux) +[ 0.663409] Call Trace: +[ 0.663410] [<0002f3284c385f58>] dump_stack_lvl+0xe8/0x140 +[ 0.663413] [<0002f3284c507b9e>] __might_resched+0x66e/0x700 +[ 0.663415] [<0002f3284cc4f6c0>] __alloc_frozen_pages_noprof+0x370/0x4b0 +[ 0.663419] [<0002f3284ccc73c0>] alloc_pages_mpol+0x1a0/0x4a0 +[ 0.663421] [<0002f3284ccc8518>] alloc_frozen_pages_noprof+0x88/0xc0 +[ 0.663424] [<0002f3284ccc8572>] alloc_pages_noprof+0x22/0x120 +[ 0.663427] [<0002f3284cc341ac>] get_free_pages_noprof+0x2c/0xc0 +[ 0.663429] [<0002f3284cceba70>] kasan_populate_vmalloc_pte+0x50/0x120 +[ 0.663433] [<0002f3284cbb4ef8>] apply_to_pte_range+0x118/0x4a0 +[ 0.663435] [<0002f3284cbc7c14>] apply_to_pmd_range+0x194/0x3e0 +[ 0.663437] [<0002f3284cbc99be>] __apply_to_page_range+0x2fe/0x7a0 +[ 0.663440] [<0002f3284cbc9e88>] apply_to_page_range+0x28/0x40 +[ 0.663442] [<0002f3284ccebf12>] kasan_populate_vmalloc+0x82/0xa0 +[ 0.663445] [<0002f3284cc1578c>] alloc_vmap_area+0x34c/0xc10 +[ 0.663448] [<0002f3284cc1c2a6>] __get_vm_area_node+0x186/0x2a0 +[ 0.663451] [<0002f3284cc1e696>] __vmalloc_node_range_noprof+0x116/0x310 +[ 0.663454] [<0002f3284cc1d950>] __vmalloc_node_noprof+0xd0/0x110 +[ 0.663457] [<0002f3284c454b88>] alloc_thread_stack_node+0xf8/0x330 +[ 0.663460] [<0002f3284c458d56>] dup_task_struct+0x66/0x4d0 +[ 0.663463] [<0002f3284c45be90>] copy_process+0x280/0x4b90 +[ 0.663465] [<0002f3284c460940>] kernel_clone+0xd0/0x4b0 +[ 0.663467] [<0002f3284c46115e>] kernel_thread+0xbe/0xe0 +[ 0.663469] [<0002f3284c4e440e>] kthreadd+0x50e/0x7f0 +[ 0.663472] [<0002f3284c38c04a>] __ret_from_fork+0x8a/0xf0 +[ 0.663475] [<0002f3284ed57ff2>] ret_from_fork+0xa/0x38 + +Instead of allocating single pages per-PTE, bulk-allocate the shadow +memory prior to applying kasan_populate_vmalloc_pte() callback on a page +range. + +Link: https://lkml.kernel.org/r/c61d3560297c93ed044f0b1af085610353a06a58.1747316918.git.agordeev@linux.ibm.com +Fixes: 3c5c3cfb9ef4 ("kasan: support backing vmalloc space with real shadow memory") +Signed-off-by: Alexander Gordeev +Suggested-by: Andrey Ryabinin +Reviewed-by: Harry Yoo +Cc: Daniel Axtens +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Sasha Levin +--- + mm/kasan/shadow.c | 92 +++++++++++++++++++++++++++++++++++++++-------- + 1 file changed, 78 insertions(+), 14 deletions(-) + +diff --git a/mm/kasan/shadow.c b/mm/kasan/shadow.c +index 88d1c9dcb5072..d2c70cd2afb1d 100644 +--- a/mm/kasan/shadow.c ++++ b/mm/kasan/shadow.c +@@ -292,33 +292,99 @@ void __init __weak kasan_populate_early_vm_area_shadow(void *start, + { + } + ++struct vmalloc_populate_data { ++ unsigned long start; ++ struct page **pages; ++}; ++ + static int kasan_populate_vmalloc_pte(pte_t *ptep, unsigned long addr, +- void *unused) ++ void *_data) + { +- unsigned long page; ++ struct vmalloc_populate_data *data = _data; ++ struct page *page; + pte_t pte; ++ int index; + + if (likely(!pte_none(ptep_get(ptep)))) + return 0; + +- page = __get_free_page(GFP_KERNEL); +- if (!page) +- return -ENOMEM; +- +- __memset((void *)page, KASAN_VMALLOC_INVALID, PAGE_SIZE); +- pte = pfn_pte(PFN_DOWN(__pa(page)), PAGE_KERNEL); ++ index = PFN_DOWN(addr - data->start); ++ page = data->pages[index]; ++ __memset(page_to_virt(page), KASAN_VMALLOC_INVALID, PAGE_SIZE); ++ pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL); + + spin_lock(&init_mm.page_table_lock); + if (likely(pte_none(ptep_get(ptep)))) { + set_pte_at(&init_mm, addr, ptep, pte); +- page = 0; ++ data->pages[index] = NULL; + } + spin_unlock(&init_mm.page_table_lock); +- if (page) +- free_page(page); ++ ++ return 0; ++} ++ ++static void ___free_pages_bulk(struct page **pages, int nr_pages) ++{ ++ int i; ++ ++ for (i = 0; i < nr_pages; i++) { ++ if (pages[i]) { ++ __free_pages(pages[i], 0); ++ pages[i] = NULL; ++ } ++ } ++} ++ ++static int ___alloc_pages_bulk(struct page **pages, int nr_pages) ++{ ++ unsigned long nr_populated, nr_total = nr_pages; ++ struct page **page_array = pages; ++ ++ while (nr_pages) { ++ nr_populated = alloc_pages_bulk(GFP_KERNEL, nr_pages, pages); ++ if (!nr_populated) { ++ ___free_pages_bulk(page_array, nr_total - nr_pages); ++ return -ENOMEM; ++ } ++ pages += nr_populated; ++ nr_pages -= nr_populated; ++ } ++ + return 0; + } + ++static int __kasan_populate_vmalloc(unsigned long start, unsigned long end) ++{ ++ unsigned long nr_pages, nr_total = PFN_UP(end - start); ++ struct vmalloc_populate_data data; ++ int ret = 0; ++ ++ data.pages = (struct page **)__get_free_page(GFP_KERNEL | __GFP_ZERO); ++ if (!data.pages) ++ return -ENOMEM; ++ ++ while (nr_total) { ++ nr_pages = min(nr_total, PAGE_SIZE / sizeof(data.pages[0])); ++ ret = ___alloc_pages_bulk(data.pages, nr_pages); ++ if (ret) ++ break; ++ ++ data.start = start; ++ ret = apply_to_page_range(&init_mm, start, nr_pages * PAGE_SIZE, ++ kasan_populate_vmalloc_pte, &data); ++ ___free_pages_bulk(data.pages, nr_pages); ++ if (ret) ++ break; ++ ++ start += nr_pages * PAGE_SIZE; ++ nr_total -= nr_pages; ++ } ++ ++ free_page((unsigned long)data.pages); ++ ++ return ret; ++} ++ + int kasan_populate_vmalloc(unsigned long addr, unsigned long size) + { + unsigned long shadow_start, shadow_end; +@@ -348,9 +414,7 @@ int kasan_populate_vmalloc(unsigned long addr, unsigned long size) + shadow_start = PAGE_ALIGN_DOWN(shadow_start); + shadow_end = PAGE_ALIGN(shadow_end); + +- ret = apply_to_page_range(&init_mm, shadow_start, +- shadow_end - shadow_start, +- kasan_populate_vmalloc_pte, NULL); ++ ret = __kasan_populate_vmalloc(shadow_start, shadow_end); + if (ret) + return ret; + +-- +2.39.5 + diff --git a/queue-6.12/mmc-sdhci-of-dwcmshc-add-pd-workaround-on-rk3576.patch b/queue-6.12/mmc-sdhci-of-dwcmshc-add-pd-workaround-on-rk3576.patch new file mode 100644 index 0000000000..f407192901 --- /dev/null +++ b/queue-6.12/mmc-sdhci-of-dwcmshc-add-pd-workaround-on-rk3576.patch @@ -0,0 +1,118 @@ +From 194883c47128a1a7f3139fe04fff0ed4d7830fcc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Apr 2025 09:53:32 +0200 +Subject: mmc: sdhci-of-dwcmshc: add PD workaround on RK3576 + +From: Nicolas Frattaroli + +[ Upstream commit 08f959759e1e6e9c4b898c51a7d387ac3480630b ] + +RK3576's power domains have a peculiar design where the PD_NVM power +domain, of which the sdhci controller is a part, seemingly does not have +idempotent runtime disable/enable. The end effect is that if PD_NVM gets +turned off by the generic power domain logic because all the devices +depending on it are suspended, then the next time the sdhci device is +unsuspended, it'll hang the SoC as soon as it tries accessing the CQHCI +registers. + +RK3576's UFS support needed a new dev_pm_genpd_rpm_always_on function +added to the generic power domains API to handle what appears to be a +similar hardware design. + +Use this new function to ask for the same treatment in the sdhci +controller by giving rk3576 its own platform data with its own postinit +function. The benefit of doing this instead of marking the power domains +always on in the power domain core is that we only do this if we know +the platform we're running on actually uses the sdhci controller. For +others, keeping PD_NVM always on would be a waste, as they won't run +into this specific issue. The only other IP in PD_NVM that could be +affected is FSPI0. If it gets a mainline driver, it will probably want +to do the same thing. + +Acked-by: Adrian Hunter +Signed-off-by: Nicolas Frattaroli +Reviewed-by: Shawn Lin +Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC") +Cc: # v6.15+ +Link: https://lore.kernel.org/r/20250423-rk3576-emmc-fix-v3-1-0bf80e29967f@collabora.com +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 40 +++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 8fd80dac11bfd..bf29aad082a19 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -787,6 +788,29 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv + } + } + ++static void dwcmshc_rk3576_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) ++{ ++ struct device *dev = mmc_dev(host->mmc); ++ int ret; ++ ++ /* ++ * This works around the design of the RK3576's power domains, which ++ * makes the PD_NVM power domain, which the sdhci controller on the ++ * RK3576 is in, never come back the same way once it's run-time ++ * suspended once. This can happen during early kernel boot if no driver ++ * is using either PD_NVM or its child power domain PD_SDGMAC for a ++ * short moment, leading to it being turned off to save power. By ++ * keeping it on, sdhci suspending won't lead to PD_NVM becoming a ++ * candidate for getting turned off. ++ */ ++ ret = dev_pm_genpd_rpm_always_on(dev, true); ++ if (ret && ret != -EOPNOTSUPP) ++ dev_warn(dev, "failed to set PD rpm always on, SoC may hang later: %pe\n", ++ ERR_PTR(ret)); ++ ++ dwcmshc_rk35xx_postinit(host, dwc_priv); ++} ++ + static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) + { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); +@@ -1218,6 +1242,18 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { + .postinit = dwcmshc_rk35xx_postinit, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3576_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_rk35xx_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | ++ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, ++ }, ++ .init = dwcmshc_rk35xx_init, ++ .postinit = dwcmshc_rk3576_postinit, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, +@@ -1316,6 +1352,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "rockchip,rk3588-dwcmshc", + .data = &sdhci_dwcmshc_rk35xx_pdata, + }, ++ { ++ .compatible = "rockchip,rk3576-dwcmshc", ++ .data = &sdhci_dwcmshc_rk3576_pdata, ++ }, + { + .compatible = "rockchip,rk3568-dwcmshc", + .data = &sdhci_dwcmshc_rk35xx_pdata, +-- +2.39.5 + diff --git a/queue-6.12/pinctrl-samsung-add-dedicated-soc-eint-suspend-resum.patch b/queue-6.12/pinctrl-samsung-add-dedicated-soc-eint-suspend-resum.patch new file mode 100644 index 0000000000..0106b6c328 --- /dev/null +++ b/queue-6.12/pinctrl-samsung-add-dedicated-soc-eint-suspend-resum.patch @@ -0,0 +1,311 @@ +From 2f836d9174448b2dd1d0f1a3689671aea5090968 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 2 Apr 2025 16:17:31 +0100 +Subject: pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Peter Griffin + +[ Upstream commit 77ac6b742eba063a5b6600cda67834a7a212281a ] + +Refactor the existing platform specific suspend/resume callback +so that each SoC variant has it's own callback containing the +SoC specific logic. + +This allows exynosautov920 to have a dedicated function for using +eint_con_offset and eint_mask_offset. Also it is easily extendable +for gs101 which will need dedicated logic for handling the varying +register offset of fltcon0 via eint_fltcon_offset. + +Reviewed-by: André Draszik +Signed-off-by: Peter Griffin +Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-2-78ce0d4eb30c@linaro.org +Signed-off-by: Krzysztof Kozlowski +Stable-dep-of: bdbe0a0f7100 ("pinctrl: samsung: add gs101 specific eint suspend/resume callbacks") +Signed-off-by: Sasha Levin +--- + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 28 ++-- + drivers/pinctrl/samsung/pinctrl-exynos.c | 152 ++++++++++-------- + drivers/pinctrl/samsung/pinctrl-exynos.h | 2 + + 3 files changed, 97 insertions(+), 85 deletions(-) + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +index 23b4bc1e5da81..ce61a85c7784a 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c ++++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +@@ -809,8 +809,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { + .pin_banks = exynosautov920_pin_banks0, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + .retention_data = &exynosautov920_retention_data, + }, { + /* pin-controller instance 1 AUD data */ +@@ -821,43 +821,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { + .pin_banks = exynosautov920_pin_banks2, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, { + /* pin-controller instance 3 HSI1 data */ + .pin_banks = exynosautov920_pin_banks3, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, { + /* pin-controller instance 4 HSI2 data */ + .pin_banks = exynosautov920_pin_banks4, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, { + /* pin-controller instance 5 HSI2UFS data */ + .pin_banks = exynosautov920_pin_banks5, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynosautov920_pin_banks6, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynosautov920_pin_banks7, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = exynosautov920_pinctrl_suspend, ++ .resume = exynosautov920_pinctrl_resume, + }, + }; + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c +index 62c8d8d907545..af4fb1cde8de9 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.c ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.c +@@ -761,105 +761,115 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) + return 0; + } + +-static void exynos_pinctrl_suspend_bank(struct samsung_pin_bank *bank) ++static void exynos_set_wakeup(struct samsung_pin_bank *bank) + { +- struct exynos_eint_gpio_save *save = bank->soc_priv; +- const void __iomem *regs = bank->eint_base; ++ struct exynos_irq_chip *irq_chip; + +- save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET +- + bank->eint_offset); +- save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset); +- save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset + 4); +- save->eint_mask = readl(regs + bank->irq_chip->eint_mask +- + bank->eint_offset); +- +- pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); +- pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); +- pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); +- pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); ++ if (bank->irq_chip) { ++ irq_chip = bank->irq_chip; ++ irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); ++ } + } + +-static void exynosauto_pinctrl_suspend_bank(struct samsung_pin_bank *bank) ++void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + const void __iomem *regs = bank->eint_base; + +- save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); +- save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); +- +- pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); +- pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset); ++ save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset); ++ save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset + 4); ++ save->eint_mask = readl(regs + bank->irq_chip->eint_mask ++ + bank->eint_offset); ++ ++ pr_debug("%s: save con %#010x\n", ++ bank->name, save->eint_con); ++ pr_debug("%s: save fltcon0 %#010x\n", ++ bank->name, save->eint_fltcon0); ++ pr_debug("%s: save fltcon1 %#010x\n", ++ bank->name, save->eint_fltcon1); ++ pr_debug("%s: save mask %#010x\n", ++ bank->name, save->eint_mask); ++ } else if (bank->eint_type == EINT_TYPE_WKUP) { ++ exynos_set_wakeup(bank); ++ } + } + +-void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) ++void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) + { +- struct exynos_irq_chip *irq_chip = NULL; ++ struct exynos_eint_gpio_save *save = bank->soc_priv; ++ const void __iomem *regs = bank->eint_base; + + if (bank->eint_type == EINT_TYPE_GPIO) { +- if (bank->eint_con_offset) +- exynosauto_pinctrl_suspend_bank(bank); +- else +- exynos_pinctrl_suspend_bank(bank); ++ save->eint_con = readl(regs + bank->pctl_offset + ++ bank->eint_con_offset); ++ save->eint_mask = readl(regs + bank->pctl_offset + ++ bank->eint_mask_offset); ++ pr_debug("%s: save con %#010x\n", ++ bank->name, save->eint_con); ++ pr_debug("%s: save mask %#010x\n", ++ bank->name, save->eint_mask); + } else if (bank->eint_type == EINT_TYPE_WKUP) { +- if (!irq_chip) { +- irq_chip = bank->irq_chip; +- irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); +- } ++ exynos_set_wakeup(bank); + } + } + +-static void exynos_pinctrl_resume_bank(struct samsung_pin_bank *bank) ++void exynos_pinctrl_resume(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + +- pr_debug("%s: con %#010x => %#010x\n", bank->name, +- readl(regs + EXYNOS_GPIO_ECON_OFFSET +- + bank->eint_offset), save->eint_con); +- pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, +- readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset), save->eint_fltcon0); +- pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, +- readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset + 4), save->eint_fltcon1); +- pr_debug("%s: mask %#010x => %#010x\n", bank->name, +- readl(regs + bank->irq_chip->eint_mask +- + bank->eint_offset), save->eint_mask); +- +- writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET +- + bank->eint_offset); +- writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset); +- writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET +- + 2 * bank->eint_offset + 4); +- writel(save->eint_mask, regs + bank->irq_chip->eint_mask +- + bank->eint_offset); ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ pr_debug("%s: con %#010x => %#010x\n", bank->name, ++ readl(regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset), save->eint_con); ++ pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, ++ readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset), save->eint_fltcon0); ++ pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, ++ readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset + 4), ++ save->eint_fltcon1); ++ pr_debug("%s: mask %#010x => %#010x\n", bank->name, ++ readl(regs + bank->irq_chip->eint_mask ++ + bank->eint_offset), save->eint_mask); ++ ++ writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset); ++ writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset); ++ writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + 2 * bank->eint_offset + 4); ++ writel(save->eint_mask, regs + bank->irq_chip->eint_mask ++ + bank->eint_offset); ++ } + } + +-static void exynosauto_pinctrl_resume_bank(struct samsung_pin_bank *bank) ++void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + +- pr_debug("%s: con %#010x => %#010x\n", bank->name, +- readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); +- pr_debug("%s: mask %#010x => %#010x\n", bank->name, +- readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask); +- +- writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); +- writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); +- +-} +- +-void exynos_pinctrl_resume(struct samsung_pin_bank *bank) +-{ + if (bank->eint_type == EINT_TYPE_GPIO) { +- if (bank->eint_con_offset) +- exynosauto_pinctrl_resume_bank(bank); +- else +- exynos_pinctrl_resume_bank(bank); ++ /* exynosautov920 has eint_con_offset for all but one bank */ ++ if (!bank->eint_con_offset) ++ exynos_pinctrl_resume(bank); ++ ++ pr_debug("%s: con %#010x => %#010x\n", bank->name, ++ readl(regs + bank->pctl_offset + bank->eint_con_offset), ++ save->eint_con); ++ pr_debug("%s: mask %#010x => %#010x\n", bank->name, ++ readl(regs + bank->pctl_offset + ++ bank->eint_mask_offset), save->eint_mask); ++ ++ writel(save->eint_con, ++ regs + bank->pctl_offset + bank->eint_con_offset); ++ writel(save->eint_mask, ++ regs + bank->pctl_offset + bank->eint_mask_offset); + } + } + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h +index ce39ab52102e7..837b737c6f0a7 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.h ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.h +@@ -211,6 +211,8 @@ struct exynos_muxed_weint_data { + + int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); + int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); ++void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); ++void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); + void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); + void exynos_pinctrl_resume(struct samsung_pin_bank *bank); + struct samsung_retention_ctrl * +-- +2.39.5 + diff --git a/queue-6.12/pinctrl-samsung-add-gs101-specific-eint-suspend-resu.patch b/queue-6.12/pinctrl-samsung-add-gs101-specific-eint-suspend-resu.patch new file mode 100644 index 0000000000..d7d468f6a0 --- /dev/null +++ b/queue-6.12/pinctrl-samsung-add-gs101-specific-eint-suspend-resu.patch @@ -0,0 +1,196 @@ +From 0f0abc4bbd369d2819aa7b3a27e048525add08be Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 2 Apr 2025 16:17:32 +0100 +Subject: pinctrl: samsung: add gs101 specific eint suspend/resume callbacks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Peter Griffin + +[ Upstream commit bdbe0a0f71003b997d6a2dbe4bc7b5b0438207c7 ] + +gs101 differs to other SoCs in that fltcon1 register doesn't +always exist. Additionally the offset of fltcon0 is not fixed +and needs to use the newly added eint_fltcon_offset variable. + +Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") +Cc: stable@vger.kernel.org # depends on the previous three patches +Reviewed-by: André Draszik +Signed-off-by: Peter Griffin +Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-3-78ce0d4eb30c@linaro.org +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Sasha Levin +--- + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 24 +++---- + drivers/pinctrl/samsung/pinctrl-exynos.c | 71 +++++++++++++++++++ + drivers/pinctrl/samsung/pinctrl-exynos.h | 2 + + 3 files changed, 85 insertions(+), 12 deletions(-) + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +index ce61a85c7784a..a2ac1702d0dfa 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c ++++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +@@ -1024,15 +1024,15 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { + .pin_banks = gs101_pin_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_alive), + .eint_wkup_init = exynos_eint_wkup_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ + .pin_banks = gs101_pin_far_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), + .eint_wkup_init = exynos_eint_wkup_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (GSACORE) */ + .pin_banks = gs101_pin_gsacore, +@@ -1046,29 +1046,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { + .pin_banks = gs101_pin_peric0, + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (PERIC1) */ + .pin_banks = gs101_pin_peric1, + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI1) */ + .pin_banks = gs101_pin_hsi1, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI2) */ + .pin_banks = gs101_pin_hsi2, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), + .eint_gpio_init = exynos_eint_gpio_init, +- .suspend = exynos_pinctrl_suspend, +- .resume = exynos_pinctrl_resume, ++ .suspend = gs101_pinctrl_suspend, ++ .resume = gs101_pinctrl_resume, + }, + }; + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c +index af4fb1cde8de9..7887fd4166511 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.c ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.c +@@ -799,6 +799,41 @@ void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) + } + } + ++void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) ++{ ++ struct exynos_eint_gpio_save *save = bank->soc_priv; ++ const void __iomem *regs = bank->eint_base; ++ ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset); ++ ++ save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + bank->eint_fltcon_offset); ++ ++ /* fltcon1 register only exists for pins 4-7 */ ++ if (bank->nr_pins > 4) ++ save->eint_fltcon1 = readl(regs + ++ EXYNOS_GPIO_EFLTCON_OFFSET ++ + bank->eint_fltcon_offset + 4); ++ ++ save->eint_mask = readl(regs + bank->irq_chip->eint_mask ++ + bank->eint_offset); ++ ++ pr_debug("%s: save con %#010x\n", ++ bank->name, save->eint_con); ++ pr_debug("%s: save fltcon0 %#010x\n", ++ bank->name, save->eint_fltcon0); ++ if (bank->nr_pins > 4) ++ pr_debug("%s: save fltcon1 %#010x\n", ++ bank->name, save->eint_fltcon1); ++ pr_debug("%s: save mask %#010x\n", ++ bank->name, save->eint_mask); ++ } else if (bank->eint_type == EINT_TYPE_WKUP) { ++ exynos_set_wakeup(bank); ++ } ++} ++ + void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; +@@ -818,6 +853,42 @@ void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) + } + } + ++void gs101_pinctrl_resume(struct samsung_pin_bank *bank) ++{ ++ struct exynos_eint_gpio_save *save = bank->soc_priv; ++ ++ void __iomem *regs = bank->eint_base; ++ void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET ++ + bank->eint_fltcon_offset; ++ ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ pr_debug("%s: con %#010x => %#010x\n", bank->name, ++ readl(regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset), save->eint_con); ++ ++ pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, ++ readl(eint_fltcfg0), save->eint_fltcon0); ++ ++ /* fltcon1 register only exists for pins 4-7 */ ++ if (bank->nr_pins > 4) ++ pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, ++ readl(eint_fltcfg0 + 4), save->eint_fltcon1); ++ ++ pr_debug("%s: mask %#010x => %#010x\n", bank->name, ++ readl(regs + bank->irq_chip->eint_mask ++ + bank->eint_offset), save->eint_mask); ++ ++ writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET ++ + bank->eint_offset); ++ writel(save->eint_fltcon0, eint_fltcfg0); ++ ++ if (bank->nr_pins > 4) ++ writel(save->eint_fltcon1, eint_fltcfg0 + 4); ++ writel(save->eint_mask, regs + bank->irq_chip->eint_mask ++ + bank->eint_offset); ++ } ++} ++ + void exynos_pinctrl_resume(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h +index 837b737c6f0a7..c70b8ead56b4b 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.h ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.h +@@ -215,6 +215,8 @@ void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); + void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); + void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); + void exynos_pinctrl_resume(struct samsung_pin_bank *bank); ++void gs101_pinctrl_suspend(struct samsung_pin_bank *bank); ++void gs101_pinctrl_resume(struct samsung_pin_bank *bank); + struct samsung_retention_ctrl * + exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data); +-- +2.39.5 + diff --git a/queue-6.12/pinctrl-samsung-refactor-drvdata-suspend-resume-call.patch b/queue-6.12/pinctrl-samsung-refactor-drvdata-suspend-resume-call.patch new file mode 100644 index 0000000000..75ab16ce9b --- /dev/null +++ b/queue-6.12/pinctrl-samsung-refactor-drvdata-suspend-resume-call.patch @@ -0,0 +1,297 @@ +From f79a384f928cca03353efded8a2e583d37eca708 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 2 Apr 2025 16:17:30 +0100 +Subject: pinctrl: samsung: refactor drvdata suspend & resume callbacks + +From: Peter Griffin + +[ Upstream commit 3ade961e97f3b05dcdd9a4fabfe179c9e75571e0 ] + +This enables the clk_enable() and clk_disable() logic to be removed +from each callback, but otherwise should have no functional impact. + +It is a prepatory patch so that the callbacks can become SoC +specific. + +Signed-off-by: Peter Griffin +Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-1-78ce0d4eb30c@linaro.org +Signed-off-by: Krzysztof Kozlowski +Stable-dep-of: bdbe0a0f7100 ("pinctrl: samsung: add gs101 specific eint suspend/resume callbacks") +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++----------------- + drivers/pinctrl/samsung/pinctrl-exynos.h | 4 +- + drivers/pinctrl/samsung/pinctrl-samsung.c | 21 ++++-- + drivers/pinctrl/samsung/pinctrl-samsung.h | 8 +- + 4 files changed, 42 insertions(+), 80 deletions(-) + +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c +index ac6dc22b37c98..62c8d8d907545 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.c ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.c +@@ -761,19 +761,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) + return 0; + } + +-static void exynos_pinctrl_suspend_bank( +- struct samsung_pinctrl_drv_data *drvdata, +- struct samsung_pin_bank *bank) ++static void exynos_pinctrl_suspend_bank(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + const void __iomem *regs = bank->eint_base; + +- if (clk_enable(bank->drvdata->pclk)) { +- dev_err(bank->gpio_chip.parent, +- "unable to enable clock for saving state\n"); +- return; +- } +- + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET +@@ -783,71 +775,46 @@ static void exynos_pinctrl_suspend_bank( + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + +- clk_disable(bank->drvdata->pclk); +- + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); + } + +-static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata, +- struct samsung_pin_bank *bank) ++static void exynosauto_pinctrl_suspend_bank(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + const void __iomem *regs = bank->eint_base; + +- if (clk_enable(bank->drvdata->pclk)) { +- dev_err(bank->gpio_chip.parent, +- "unable to enable clock for saving state\n"); +- return; +- } +- + save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); + save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); + +- clk_disable(bank->drvdata->pclk); +- + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); + } + +-void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) ++void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) + { +- struct samsung_pin_bank *bank = drvdata->pin_banks; + struct exynos_irq_chip *irq_chip = NULL; +- int i; + +- for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { +- if (bank->eint_type == EINT_TYPE_GPIO) { +- if (bank->eint_con_offset) +- exynosauto_pinctrl_suspend_bank(drvdata, bank); +- else +- exynos_pinctrl_suspend_bank(drvdata, bank); +- } +- else if (bank->eint_type == EINT_TYPE_WKUP) { +- if (!irq_chip) { +- irq_chip = bank->irq_chip; +- irq_chip->set_eint_wakeup_mask(drvdata, +- irq_chip); +- } ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ if (bank->eint_con_offset) ++ exynosauto_pinctrl_suspend_bank(bank); ++ else ++ exynos_pinctrl_suspend_bank(bank); ++ } else if (bank->eint_type == EINT_TYPE_WKUP) { ++ if (!irq_chip) { ++ irq_chip = bank->irq_chip; ++ irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); + } + } + } + +-static void exynos_pinctrl_resume_bank( +- struct samsung_pinctrl_drv_data *drvdata, +- struct samsung_pin_bank *bank) ++static void exynos_pinctrl_resume_bank(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + +- if (clk_enable(bank->drvdata->pclk)) { +- dev_err(bank->gpio_chip.parent, +- "unable to enable clock for restoring state\n"); +- return; +- } +- + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); +@@ -869,22 +836,13 @@ static void exynos_pinctrl_resume_bank( + + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); +- +- clk_disable(bank->drvdata->pclk); + } + +-static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata, +- struct samsung_pin_bank *bank) ++static void exynosauto_pinctrl_resume_bank(struct samsung_pin_bank *bank) + { + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + +- if (clk_enable(bank->drvdata->pclk)) { +- dev_err(bank->gpio_chip.parent, +- "unable to enable clock for restoring state\n"); +- return; +- } +- + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, +@@ -893,21 +851,16 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd + writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); + writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); + +- clk_disable(bank->drvdata->pclk); + } + +-void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) ++void exynos_pinctrl_resume(struct samsung_pin_bank *bank) + { +- struct samsung_pin_bank *bank = drvdata->pin_banks; +- int i; +- +- for (i = 0; i < drvdata->nr_banks; ++i, ++bank) +- if (bank->eint_type == EINT_TYPE_GPIO) { +- if (bank->eint_con_offset) +- exynosauto_pinctrl_resume_bank(drvdata, bank); +- else +- exynos_pinctrl_resume_bank(drvdata, bank); +- } ++ if (bank->eint_type == EINT_TYPE_GPIO) { ++ if (bank->eint_con_offset) ++ exynosauto_pinctrl_resume_bank(bank); ++ else ++ exynos_pinctrl_resume_bank(bank); ++ } + } + + static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) +diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h +index 97a43fa4dfc56..ce39ab52102e7 100644 +--- a/drivers/pinctrl/samsung/pinctrl-exynos.h ++++ b/drivers/pinctrl/samsung/pinctrl-exynos.h +@@ -211,8 +211,8 @@ struct exynos_muxed_weint_data { + + int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); + int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); +-void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); +-void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); ++void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); ++void exynos_pinctrl_resume(struct samsung_pin_bank *bank); + struct samsung_retention_ctrl * + exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data); +diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c +index 63ac89a802d30..210534586c0c0 100644 +--- a/drivers/pinctrl/samsung/pinctrl-samsung.c ++++ b/drivers/pinctrl/samsung/pinctrl-samsung.c +@@ -1333,6 +1333,7 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) + static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) + { + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); ++ struct samsung_pin_bank *bank; + int i; + + i = clk_enable(drvdata->pclk); +@@ -1343,7 +1344,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) + } + + for (i = 0; i < drvdata->nr_banks; i++) { +- struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; ++ bank = &drvdata->pin_banks[i]; + const void __iomem *reg = bank->pctl_base + bank->pctl_offset; + const u8 *offs = bank->type->reg_offset; + const u8 *widths = bank->type->fld_width; +@@ -1371,10 +1372,14 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) + } + } + ++ for (i = 0; i < drvdata->nr_banks; i++) { ++ bank = &drvdata->pin_banks[i]; ++ if (drvdata->suspend) ++ drvdata->suspend(bank); ++ } ++ + clk_disable(drvdata->pclk); + +- if (drvdata->suspend) +- drvdata->suspend(drvdata); + if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) + drvdata->retention_ctrl->enable(drvdata); + +@@ -1392,6 +1397,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) + static int __maybe_unused samsung_pinctrl_resume(struct device *dev) + { + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); ++ struct samsung_pin_bank *bank; + int ret; + int i; + +@@ -1406,11 +1412,14 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev) + return ret; + } + +- if (drvdata->resume) +- drvdata->resume(drvdata); ++ for (i = 0; i < drvdata->nr_banks; i++) { ++ bank = &drvdata->pin_banks[i]; ++ if (drvdata->resume) ++ drvdata->resume(bank); ++ } + + for (i = 0; i < drvdata->nr_banks; i++) { +- struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; ++ bank = &drvdata->pin_banks[i]; + void __iomem *reg = bank->pctl_base + bank->pctl_offset; + const u8 *offs = bank->type->reg_offset; + const u8 *widths = bank->type->fld_width; +diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h +index 14c3b6b965851..7ffd2e193e425 100644 +--- a/drivers/pinctrl/samsung/pinctrl-samsung.h ++++ b/drivers/pinctrl/samsung/pinctrl-samsung.h +@@ -285,8 +285,8 @@ struct samsung_pin_ctrl { + int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); + int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); + void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata); +- void (*suspend)(struct samsung_pinctrl_drv_data *); +- void (*resume)(struct samsung_pinctrl_drv_data *); ++ void (*suspend)(struct samsung_pin_bank *bank); ++ void (*resume)(struct samsung_pin_bank *bank); + }; + + /** +@@ -335,8 +335,8 @@ struct samsung_pinctrl_drv_data { + + struct samsung_retention_ctrl *retention_ctrl; + +- void (*suspend)(struct samsung_pinctrl_drv_data *); +- void (*resume)(struct samsung_pinctrl_drv_data *); ++ void (*suspend)(struct samsung_pin_bank *bank); ++ void (*resume)(struct samsung_pin_bank *bank); + }; + + /** +-- +2.39.5 + diff --git a/queue-6.12/pmdomain-core-introduce-dev_pm_genpd_rpm_always_on.patch b/queue-6.12/pmdomain-core-introduce-dev_pm_genpd_rpm_always_on.patch new file mode 100644 index 0000000000..9f183c9449 --- /dev/null +++ b/queue-6.12/pmdomain-core-introduce-dev_pm_genpd_rpm_always_on.patch @@ -0,0 +1,118 @@ +From e9ae6c26434f8006fd571c8b06d99650e57ee985 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Feb 2025 14:15:52 +0800 +Subject: pmdomain: core: Introduce dev_pm_genpd_rpm_always_on() + +From: Ulf Hansson + +[ Upstream commit cd3fa304ba5c93ce57b9b55b3cd893af2be96527 ] + +For some usecases a consumer driver requires its device to remain power-on +from the PM domain perspective during runtime. Using dev PM qos along with +the genpd governors, doesn't work for this case as would potentially +prevent the device from being runtime suspended too. + +To support these usecases, let's introduce dev_pm_genpd_rpm_always_on() to +allow consumers drivers to dynamically control the behaviour in genpd for a +device that is attached to it. + +Signed-off-by: Ulf Hansson +Signed-off-by: Shawn Lin +Acked-by: Manivannan Sadhasivam +Link: https://lore.kernel.org/r/1738736156-119203-4-git-send-email-shawn.lin@rock-chips.com +Signed-off-by: Ulf Hansson +Stable-dep-of: 08f959759e1e ("mmc: sdhci-of-dwcmshc: add PD workaround on RK3576") +Signed-off-by: Sasha Levin +--- + drivers/pmdomain/core.c | 35 +++++++++++++++++++++++++++++++++++ + include/linux/pm_domain.h | 7 +++++++ + 2 files changed, 42 insertions(+) + +diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c +index 05913e9fe0821..8b1f894f5e790 100644 +--- a/drivers/pmdomain/core.c ++++ b/drivers/pmdomain/core.c +@@ -697,6 +697,37 @@ bool dev_pm_genpd_get_hwmode(struct device *dev) + } + EXPORT_SYMBOL_GPL(dev_pm_genpd_get_hwmode); + ++/** ++ * dev_pm_genpd_rpm_always_on() - Control if the PM domain can be powered off. ++ * ++ * @dev: Device for which the PM domain may need to stay on for. ++ * @on: Value to set or unset for the condition. ++ * ++ * For some usecases a consumer driver requires its device to remain power-on ++ * from the PM domain perspective during runtime. This function allows the ++ * behaviour to be dynamically controlled for a device attached to a genpd. ++ * ++ * It is assumed that the users guarantee that the genpd wouldn't be detached ++ * while this routine is getting called. ++ * ++ * Return: Returns 0 on success and negative error values on failures. ++ */ ++int dev_pm_genpd_rpm_always_on(struct device *dev, bool on) ++{ ++ struct generic_pm_domain *genpd; ++ ++ genpd = dev_to_genpd_safe(dev); ++ if (!genpd) ++ return -ENODEV; ++ ++ genpd_lock(genpd); ++ dev_gpd_data(dev)->rpm_always_on = on; ++ genpd_unlock(genpd); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(dev_pm_genpd_rpm_always_on); ++ + static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) + { + unsigned int state_idx = genpd->state_idx; +@@ -868,6 +899,10 @@ static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on, + if (!pm_runtime_suspended(pdd->dev) || + irq_safe_dev_in_sleep_domain(pdd->dev, genpd)) + not_suspended++; ++ ++ /* The device may need its PM domain to stay powered on. */ ++ if (to_gpd_data(pdd)->rpm_always_on) ++ return -EBUSY; + } + + if (not_suspended > 1 || (not_suspended == 1 && !one_dev_on)) +diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h +index cf4b11be37097..c6716f474ba45 100644 +--- a/include/linux/pm_domain.h ++++ b/include/linux/pm_domain.h +@@ -251,6 +251,7 @@ struct generic_pm_domain_data { + unsigned int default_pstate; + unsigned int rpm_pstate; + bool hw_mode; ++ bool rpm_always_on; + void *data; + }; + +@@ -283,6 +284,7 @@ ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev); + void dev_pm_genpd_synced_poweroff(struct device *dev); + int dev_pm_genpd_set_hwmode(struct device *dev, bool enable); + bool dev_pm_genpd_get_hwmode(struct device *dev); ++int dev_pm_genpd_rpm_always_on(struct device *dev, bool on); + + extern struct dev_power_governor simple_qos_governor; + extern struct dev_power_governor pm_domain_always_on_gov; +@@ -366,6 +368,11 @@ static inline bool dev_pm_genpd_get_hwmode(struct device *dev) + return false; + } + ++static inline int dev_pm_genpd_rpm_always_on(struct device *dev, bool on) ++{ ++ return -EOPNOTSUPP; ++} ++ + #define simple_qos_governor (*(struct dev_power_governor *)(NULL)) + #define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL)) + #endif +-- +2.39.5 + diff --git a/queue-6.12/serial-sh-sci-clean-sci_ports-0-after-at-earlycon-ex.patch b/queue-6.12/serial-sh-sci-clean-sci_ports-0-after-at-earlycon-ex.patch new file mode 100644 index 0000000000..2b7633daa3 --- /dev/null +++ b/queue-6.12/serial-sh-sci-clean-sci_ports-0-after-at-earlycon-ex.patch @@ -0,0 +1,122 @@ +From 848409217e96d5afac6089bba4da9fc8dacfafca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Jan 2025 20:22:48 +0200 +Subject: serial: sh-sci: Clean sci_ports[0] after at earlycon exit + +From: Claudiu Beznea + +[ Upstream commit 3791ea69a4858b81e0277f695ca40f5aae40f312 ] + +The early_console_setup() function initializes the sci_ports[0].port with +an object of type struct uart_port obtained from the object of type +struct earlycon_device received as argument by the early_console_setup(). + +It may happen that later, when the rest of the serial ports are probed, +the serial port that was used as earlycon (e.g., port A) to be mapped to a +different position in sci_ports[] and the slot 0 to be used by a different +serial port (e.g., port B), as follows: + +sci_ports[0] = port A +sci_ports[X] = port B + +In this case, the new port mapped at index zero will have associated data +that was used for earlycon. + +In case this happens, after Linux boot, any access to the serial port that +maps on sci_ports[0] (port A) will block the serial port that was used as +earlycon (port B). + +To fix this, add early_console_exit() that clean the sci_ports[0] at +earlycon exit time. + +Fixes: 0b0cced19ab1 ("serial: sh-sci: Add CONFIG_SERIAL_EARLYCON support") +Cc: stable@vger.kernel.org +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20241106120118.1719888-4-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/sh-sci.c | 32 ++++++++++++++++++++++++++++++-- + 1 file changed, 30 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index aacbed76c7c54..519a48f89f20e 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -183,6 +183,7 @@ static struct sci_port sci_ports[SCI_NPORTS]; + static unsigned long sci_ports_in_use; + static struct uart_driver sci_uart_driver; + static bool sci_uart_earlycon; ++static bool sci_uart_earlycon_dev_probing; + + static inline struct sci_port * + to_sci_port(struct uart_port *uart) +@@ -3404,7 +3405,8 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, + static int sci_probe_single(struct platform_device *dev, + unsigned int index, + struct plat_sci_port *p, +- struct sci_port *sciport) ++ struct sci_port *sciport, ++ struct resource *sci_res) + { + int ret; + +@@ -3451,6 +3453,14 @@ static int sci_probe_single(struct platform_device *dev, + sciport->port.flags |= UPF_HARD_FLOW; + } + ++ if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { ++ /* ++ * Skip cleanup the sci_port[0] in early_console_exit(), this ++ * port is the same as the earlycon one. ++ */ ++ sci_uart_earlycon_dev_probing = true; ++ } ++ + return uart_add_one_port(&sci_uart_driver, &sciport->port); + } + +@@ -3509,7 +3519,7 @@ static int sci_probe(struct platform_device *dev) + + platform_set_drvdata(dev, sp); + +- ret = sci_probe_single(dev, dev_id, p, sp); ++ ret = sci_probe_single(dev, dev_id, p, sp, res); + if (ret) + return ret; + +@@ -3666,6 +3676,22 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver, + #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON + static struct plat_sci_port port_cfg; + ++static int early_console_exit(struct console *co) ++{ ++ struct sci_port *sci_port = &sci_ports[0]; ++ ++ /* ++ * Clean the slot used by earlycon. A new SCI device might ++ * map to this slot. ++ */ ++ if (!sci_uart_earlycon_dev_probing) { ++ memset(sci_port, 0, sizeof(*sci_port)); ++ sci_uart_earlycon = false; ++ } ++ ++ return 0; ++} ++ + static int __init early_console_setup(struct earlycon_device *device, + int type) + { +@@ -3683,6 +3709,8 @@ static int __init early_console_setup(struct earlycon_device *device, + SCSCR_RE | SCSCR_TE | port_cfg.scscr); + + device->con->write = serial_console_write; ++ device->con->exit = early_console_exit; ++ + return 0; + } + static int __init sci_early_console_setup(struct earlycon_device *device, +-- +2.39.5 + diff --git a/queue-6.12/serial-sh-sci-increment-the-runtime-usage-counter-fo.patch b/queue-6.12/serial-sh-sci-increment-the-runtime-usage-counter-fo.patch new file mode 100644 index 0000000000..1598a09433 --- /dev/null +++ b/queue-6.12/serial-sh-sci-increment-the-runtime-usage-counter-fo.patch @@ -0,0 +1,91 @@ +From 44fc2adc5e237c2241c09bc469bdfd5d7484b647 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Jan 2025 20:22:49 +0200 +Subject: serial: sh-sci: Increment the runtime usage counter for the earlycon + device + +From: Claudiu Beznea + +[ Upstream commit 651dee03696e1dfde6d9a7e8664bbdcd9a10ea7f ] + +In the sh-sci driver, serial ports are mapped to the sci_ports[] array, +with earlycon mapped at index zero. + +The uart_add_one_port() function eventually calls __device_attach(), +which, in turn, calls pm_request_idle(). The identified code path is as +follows: + +uart_add_one_port() -> + serial_ctrl_register_port() -> + serial_core_register_port() -> + serial_core_port_device_add() -> + serial_base_port_add() -> + device_add() -> + bus_probe_device() -> + device_initial_probe() -> + __device_attach() -> + // ... + if (dev->p->dead) { + // ... + } else if (dev->driver) { + // ... + } else { + // ... + pm_request_idle(dev); + // ... + } + +The earlycon device clocks are enabled by the bootloader. However, the +pm_request_idle() call in __device_attach() disables the SCI port clocks +while earlycon is still active. + +The earlycon write function, serial_console_write(), calls +sci_poll_put_char() via serial_console_putchar(). If the SCI port clocks +are disabled, writing to earlycon may sometimes cause the SR.TDFE bit to +remain unset indefinitely, causing the while loop in sci_poll_put_char() +to never exit. On single-core SoCs, this can result in the system being +blocked during boot when this issue occurs. + +To resolve this, increment the runtime PM usage counter for the earlycon +SCI device before registering the UART port. + +Fixes: 0b0cced19ab1 ("serial: sh-sci: Add CONFIG_SERIAL_EARLYCON support") +Cc: stable@vger.kernel.org +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20250116182249.3828577-6-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/sh-sci.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index 519a48f89f20e..53236e3e4fa47 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -3454,6 +3454,22 @@ static int sci_probe_single(struct platform_device *dev, + } + + if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { ++ /* ++ * In case: ++ * - this is the earlycon port (mapped on index 0 in sci_ports[]) and ++ * - it now maps to an alias other than zero and ++ * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is ++ * available in bootargs) ++ * ++ * we need to avoid disabling clocks and PM domains through the runtime ++ * PM APIs called in __device_attach(). For this, increment the runtime ++ * PM reference counter (the clocks and PM domains were already enabled ++ * by the bootloader). Otherwise the earlycon may access the HW when it ++ * has no clocks enabled leading to failures (infinite loop in ++ * sci_poll_put_char()). ++ */ ++ pm_runtime_get_noresume(&dev->dev); ++ + /* + * Skip cleanup the sci_port[0] in early_console_exit(), this + * port is the same as the earlycon one. +-- +2.39.5 + diff --git a/queue-6.12/serial-sh-sci-move-runtime-pm-enable-to-sci_probe_si.patch b/queue-6.12/serial-sh-sci-move-runtime-pm-enable-to-sci_probe_si.patch new file mode 100644 index 0000000000..72e06e1a82 --- /dev/null +++ b/queue-6.12/serial-sh-sci-move-runtime-pm-enable-to-sci_probe_si.patch @@ -0,0 +1,92 @@ +From 083ca6d4304c4714e0f3b539a830c0c7bba517da Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Jan 2025 20:22:46 +0200 +Subject: serial: sh-sci: Move runtime PM enable to sci_probe_single() + +From: Claudiu Beznea + +[ Upstream commit 239f11209e5f282e16f5241b99256e25dd0614b6 ] + +Relocate the runtime PM enable operation to sci_probe_single(). This change +prepares the codebase for upcoming fixes. + +While at it, replace the existing logic with a direct call to +devm_pm_runtime_enable() and remove sci_cleanup_single(). The +devm_pm_runtime_enable() function automatically handles disabling runtime +PM during driver removal. + +Reviewed-by: Geert Uytterhoeven +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20250116182249.3828577-3-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/sh-sci.c | 24 ++++++------------------ + 1 file changed, 6 insertions(+), 18 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index 76cf177b040eb..aacbed76c7c54 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -3074,10 +3074,6 @@ static int sci_init_single(struct platform_device *dev, + ret = sci_init_clocks(sci_port, &dev->dev); + if (ret < 0) + return ret; +- +- port->dev = &dev->dev; +- +- pm_runtime_enable(&dev->dev); + } + + port->type = p->type; +@@ -3104,11 +3100,6 @@ static int sci_init_single(struct platform_device *dev, + return 0; + } + +-static void sci_cleanup_single(struct sci_port *port) +-{ +- pm_runtime_disable(port->port.dev); +-} +- + #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ + defined(CONFIG_SERIAL_SH_SCI_EARLYCON) + static void serial_console_putchar(struct uart_port *port, unsigned char ch) +@@ -3278,8 +3269,6 @@ static void sci_remove(struct platform_device *dev) + sci_ports_in_use &= ~BIT(port->port.line); + uart_remove_one_port(&sci_uart_driver, &port->port); + +- sci_cleanup_single(port); +- + if (port->port.fifosize > 1) + device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) +@@ -3444,6 +3433,11 @@ static int sci_probe_single(struct platform_device *dev, + if (ret) + return ret; + ++ sciport->port.dev = &dev->dev; ++ ret = devm_pm_runtime_enable(&dev->dev); ++ if (ret) ++ return ret; ++ + sciport->gpios = mctrl_gpio_init(&sciport->port, 0); + if (IS_ERR(sciport->gpios)) + return PTR_ERR(sciport->gpios); +@@ -3457,13 +3451,7 @@ static int sci_probe_single(struct platform_device *dev, + sciport->port.flags |= UPF_HARD_FLOW; + } + +- ret = uart_add_one_port(&sci_uart_driver, &sciport->port); +- if (ret) { +- sci_cleanup_single(sciport); +- return ret; +- } +- +- return 0; ++ return uart_add_one_port(&sci_uart_driver, &sciport->port); + } + + static int sci_probe(struct platform_device *dev) +-- +2.39.5 + diff --git a/queue-6.12/series b/queue-6.12/series index dbee420f20..37b9c59a45 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -395,3 +395,28 @@ path_overmount-avoid-false-negatives.patch fix-propagation-graph-breakage-by-move_mount_set_gro.patch do_change_type-refuse-to-operate-on-unmounted-not-ou.patch tools-power-turbostat-fix-amd-package-energy-reporti.patch +drm-amd-pm-add-inst-to-dpm_set_vcn_enable.patch +drm-amd-pm-power-up-or-down-vcn-by-instance.patch +drm-amdgpu-read-back-register-after-written-for-vcn-.patch +alsa-hda-tas2781-add-tas2781-hda-spi-driver.patch +alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch +alsa-hda-realtek-fix-micmute-leds-on-hp-laptops-with.patch-23213 +alsa-hda-realtek-add-support-for-various-hp-laptops-.patch +alsa-hda-realtek-support-mute-led-function-for-hp-pl.patch +alsa-hda-realtek-add-new-hp-zbook-laptop-with-micmut.patch +alsa-hda-realtek-add-support-for-hp-agusta-using-cs3.patch +input-synaptics-rmi-fix-crash-with-unsupported-versi.patch +pmdomain-core-introduce-dev_pm_genpd_rpm_always_on.patch +mmc-sdhci-of-dwcmshc-add-pd-workaround-on-rk3576.patch +kasan-avoid-sleepable-page-allocation-from-atomic-co.patch +arm64-dts-qcom-x1e80100-apply-consistent-critical-th.patch +arm64-dts-qcom-x1e80100-add-gpu-cooling.patch +pinctrl-samsung-refactor-drvdata-suspend-resume-call.patch +pinctrl-samsung-add-dedicated-soc-eint-suspend-resum.patch +pinctrl-samsung-add-gs101-specific-eint-suspend-resu.patch +dt-bindings-pwm-adi-axi-pwmgen-increase-pwm-cells-to.patch +dt-bindings-pwm-correct-indentation-and-style-in-dts.patch +dt-bindings-pwm-adi-axi-pwmgen-fix-clocks.patch +serial-sh-sci-move-runtime-pm-enable-to-sci_probe_si.patch +serial-sh-sci-clean-sci_ports-0-after-at-earlycon-ex.patch +serial-sh-sci-increment-the-runtime-usage-counter-fo.patch