From: Fabiano Rosas <farosas@linux.ibm.com>
Date: Fri, 28 Jan 2022 12:15:05 +0000 (+0100)
Subject: target/ppc: 405: Instruction storage interrupt cleanup
X-Git-Tag: v7.0.0-rc0~69^2~16
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=35f579f5c21682311039f84e2e81254937e6ff78;p=thirdparty%2Fqemu.git

target/ppc: 405: Instruction storage interrupt cleanup

The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : Fixed removal which was done in the wrong routine ]
Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index deba12f4f36..7d89bd0651d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -469,7 +469,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
         break;
     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
         trace_ppc_excp_isi(msr, env->nip);
-        msr |= env->error_code;
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
         break;