From: Greg Kroah-Hartman Date: Sat, 15 Apr 2023 07:00:29 +0000 (+0200) Subject: 6.2-stable patches X-Git-Tag: v4.14.313~67 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=35ff2085d9a96f9f2d63f251954bf5fa32235e24;p=thirdparty%2Fkernel%2Fstable-queue.git 6.2-stable patches added patches: drm-amd-display-pass-the-right-info-to-drm_dp_remove_payload.patch drm-i915-workaround-icl-csc_mode-sticky-arming.patch revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch series --- diff --git a/queue-6.2/drm-amd-display-pass-the-right-info-to-drm_dp_remove_payload.patch b/queue-6.2/drm-amd-display-pass-the-right-info-to-drm_dp_remove_payload.patch new file mode 100644 index 00000000000..9defcb89f8c --- /dev/null +++ b/queue-6.2/drm-amd-display-pass-the-right-info-to-drm_dp_remove_payload.patch @@ -0,0 +1,114 @@ +From b8ca445f550a9a079134f836466ddda3bfad6108 Mon Sep 17 00:00:00 2001 +From: Wayne Lin +Date: Fri, 17 Feb 2023 13:26:56 +0800 +Subject: drm/amd/display: Pass the right info to drm_dp_remove_payload + +From: Wayne Lin + +commit b8ca445f550a9a079134f836466ddda3bfad6108 upstream. + +[Why & How] +drm_dp_remove_payload() interface was changed. Correct amdgpu dm code +to pass the right parameter to the drm helper function. + +Reviewed-by: Jerry Zuo +Acked-by: Qingqing Zhuo +Signed-off-by: Wayne Lin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +(cherry-picked from b8ca445f550a9a079134f836466ddda3bfad6108) +[Hand modified due to missing f0127cb11299df80df45583b216e13f27c408545 which + failed to apply due to missing 94dfeaa46925bb6b4d43645bbb6234e846dec257] +Reported-and-tested-by: Veronika Schwan +Fixes: d7b5638bd337 ("drm/amd/display: Take FEC Overhead into Timeslot Calculation") +Signed-off-by: Mario Limonciello +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 57 ++++++++++++-- + 1 file changed, 50 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -175,6 +175,40 @@ void dm_helpers_dp_update_branch_info( + const struct dc_link *link) + {} + ++static void dm_helpers_construct_old_payload( ++ struct dc_link *link, ++ int pbn_per_slot, ++ struct drm_dp_mst_atomic_payload *new_payload, ++ struct drm_dp_mst_atomic_payload *old_payload) ++{ ++ struct link_mst_stream_allocation_table current_link_table = ++ link->mst_stream_alloc_table; ++ struct link_mst_stream_allocation *dc_alloc; ++ int i; ++ ++ *old_payload = *new_payload; ++ ++ /* Set correct time_slots/PBN of old payload. ++ * other fields (delete & dsc_enabled) in ++ * struct drm_dp_mst_atomic_payload are don't care fields ++ * while calling drm_dp_remove_payload() ++ */ ++ for (i = 0; i < current_link_table.stream_count; i++) { ++ dc_alloc = ++ ¤t_link_table.stream_allocations[i]; ++ ++ if (dc_alloc->vcp_id == new_payload->vcpi) { ++ old_payload->time_slots = dc_alloc->slot_count; ++ old_payload->pbn = dc_alloc->slot_count * pbn_per_slot; ++ break; ++ } ++ } ++ ++ /* make sure there is an old payload*/ ++ ASSERT(i != current_link_table.stream_count); ++ ++} ++ + /* + * Writes payload allocation table in immediate downstream device. + */ +@@ -186,7 +220,7 @@ bool dm_helpers_dp_mst_write_payload_all + { + struct amdgpu_dm_connector *aconnector; + struct drm_dp_mst_topology_state *mst_state; +- struct drm_dp_mst_atomic_payload *payload; ++ struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; + struct drm_dp_mst_topology_mgr *mst_mgr; + + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; +@@ -202,17 +236,26 @@ bool dm_helpers_dp_mst_write_payload_all + mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); + + /* It's OK for this to fail */ +- payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); +- if (enable) +- drm_dp_add_payload_part1(mst_mgr, mst_state, payload); +- else +- drm_dp_remove_payload(mst_mgr, mst_state, payload, payload); ++ new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); ++ ++ if (enable) { ++ target_payload = new_payload; ++ ++ drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); ++ } else { ++ /* construct old payload by VCPI*/ ++ dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div, ++ new_payload, &old_payload); ++ target_payload = &old_payload; ++ ++ drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); ++ } + + /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ +- fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table); ++ fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); + + return true; + } diff --git a/queue-6.2/drm-i915-workaround-icl-csc_mode-sticky-arming.patch b/queue-6.2/drm-i915-workaround-icl-csc_mode-sticky-arming.patch new file mode 100644 index 00000000000..d23d45fa31d --- /dev/null +++ b/queue-6.2/drm-i915-workaround-icl-csc_mode-sticky-arming.patch @@ -0,0 +1,117 @@ +From 4d4e766f8b7dbdefa7a78e91eb9c7a29d0d818b8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 20 Mar 2023 11:54:36 +0200 +Subject: drm/i915: Workaround ICL CSC_MODE sticky arming +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 4d4e766f8b7dbdefa7a78e91eb9c7a29d0d818b8 upstream. + +Unlike SKL/GLK the ICL CSC unit suffers from a new issue where +CSC_MODE arming is sticky. That is, once armed it remains armed +causing the CSC coeff/offset registers to become effectively +self-arming. + +CSC coeff/offset registers writes no longer disarm the CSC, +but fortunately register read still do. So we can use that +to disarm the CSC unit once the registers for the current +frame have been latched. This avoid s the self-arming behaviour +from persisting into the next frame's .color_commit_noarm() +call. + +Cc: #v5.19+ +Cc: Manasi Navare +Cc: Drew Davenport +Cc: Imre Deak +Cc: Jouni Högander +Fixes: d13dde449580 ("drm/i915: Split pipe+output CSC programming to noarm+arm pair") +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230320095438.17328-5-ville.syrjala@linux.intel.com +Reviewed-by: Imre Deak +(cherry picked from commit 92736f1b452bbb8a66bdb5b1d263ad00e04dd3b8) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_color.c | 43 ++++++++++++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_color.c ++++ b/drivers/gpu/drm/i915/display/intel_color.c +@@ -516,6 +516,14 @@ static void ilk_lut_12p4_pack(struct drm + + static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state) + { ++ /* ++ * Despite Wa_1406463849, ICL no longer suffers from the SKL ++ * DC5/PSR CSC black screen issue (see skl_color_commit_noarm()). ++ * Possibly due to the extra sticky CSC arming ++ * (see icl_color_post_update()). ++ * ++ * On TGL+ all CSC arming issues have been properly fixed. ++ */ + icl_load_csc_matrix(crtc_state); + } + +@@ -617,6 +625,28 @@ static void icl_color_commit_arm(const s + crtc_state->csc_mode); + } + ++static void icl_color_post_update(const struct intel_crtc_state *crtc_state) ++{ ++ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); ++ struct drm_i915_private *i915 = to_i915(crtc->base.dev); ++ ++ /* ++ * Despite Wa_1406463849, ICL CSC is no longer disarmed by ++ * coeff/offset register *writes*. Instead, once CSC_MODE ++ * is armed it stays armed, even after it has been latched. ++ * Afterwards the coeff/offset registers become effectively ++ * self-arming. That self-arming must be disabled before the ++ * next icl_color_commit_noarm() tries to write the next set ++ * of coeff/offset registers. Fortunately register *reads* ++ * do still disarm the CSC. Naturally this must not be done ++ * until the previously written CSC registers have actually ++ * been latched. ++ * ++ * TGL+ no longer need this workaround. ++ */ ++ intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(crtc->pipe)); ++} ++ + static struct drm_property_blob * + create_linear_lut(struct drm_i915_private *i915, int lut_size) + { +@@ -2345,10 +2375,19 @@ static const struct intel_color_funcs i9 + .read_luts = i9xx_read_luts, + }; + ++static const struct intel_color_funcs tgl_color_funcs = { ++ .color_check = icl_color_check, ++ .color_commit_noarm = icl_color_commit_noarm, ++ .color_commit_arm = icl_color_commit_arm, ++ .load_luts = icl_load_luts, ++ .read_luts = icl_read_luts, ++}; ++ + static const struct intel_color_funcs icl_color_funcs = { + .color_check = icl_color_check, + .color_commit_noarm = icl_color_commit_noarm, + .color_commit_arm = icl_color_commit_arm, ++ .color_post_update = icl_color_post_update, + .load_luts = icl_load_luts, + .read_luts = icl_read_luts, + }; +@@ -2440,7 +2479,9 @@ void intel_color_init_hooks(struct drm_i + else + i915->display.funcs.color = &i9xx_color_funcs; + } else { +- if (DISPLAY_VER(i915) >= 11) ++ if (DISPLAY_VER(i915) >= 12) ++ i915->display.funcs.color = &tgl_color_funcs; ++ else if (DISPLAY_VER(i915) == 11) + i915->display.funcs.color = &icl_color_funcs; + else if (DISPLAY_VER(i915) == 10) + i915->display.funcs.color = &glk_color_funcs; diff --git a/queue-6.2/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch b/queue-6.2/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch new file mode 100644 index 00000000000..802fd88c26e --- /dev/null +++ b/queue-6.2/revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch @@ -0,0 +1,91 @@ +From 534e465845ebfb4a97eb5459d3931a0b35e3b9a5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= +Date: Tue, 11 Apr 2023 13:49:32 +0000 +Subject: Revert "pinctrl: amd: Disable and mask interrupts on resume" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Kornel Dulęba + +commit 534e465845ebfb4a97eb5459d3931a0b35e3b9a5 upstream. + +This reverts commit b26cd9325be4c1fcd331b77f10acb627c560d4d7. + +This patch introduces a regression on Lenovo Z13, which can't wake +from the lid with it applied; and some unspecified AMD based Dell +platforms are unable to wake from hitting the power button + +Signed-off-by: Kornel Dulęba +Reviewed-by: Mario Limonciello +Link: https://lore.kernel.org/r/20230411134932.292287-1-korneld@chromium.org +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 36 ++++++++++++++++-------------------- + 1 file changed, 16 insertions(+), 20 deletions(-) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -865,34 +865,32 @@ static const struct pinconf_ops amd_pinc + .pin_config_group_set = amd_pinconf_group_set, + }; + +-static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) ++static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) + { +- const struct pin_desc *pd; ++ struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + unsigned long flags; + u32 pin_reg, mask; ++ int i; + + mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | + BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | + BIT(WAKE_CNTRL_OFF_S4); + +- pd = pin_desc_get(gpio_dev->pctrl, pin); +- if (!pd) +- return; ++ for (i = 0; i < desc->npins; i++) { ++ int pin = desc->pins[i].number; ++ const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); + +- raw_spin_lock_irqsave(&gpio_dev->lock, flags); +- pin_reg = readl(gpio_dev->base + pin * 4); +- pin_reg &= ~mask; +- writel(pin_reg, gpio_dev->base + pin * 4); +- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); +-} ++ if (!pd) ++ continue; + +-static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +-{ +- struct pinctrl_desc *desc = gpio_dev->pctrl->desc; +- int i; ++ raw_spin_lock_irqsave(&gpio_dev->lock, flags); + +- for (i = 0; i < desc->npins; i++) +- amd_gpio_irq_init_pin(gpio_dev, i); ++ pin_reg = readl(gpio_dev->base + i * 4); ++ pin_reg &= ~mask; ++ writel(pin_reg, gpio_dev->base + i * 4); ++ ++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); ++ } + } + + #ifdef CONFIG_PM_SLEEP +@@ -945,10 +943,8 @@ static int amd_gpio_resume(struct device + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + +- if (!amd_gpio_should_save(gpio_dev, pin)) { +- amd_gpio_irq_init_pin(gpio_dev, pin); ++ if (!amd_gpio_should_save(gpio_dev, pin)) + continue; +- } + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; diff --git a/queue-6.2/series b/queue-6.2/series new file mode 100644 index 00000000000..2acad5d5ebe --- /dev/null +++ b/queue-6.2/series @@ -0,0 +1,3 @@ +revert-pinctrl-amd-disable-and-mask-interrupts-on-resume.patch +drm-amd-display-pass-the-right-info-to-drm_dp_remove_payload.patch +drm-i915-workaround-icl-csc_mode-sticky-arming.patch