From: Russell King (Oracle) Date: Thu, 20 Mar 2025 22:11:17 +0000 (+0000) Subject: net: stmmac: socfpga: remove phy_resume() call X-Git-Tag: v6.15-rc1~160^2~22^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=366aeeba79088003307f0f12bb3575fb083cc72a;p=thirdparty%2Fkernel%2Flinux.git net: stmmac: socfpga: remove phy_resume() call As the previous commit addressed DWGMAC resuming with a PHY in suspended state, there is now no need for socfpga to work around this. Remove this code. Signed-off-by: Russell King (Oracle) Link: https://patch.msgid.link/E1tvO6f-008Vjn-J1@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 6b78ae7304669..1168556585597 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -523,24 +523,6 @@ static int socfpga_dwmac_resume(struct device *dev) dwmac_priv->ops->set_phy_mode(priv->plat->bsp_priv); - /* Before the enet controller is suspended, the phy is suspended. - * This causes the phy clock to be gated. The enet controller is - * resumed before the phy, so the clock is still gated "off" when - * the enet controller is resumed. This code makes sure the phy - * is "resumed" before reinitializing the enet controller since - * the enet controller depends on an active phy clock to complete - * a DMA reset. A DMA reset will "time out" if executed - * with no phy clock input on the Synopsys enet controller. - * Verified through Synopsys Case #8000711656. - * - * Note that the phy clock is also gated when the phy is isolated. - * Phy "suspend" and "isolate" controls are located in phy basic - * control register 0, and can be modified by the phy driver - * framework. - */ - if (ndev->phydev) - phy_resume(ndev->phydev); - return stmmac_resume(dev); } #endif /* CONFIG_PM_SLEEP */