From: Oliver Upton <oliver.upton@linux.dev>
Date: Wed, 19 Mar 2025 21:54:52 +0000 (-0700)
Subject: Merge branch 'kvm-arm64/pmu-fixes' into kvmarm/next
X-Git-Tag: v6.15-rc1~195^2~2^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=369c0122682c4468a69f2454614eded71c5348f3;p=thirdparty%2Fkernel%2Flinux.git

Merge branch 'kvm-arm64/pmu-fixes' into kvmarm/next

* kvm-arm64/pmu-fixes:
  : vPMU fixes for 6.15 courtesy of Akihiko Odaki
  :
  : Various fixes to KVM's vPMU implementation, notably ensuring
  : userspace-directed changes to the PMCs are reflected in the backing perf
  : events.
  KVM: arm64: PMU: Reload when resetting
  KVM: arm64: PMU: Reload when user modifies registers
  KVM: arm64: PMU: Fix SET_ONE_REG for vPMC regs
  KVM: arm64: PMU: Assume PMU presence in pmu-emul.c
  KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---

369c0122682c4468a69f2454614eded71c5348f3
diff --cc arch/arm64/kvm/emulate-nested.c
index 834c587500699,9293fb078fc62..0fcfcc0478f94
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@@ -2515,10 -2514,10 +2515,11 @@@ void kvm_emulate_nested_eret(struct kvm
  	*vcpu_cpsr(vcpu) = spsr;
  
  	kvm_arch_vcpu_load(vcpu, smp_processor_id());
 +	vcpu_clear_flag(vcpu, IN_NESTED_ERET);
  	preempt_enable();
  
- 	kvm_pmu_nested_transition(vcpu);
+ 	if (kvm_vcpu_has_pmu(vcpu))
+ 		kvm_pmu_nested_transition(vcpu);
  }
  
  static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
diff --cc arch/arm64/kvm/pmu-emul.c
index 51fb47e0bf893,aae5713d8993a..a1bc10d7116a5
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@@ -901,14 -832,20 +885,11 @@@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu 
  	u64 val, mask = 0;
  	int base, i, nr_events;
  
- 	if (!kvm_vcpu_has_pmu(vcpu))
- 		return 0;
- 
  	if (!pmceid1) {
 -		val = read_sysreg(pmceid0_el0);
 -		/* always support CHAIN */
 -		val |= BIT(ARMV8_PMUV3_PERFCTR_CHAIN);
 +		val = compute_pmceid0(cpu_pmu);
  		base = 0;
  	} else {
 -		val = read_sysreg(pmceid1_el0);
 -		/*
 -		 * Don't advertise STALL_SLOT*, as PMMIR_EL0 is handled
 -		 * as RAZ
 -		 */
 -		val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) |
 -			 BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) |
 -			 BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32));
 +		val = compute_pmceid1(cpu_pmu);
  		base = 32;
  	}