From: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Date: Wed, 10 Nov 2021 13:58:00 +0000 (-0700)
Subject: usb: dwc3: Update REFCLK_FLADJ for frame length adjustment
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=36ac9b6a6e9c05d6a8ad2474b16fa9c59044bbe4;p=thirdparty%2Fu-boot.git

usb: dwc3: Update REFCLK_FLADJ for frame length adjustment

Remove unwanted condition check for frame length adjustment.

For ZynqMP / Versal the ref clk is set to 20Mhz frequency and it is always
recommended. For 20Mhz frequency the refclk_fladj value should be 0, so
clear bits 21:8 in GFLADJ register.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
---

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 95baa067eff..565b502744b 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -66,13 +66,8 @@ static void dwc3_frame_length_adjustment(struct udevice *dev, struct dwc3 *dwc)
 
 	refclk_fladj = dev_read_bool(dev, "snps,refclk_fladj");
 
-	if (refclk_fladj) {
-		if ((reg & GFLADJ_REFCLK_FLADJ) != (fladj &
-					GFLADJ_REFCLK_FLADJ)) {
-			reg &= ~GFLADJ_REFCLK_FLADJ;
-			reg |= (fladj & GFLADJ_REFCLK_FLADJ);
-		}
-	}
+	if (refclk_fladj)
+		reg &= ~GFLADJ_REFCLK_FLADJ;
 
 	if ((reg & GFLADJ_30MHZ_MASK) != fladj) {
 		reg &= ~GFLADJ_30MHZ_MASK;