From: Arnd Bergmann <arnd@arndb.de>
Date: Wed, 14 Sep 2016 20:48:29 +0000 (+0200)
Subject: Merge branch 'dt/irq-fix' into next/dt64
X-Git-Tag: v4.9-rc1~75^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=37179033fc98156ce5cd360ff658da3e1fb01a56;p=thirdparty%2Flinux.git

Merge branch 'dt/irq-fix' into next/dt64

* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.
---

37179033fc98156ce5cd360ff658da3e1fb01a56
diff --cc arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8d7ce97c0ddbb,162831546e183..6328a66ed97e4
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@@ -474,14 -473,10 +474,14 @@@
  
  		timer {
  			compatible = "arm,armv8-timer";
 -			interrupts = <1 13 0xff08>,
 -				     <1 14 0xff08>,
 -				     <1 11 0xff08>,
 -				     <1 10 0xff08>;
 +			interrupts = <GIC_PPI 13
- 					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +				     <GIC_PPI 14
- 					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +				     <GIC_PPI 11
- 					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +				     <GIC_PPI 10
- 					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>;
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
  		};
  
  		pmu_system_controller: system-controller@105c0000 {
diff --cc arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index e70b9961115de,c2a6745f168cb..7b6136182ad08
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@@ -122,18 -122,12 +122,18 @@@
  
  			timer {
  				compatible = "arm,armv8-timer";
- 				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- 					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- 					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- 					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ 				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ 					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ 					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ 					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  			};
  
 +			pmu {
 +				compatible = "arm,cortex-a72-pmu";
 +				interrupt-parent = <&pic>;
 +				interrupts = <17>;
 +			};
 +
  			odmi: odmi@300000 {
  				compatible = "marvell,odmi-controller";
  				interrupt-controller;