From: Daniel Henrique Barboza Date: Wed, 18 Dec 2024 11:40:20 +0000 (-0300) Subject: target/riscv: add shcounterenw X-Git-Tag: v10.0.0-rc0~83^2~46 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3739732e755d84859fc2278ae3fff7d3869507b5;p=thirdparty%2Fqemu.git target/riscv: add shcounterenw shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d51201069..07bcf96e866 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 4f231735aba..460808d017b 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ