From: Greg Kroah-Hartman Date: Wed, 15 Aug 2012 19:03:42 +0000 (-0700) Subject: 3.0-stable patches X-Git-Tag: v3.0.41~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=373bbddc48557c7428eb21497c68cfe35891c6a6;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0-stable patches added patches: x86-simplify-code-by-removing-a-smp-ifdefs-from-struct-cpuinfo_x86.patch --- diff --git a/queue-3.0/series b/queue-3.0/series index 88864768473..1072188666d 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -1,3 +1,4 @@ +x86-simplify-code-by-removing-a-smp-ifdefs-from-struct-cpuinfo_x86.patch redefine-atomic_init-and-atomic64_init-to-drop-the-casts.patch sunrpc-return-negative-value-in-case-rpcbind-client-creation-error.patch nilfs2-fix-deadlock-issue-between-chcp-and-thaw-ioctls.patch diff --git a/queue-3.0/x86-simplify-code-by-removing-a-smp-ifdefs-from-struct-cpuinfo_x86.patch b/queue-3.0/x86-simplify-code-by-removing-a-smp-ifdefs-from-struct-cpuinfo_x86.patch new file mode 100644 index 00000000000..481b55b19cb --- /dev/null +++ b/queue-3.0/x86-simplify-code-by-removing-a-smp-ifdefs-from-struct-cpuinfo_x86.patch @@ -0,0 +1,253 @@ +From hmh@hmh.eng.br Wed Aug 15 11:22:19 2012 +From: Kevin Winchester +Date: Tue, 14 Aug 2012 21:26:54 -0300 +Subject: x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86' +To: Greg Kroah-Hartman + +From: Kevin Winchester + +commit 141168c36cdee3ff23d9c7700b0edc47cb65479f and +commit 3f806e50981825fa56a7f1938f24c0680816be45 upstream. + +Several fields in struct cpuinfo_x86 were not defined for the +!SMP case, likely to save space. However, those fields still +have some meaning for UP, and keeping them allows some #ifdef +removal from other files. The additional size of the UP kernel +from this change is not significant enough to worry about +keeping up the distinction: + + text data bss dec hex filename + 4737168 506459 972040 6215667 5ed7f3 vmlinux.o.before + 4737444 506459 972040 6215943 5ed907 vmlinux.o.after + +for a difference of 276 bytes for an example UP config. + +If someone wants those 276 bytes back badly then it should +be implemented in a cleaner way. + +Signed-off-by: Kevin Winchester +Cc: Steffen Persvold +Link: http://lkml.kernel.org/r/1324428742-12498-1-git-send-email-kjwinchester@gmail.com +Signed-off-by: Ingo Molnar +Signed-off-by: Borislav Petkov +Signed-off-by: Ben Hutchings +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/include/asm/processor.h | 2 -- + arch/x86/kernel/amd_nb.c | 8 ++------ + arch/x86/kernel/cpu/amd.c | 2 -- + arch/x86/kernel/cpu/common.c | 5 ----- + arch/x86/kernel/cpu/intel.c | 2 -- + arch/x86/kernel/cpu/mcheck/mce.c | 2 -- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 5 +---- + arch/x86/kernel/cpu/proc.c | 4 +--- + drivers/edac/i7core_edac.c | 2 -- + drivers/hwmon/coretemp.c | 7 +++---- + 10 files changed, 7 insertions(+), 32 deletions(-) + +--- a/arch/x86/include/asm/processor.h ++++ b/arch/x86/include/asm/processor.h +@@ -99,7 +99,6 @@ struct cpuinfo_x86 { + u16 apicid; + u16 initial_apicid; + u16 x86_clflush_size; +-#ifdef CONFIG_SMP + /* number of cores as seen by the OS: */ + u16 booted_cores; + /* Physical processor id: */ +@@ -110,7 +109,6 @@ struct cpuinfo_x86 { + u8 compute_unit_id; + /* Index into per_cpu list: */ + u16 cpu_index; +-#endif + } __attribute__((__aligned__(SMP_CACHE_BYTES))); + + #define X86_VENDOR_INTEL 0 +--- a/arch/x86/kernel/amd_nb.c ++++ b/arch/x86/kernel/amd_nb.c +@@ -154,16 +154,14 @@ int amd_get_subcaches(int cpu) + { + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; +- int cuid = 0; ++ int cuid; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + +-#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +-#endif + return (mask >> (4 * cuid)) & 0xf; + } + +@@ -172,7 +170,7 @@ int amd_set_subcaches(int cpu, int mask) + static unsigned int reset, ban; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + unsigned int reg; +- int cuid = 0; ++ int cuid; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; +@@ -190,9 +188,7 @@ int amd_set_subcaches(int cpu, int mask) + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + +-#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +-#endif + mask <<= 4 * cuid; + mask |= (0xf ^ (1 << cuid)) << 26; + +--- a/arch/x86/kernel/cpu/amd.c ++++ b/arch/x86/kernel/cpu/amd.c +@@ -146,7 +146,6 @@ static void __cpuinit init_amd_k6(struct + + static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) + { +-#ifdef CONFIG_SMP + /* calling is from identify_secondary_cpu() ? */ + if (!c->cpu_index) + return; +@@ -190,7 +189,6 @@ static void __cpuinit amd_k7_smp_check(s + + valid_k7: + ; +-#endif + } + + static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -675,9 +675,7 @@ static void __init early_identify_cpu(st + if (this_cpu->c_early_init) + this_cpu->c_early_init(c); + +-#ifdef CONFIG_SMP + c->cpu_index = 0; +-#endif + filter_cpuid_features(c, false); + + setup_smep(c); +@@ -760,10 +758,7 @@ static void __cpuinit generic_identify(s + c->apicid = c->initial_apicid; + # endif + #endif +- +-#ifdef CONFIG_X86_HT + c->phys_proc_id = c->initial_apicid; +-#endif + } + + setup_smep(c); +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -179,7 +179,6 @@ static void __cpuinit trap_init_f00f_bug + + static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) + { +-#ifdef CONFIG_SMP + /* calling is from identify_secondary_cpu() ? */ + if (!c->cpu_index) + return; +@@ -196,7 +195,6 @@ static void __cpuinit intel_smp_check(st + WARN_ONCE(1, "WARNING: SMP operation may be unreliable" + "with B stepping processors.\n"); + } +-#endif + } + + static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) +--- a/arch/x86/kernel/cpu/mcheck/mce.c ++++ b/arch/x86/kernel/cpu/mcheck/mce.c +@@ -122,9 +122,7 @@ void mce_setup(struct mce *m) + m->time = get_seconds(); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->cpuid = cpuid_eax(1); +-#ifdef CONFIG_SMP + m->socketid = cpu_data(m->extcpu).phys_proc_id; +-#endif + m->apicid = cpu_data(m->extcpu).initial_apicid; + rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); + } +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -65,11 +65,9 @@ struct threshold_bank { + }; + static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks); + +-#ifdef CONFIG_SMP + static unsigned char shared_bank[NR_BANKS] = { + 0, 0, 0, 0, 1 + }; +-#endif + + static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ + +@@ -227,10 +225,9 @@ void mce_amd_feature_init(struct cpuinfo + + if (!block) + per_cpu(bank_map, cpu) |= (1 << bank); +-#ifdef CONFIG_SMP ++ + if (shared_bank[bank] && c->cpu_core_id) + break; +-#endif + + memset(&b, 0, sizeof(b)); + b.cpu = cpu; +--- a/arch/x86/kernel/cpu/proc.c ++++ b/arch/x86/kernel/cpu/proc.c +@@ -64,12 +64,10 @@ static void show_cpuinfo_misc(struct seq + static int show_cpuinfo(struct seq_file *m, void *v) + { + struct cpuinfo_x86 *c = v; +- unsigned int cpu = 0; ++ unsigned int cpu; + int i; + +-#ifdef CONFIG_SMP + cpu = c->cpu_index; +-#endif + seq_printf(m, "processor\t: %u\n" + "vendor_id\t: %s\n" + "cpu family\t: %d\n" +--- a/drivers/edac/i7core_edac.c ++++ b/drivers/edac/i7core_edac.c +@@ -1842,11 +1842,9 @@ static int i7core_mce_check_error(void * + if (mce->bank != 8) + return 0; + +-#ifdef CONFIG_SMP + /* Only handle if it is the right mc controller */ + if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) + return 0; +-#endif + + smp_rmb(); + if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { +--- a/drivers/hwmon/coretemp.c ++++ b/drivers/hwmon/coretemp.c +@@ -47,16 +47,15 @@ + #define MAX_ATTRS 5 /* Maximum no of per-core attrs */ + #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) + +-#ifdef CONFIG_SMP + #define TO_PHYS_ID(cpu) cpu_data(cpu).phys_proc_id + #define TO_CORE_ID(cpu) cpu_data(cpu).cpu_core_id ++#define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) ++ ++#ifdef CONFIG_SMP + #define for_each_sibling(i, cpu) for_each_cpu(i, cpu_sibling_mask(cpu)) + #else +-#define TO_PHYS_ID(cpu) (cpu) +-#define TO_CORE_ID(cpu) (cpu) + #define for_each_sibling(i, cpu) for (i = 0; false; ) + #endif +-#define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) + + /* + * Per-Core Temperature Data