From: Dnyaneshwar Bhadane Date: Tue, 27 Aug 2024 14:13:56 +0000 (+0530) Subject: drm/i915/mtl: Update PLL c20 phy value for DP uhbr20 X-Git-Tag: v6.13-rc1~122^2~19^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=388629a219ace83a09f8431a2e709c6c2efcf6ee;p=thirdparty%2Fkernel%2Flinux.git drm/i915/mtl: Update PLL c20 phy value for DP uhbr20 Update mtl c20 phy DP table for uhbr20 values according to the revised specifications. Bspec: 74165 Signed-off-by: Dnyaneshwar Bhadane Reviewed-by: Sai Teja Pottumuttu Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20240827141356.3024760-1-dnyaneshwar.bhadane@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4a6c3040ca15e..f73d576fd99e9 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -923,10 +923,10 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = { }, .mplla = { 0x3104, /* mplla cfg0 */ 0xd105, /* mplla cfg1 */ - 0xc025, /* mplla cfg2 */ - 0xc025, /* mplla cfg3 */ - 0xa6ab, /* mplla cfg4 */ - 0x8c00, /* mplla cfg5 */ + 0x9217, /* mplla cfg2 */ + 0x9217, /* mplla cfg3 */ + 0x8c00, /* mplla cfg4 */ + 0x759a, /* mplla cfg5 */ 0x4000, /* mplla cfg6 */ 0x0003, /* mplla cfg7 */ 0x3555, /* mplla cfg8 */