From: Shane Xiao Date: Wed, 29 May 2024 09:57:31 +0000 (+0800) Subject: drm/amdgpu: Update the impelmentation of AMDGPU_PTE_MTYPE_NV10 X-Git-Tag: v6.11-rc1~141^2~25^2~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=392829010238319689ee7aab5f9acffc23a53899;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: Update the impelmentation of AMDGPU_PTE_MTYPE_NV10 This patch changes the implementation of AMDGPU_PTE_MTYPE_NV10, clear the bits before setting the new one. Suggested-by: Alex Deucher Signed-off-by: longlyao Signed-off-by: Shane Xiao Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index acd1b55b8b0e0..8019f0d14a8dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -108,8 +108,11 @@ struct amdgpu_mem_stats; | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) /* gfx10 */ -#define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) -#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) +#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) +#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) +#define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ + (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ + AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) /* gfx12 */ #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index d933e19e0cf55..f0ceab3ce5bfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -473,17 +473,17 @@ static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) { switch (flags) { case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); case AMDGPU_VM_MTYPE_WC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC); case AMDGPU_VM_MTYPE_CC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC); case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC); default: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); } } @@ -536,8 +536,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT | AMDGPU_GEM_CREATE_UNCACHED)) - *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | - AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); } static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) @@ -763,7 +762,7 @@ static int gmc_v10_0_gart_init(struct amdgpu_device *adev) return r; adev->gart.table_size = adev->gart.num_gpu_pages * 8; - adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | + adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | AMDGPU_PTE_EXECUTABLE; return amdgpu_gart_table_vram_alloc(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 527dc917e049d..cad8837838346 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -438,17 +438,17 @@ static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) { switch (flags) { case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); case AMDGPU_VM_MTYPE_WC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC); case AMDGPU_VM_MTYPE_CC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC); case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC); default: - return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); } } @@ -501,8 +501,7 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT | AMDGPU_GEM_CREATE_UNCACHED)) - *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | - AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); } static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) @@ -723,7 +722,7 @@ static int gmc_v11_0_gart_init(struct amdgpu_device *adev) return r; adev->gart.table_size = adev->gart.num_gpu_pages * 8; - adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | + adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | AMDGPU_PTE_EXECUTABLE; return amdgpu_gart_table_vram_alloc(adev);