From: Greg Kroah-Hartman Date: Wed, 11 Mar 2015 14:03:34 +0000 (+0100) Subject: 3.14-stable patches X-Git-Tag: v3.10.72~44 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3a0ba874a3812ee9757cd847ce64256cb341c241;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: drm-radeon-fix-voltage-setup-on-hawaii.patch drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch drm-radeon-workaround-for-cp-hw-bug-on-cik.patch --- diff --git a/queue-3.14/drm-radeon-fix-voltage-setup-on-hawaii.patch b/queue-3.14/drm-radeon-fix-voltage-setup-on-hawaii.patch new file mode 100644 index 00000000000..88188537a41 --- /dev/null +++ b/queue-3.14/drm-radeon-fix-voltage-setup-on-hawaii.patch @@ -0,0 +1,33 @@ +From 09b6e85fc868568e1b2820235a2a851aecbccfcc Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 12 Feb 2015 00:40:58 -0500 +Subject: drm/radeon: fix voltage setup on hawaii + +From: Alex Deucher + +commit 09b6e85fc868568e1b2820235a2a851aecbccfcc upstream. + +Missing parameter when fetching the real voltage values +from atom. Fixes problems with dynamic clocking on +certain boards. + +bug: +https://bugs.freedesktop.org/show_bug.cgi?id=87457 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_atombios.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -3272,6 +3272,7 @@ int radeon_atom_get_voltage_evv(struct r + + args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; + args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; ++ args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); + args.in.ulSCLKFreq = + cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); + diff --git a/queue-3.14/drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch b/queue-3.14/drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch new file mode 100644 index 00000000000..db0fc78db83 --- /dev/null +++ b/queue-3.14/drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch @@ -0,0 +1,117 @@ +From 410af8d7285a0b96314845c75c39fd612b755688 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 6 Feb 2015 12:53:27 -0500 +Subject: drm/radeon: only enable kv/kb dpm interrupts once v3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 410af8d7285a0b96314845c75c39fd612b755688 upstream. + +Enable at init and disable on fini. Workaround for hardware problems. + +v2 (chk): extend commit message +v3: add new function + +Signed-off-by: Alex Deucher +Signed-off-by: Christian König (v2) +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/cik.c | 21 --------------------- + drivers/gpu/drm/radeon/kv_dpm.c | 17 +++++++++++++++-- + 2 files changed, 15 insertions(+), 23 deletions(-) + +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -6809,7 +6809,6 @@ int cik_irq_set(struct radeon_device *rd + u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; + u32 grbm_int_cntl = 0; + u32 dma_cntl, dma_cntl1; +- u32 thermal_int; + + if (!rdev->irq.installed) { + WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); +@@ -6846,13 +6845,6 @@ int cik_irq_set(struct radeon_device *rd + cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; + cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; + +- if (rdev->flags & RADEON_IS_IGP) +- thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & +- ~(THERM_INTH_MASK | THERM_INTL_MASK); +- else +- thermal_int = RREG32_SMC(CG_THERMAL_INT) & +- ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); +- + /* enable CP interrupts on all rings */ + if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { + DRM_DEBUG("cik_irq_set: sw int gfx\n"); +@@ -7010,14 +7002,6 @@ int cik_irq_set(struct radeon_device *rd + hpd6 |= DC_HPDx_INT_EN; + } + +- if (rdev->irq.dpm_thermal) { +- DRM_DEBUG("dpm thermal\n"); +- if (rdev->flags & RADEON_IS_IGP) +- thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; +- else +- thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; +- } +- + WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + + WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); +@@ -7071,11 +7055,6 @@ int cik_irq_set(struct radeon_device *rd + WREG32(DC_HPD5_INT_CONTROL, hpd5); + WREG32(DC_HPD6_INT_CONTROL, hpd6); + +- if (rdev->flags & RADEON_IS_IGP) +- WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); +- else +- WREG32_SMC(CG_THERMAL_INT, thermal_int); +- + return 0; + } + +--- a/drivers/gpu/drm/radeon/kv_dpm.c ++++ b/drivers/gpu/drm/radeon/kv_dpm.c +@@ -1121,6 +1121,19 @@ void kv_dpm_enable_bapm(struct radeon_de + } + } + ++static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable) ++{ ++ u32 thermal_int; ++ ++ thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); ++ if (enable) ++ thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; ++ else ++ thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK); ++ WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); ++ ++} ++ + int kv_dpm_enable(struct radeon_device *rdev) + { + struct kv_power_info *pi = kv_get_pi(rdev); +@@ -1232,8 +1245,7 @@ int kv_dpm_late_enable(struct radeon_dev + DRM_ERROR("kv_set_thermal_temperature_range failed\n"); + return ret; + } +- rdev->irq.dpm_thermal = true; +- radeon_irq_set(rdev); ++ kv_enable_thermal_int(rdev, true); + } + + /* powerdown unused blocks for now */ +@@ -1261,6 +1273,7 @@ void kv_dpm_disable(struct radeon_device + kv_stop_dpm(rdev); + kv_enable_ulv(rdev, false); + kv_reset_am(rdev); ++ kv_enable_thermal_int(rdev, false); + + kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); + } diff --git a/queue-3.14/drm-radeon-workaround-for-cp-hw-bug-on-cik.patch b/queue-3.14/drm-radeon-workaround-for-cp-hw-bug-on-cik.patch new file mode 100644 index 00000000000..ad9301b2d67 --- /dev/null +++ b/queue-3.14/drm-radeon-workaround-for-cp-hw-bug-on-cik.patch @@ -0,0 +1,47 @@ +From a9c73a0e022c33954835e66fec3cd744af90ec98 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Tue, 10 Feb 2015 14:26:39 +0100 +Subject: drm/radeon: workaround for CP HW bug on CIK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Christian=20K=C3=B6nig?= + +commit a9c73a0e022c33954835e66fec3cd744af90ec98 upstream. + +Emit the EOP twice to avoid cache flushing problems. + +Signed-off-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/cik.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -3558,7 +3558,21 @@ void cik_fence_gfx_ring_emit(struct rade + struct radeon_ring *ring = &rdev->ring[fence->ring]; + u64 addr = rdev->fence_drv[fence->ring].gpu_addr; + +- /* EVENT_WRITE_EOP - flush caches, send int */ ++ /* Workaround for cache flush problems. First send a dummy EOP ++ * event down the pipe with seq one below. ++ */ ++ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); ++ radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | ++ EOP_TC_ACTION_EN | ++ EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | ++ EVENT_INDEX(5))); ++ radeon_ring_write(ring, addr & 0xfffffffc); ++ radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | ++ DATA_SEL(1) | INT_SEL(0)); ++ radeon_ring_write(ring, fence->seq - 1); ++ radeon_ring_write(ring, 0); ++ ++ /* Then send the real EOP event down the pipe. */ + radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); + radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | diff --git a/queue-3.14/series b/queue-3.14/series index 59194657639..d9d466d054b 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -22,3 +22,6 @@ mm-mmap.c-fix-arithmetic-overflow-in-__vm_enough_memory.patch mm-nommu.c-fix-arithmetic-overflow-in-__vm_enough_memory.patch mm-compaction-fix-wrong-order-check-in-compact_finished.patch mm-memory.c-actually-remap-enough-memory.patch +drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch +drm-radeon-workaround-for-cp-hw-bug-on-cik.patch +drm-radeon-fix-voltage-setup-on-hawaii.patch