From: Michael Tokarev <mjt@tls.msk.ru>
Date: Tue, 14 Nov 2023 16:11:33 +0000 (+0300)
Subject: target/riscv/cpu.h: spelling fix: separatly
X-Git-Tag: v8.2.0-rc1~14^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3a4e56015b897a5502ab6a691cd4e20700e779c1;p=thirdparty%2Fqemu.git

target/riscv/cpu.h: spelling fix: separatly

Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf58b0f0b56..d74b361be64 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -214,13 +214,13 @@ struct CPUArchState {
 
     /*
      * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
-     * alias of mie[i] and needs to be maintained separatly.
+     * alias of mie[i] and needs to be maintained separately.
      */
     uint64_t sie;
 
     /*
      * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
-     * alias of sie[i] (mie[i]) and needs to be maintained separatly.
+     * alias of sie[i] (mie[i]) and needs to be maintained separately.
      */
     uint64_t vsie;