From: Matthew Malcomson Date: Thu, 9 May 2019 09:29:16 +0000 (+0100) Subject: [binutils][aarch64] New iclass sve_size_hsd2. X-Git-Tag: binutils-2_33~1298 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3bd82c86f0f432bd7653101069bf056fda14b7cd;p=thirdparty%2Fbinutils-gdb.git [binutils][aarch64] New iclass sve_size_hsd2. Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. --- diff --git a/include/ChangeLog b/include/ChangeLog index 14415ed9079..cf24ee4e465 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2019-05-09 Matthew Malcomson + + * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. + 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e3924991f0b..a7a7459c5fb 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -590,6 +590,7 @@ enum aarch64_insn_class sve_size_bhs, sve_size_bhsd, sve_size_hsd, + sve_size_hsd2, sve_size_sd, testbranch, cryptosm3, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a1a842d225b..8e8b185ea39 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_hsd2 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_hsd2 iclass decode. + * aarch64-opc.c (fields): Handle SVE_size field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. + 2019-05-09 Matthew Malcomson * aarch64-asm-2.c: Regenerated. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 2424b66d966..d4f498f5ddc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1659,6 +1659,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); break; + case sve_size_hsd2: + insert_field (FLD_SVE_size, &inst->value, + aarch64_get_variant (inst) + 1, 0); + break; + default: break; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index eea649fd3cc..844c6ab68b2 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2810,6 +2810,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = extract_field (FLD_SVE_sz, inst->value, 0); break; + case sve_size_hsd2: + i = extract_field (FLD_SVE_size, inst->value, 0); + if (i < 1) + return FALSE; + variant = i - 1; + break; + default: /* No mapping between instruction class and qualifiers. */ return TRUE; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index eb3a1e400d1..97cbfc8c2aa 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -311,6 +311,7 @@ const aarch64_field fields[] = { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */ { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */ { 22, 1 }, /* SVE_sz: 1-bit element size select. */ + { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */ { 16, 4 }, /* SVE_tsz: triangular size select. */ { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */ { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index b1060d45933..942fa580f3d 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -138,6 +138,7 @@ enum aarch64_field_kind FLD_SVE_rot2, FLD_SVE_rot3, FLD_SVE_sz, + FLD_SVE_size, FLD_SVE_tsz, FLD_SVE_tszh, FLD_SVE_tszl_8,