From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sat, 24 Jan 2004 15:19:09 +0000 (+0000)
Subject: added TARGET_LONG_BITS
X-Git-Tag: release_0_6_0~426
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3cf1e035ba16423d1278ac34bea2ec795a9716a3;p=thirdparty%2Fqemu.git

added TARGET_LONG_BITS


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@580 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7f755a75416..174f60db669 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -20,6 +20,8 @@
 #ifndef CPU_ARM_H
 #define CPU_ARM_H
 
+#define TARGET_LONG_BITS 32
+
 #include "cpu-defs.h"
 
 #define EXCP_UDEF       1   /* undefined instruction */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 6be987c51dc..a93486cbe4a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -20,6 +20,8 @@
 #ifndef CPU_I386_H
 #define CPU_I386_H
 
+#define TARGET_LONG_BITS 32
+
 #include "cpu-defs.h"
 
 #define R_EAX 0
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 850a88ba8e7..3809f201411 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -23,6 +23,8 @@
 #include <endian.h>
 #include <asm/byteorder.h>
 
+#define TARGET_LONG_BITS 32
+
 #include "cpu-defs.h"
 
 //#define USE_OPEN_FIRMWARE
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 67fece71273..af5ecb5082e 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -1,8 +1,8 @@
 #ifndef CPU_SPARC_H
 #define CPU_SPARC_H
 
-#include <setjmp.h>
-#include "config.h"
+#define TARGET_LONG_BITS 32
+
 #include "cpu-defs.h"
 
 /*#define EXCP_INTERRUPT 0x100*/