From: Greg Kroah-Hartman Date: Thu, 13 Feb 2020 04:09:00 +0000 (-0800) Subject: 4.4-stable patches X-Git-Tag: v4.4.214~29 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3d71e5c30aa80a398b2ba42bcb7506a2ca7c4ff5;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: arc-add-missing-multicast-filter-number-to-gmac-node.patch arm-dts-at91-sama5d3-define-clock-rate-range-for-tcb1.patch arm-dts-at91-sama5d3-fix-maximum-peripheral-clock-rates.patch powerpc-pseries-allow-not-having-ibm-hypertas-functions-hcall-multi-tce-for-ddw.patch rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch --- diff --git a/queue-4.4/arc-add-missing-multicast-filter-number-to-gmac-node.patch b/queue-4.4/arc-add-missing-multicast-filter-number-to-gmac-node.patch new file mode 100644 index 00000000000..6e2a176fcd3 --- /dev/null +++ b/queue-4.4/arc-add-missing-multicast-filter-number-to-gmac-node.patch @@ -0,0 +1,32 @@ +From 7980dff398f86a618f502378fa27cf7e77449afa Mon Sep 17 00:00:00 2001 +From: Jose Abreu +Date: Tue, 14 Jan 2020 17:09:24 +0100 +Subject: ARC: [plat-axs10x]: Add missing multicast filter number to GMAC node + +From: Jose Abreu + +commit 7980dff398f86a618f502378fa27cf7e77449afa upstream. + +Add a missing property to GMAC node so that multicast filtering works +correctly. + +Fixes: 556cc1c5f528 ("ARC: [axs101] Add support for AXS101 SDP (software development platform)") +Acked-by: Alexey Brodkin +Signed-off-by: Jose Abreu +Signed-off-by: Vineet Gupta +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arc/boot/dts/axs10x_mb.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arc/boot/dts/axs10x_mb.dtsi ++++ b/arch/arc/boot/dts/axs10x_mb.dtsi +@@ -44,6 +44,7 @@ + interrupt-names = "macirq"; + phy-mode = "rgmii"; + snps,pbl = < 32 >; ++ snps,multicast-filter-bins = <256>; + clocks = <&apbclk>; + clock-names = "stmmaceth"; + max-speed = <100>; diff --git a/queue-4.4/arm-dts-at91-sama5d3-define-clock-rate-range-for-tcb1.patch b/queue-4.4/arm-dts-at91-sama5d3-define-clock-rate-range-for-tcb1.patch new file mode 100644 index 00000000000..8951c677ca1 --- /dev/null +++ b/queue-4.4/arm-dts-at91-sama5d3-define-clock-rate-range-for-tcb1.patch @@ -0,0 +1,35 @@ +From a7e0f3fc01df4b1b7077df777c37feae8c9e8b6d Mon Sep 17 00:00:00 2001 +From: Alexandre Belloni +Date: Fri, 10 Jan 2020 18:20:07 +0100 +Subject: ARM: dts: at91: sama5d3: define clock rate range for tcb1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alexandre Belloni + +commit a7e0f3fc01df4b1b7077df777c37feae8c9e8b6d upstream. + +The clock rate range for the TCB1 clock is missing. define it in the device +tree. + +Reported-by: Karl Rudbæk Olsen +Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks") +Link: https://lore.kernel.org/r/20200110172007.1253659-2-alexandre.belloni@bootlin.com +Signed-off-by: Alexandre Belloni +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/sama5d3_tcb1.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi ++++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi +@@ -23,6 +23,7 @@ + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <27>; ++ atmel,clk-output-range = <0 166000000>; + }; + }; + }; diff --git a/queue-4.4/arm-dts-at91-sama5d3-fix-maximum-peripheral-clock-rates.patch b/queue-4.4/arm-dts-at91-sama5d3-fix-maximum-peripheral-clock-rates.patch new file mode 100644 index 00000000000..ce40af9e898 --- /dev/null +++ b/queue-4.4/arm-dts-at91-sama5d3-fix-maximum-peripheral-clock-rates.patch @@ -0,0 +1,173 @@ +From ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da Mon Sep 17 00:00:00 2001 +From: Alexandre Belloni +Date: Fri, 10 Jan 2020 18:20:06 +0100 +Subject: ARM: dts: at91: sama5d3: fix maximum peripheral clock rates +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alexandre Belloni + +commit ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da upstream. + +Currently the maximum rate for peripheral clock is calculated based on a +typical 133MHz MCK. The maximum frequency is defined in the datasheet as a +ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the +device trees to match the maximum rate based on 166MHz. + +Reported-by: Karl Rudbæk Olsen +Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks") +Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com +Signed-off-by: Alexandre Belloni +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/sama5d3.dtsi | 28 ++++++++++++++-------------- + arch/arm/boot/dts/sama5d3_can.dtsi | 4 ++-- + arch/arm/boot/dts/sama5d3_uart.dtsi | 4 ++-- + 3 files changed, 18 insertions(+), 18 deletions(-) + +--- a/arch/arm/boot/dts/sama5d3.dtsi ++++ b/arch/arm/boot/dts/sama5d3.dtsi +@@ -1106,49 +1106,49 @@ + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <12>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <13>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <14>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <15>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + twi0_clk: twi0_clk { + reg = <18>; + #clock-cells = <0>; +- atmel,clk-output-range = <0 16625000>; ++ atmel,clk-output-range = <0 41500000>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <19>; +- atmel,clk-output-range = <0 16625000>; ++ atmel,clk-output-range = <0 41500000>; + }; + + twi2_clk: twi2_clk { + #clock-cells = <0>; + reg = <20>; +- atmel,clk-output-range = <0 16625000>; ++ atmel,clk-output-range = <0 41500000>; + }; + + mci0_clk: mci0_clk { +@@ -1164,19 +1164,19 @@ + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <24>; +- atmel,clk-output-range = <0 133000000>; ++ atmel,clk-output-range = <0 166000000>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <25>; +- atmel,clk-output-range = <0 133000000>; ++ atmel,clk-output-range = <0 166000000>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <26>; +- atmel,clk-output-range = <0 133000000>; ++ atmel,clk-output-range = <0 166000000>; + }; + + pwm_clk: pwm_clk { +@@ -1187,7 +1187,7 @@ + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <29>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + dma0_clk: dma0_clk { +@@ -1218,13 +1218,13 @@ + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <38>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <39>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + sha_clk: sha_clk { +--- a/arch/arm/boot/dts/sama5d3_can.dtsi ++++ b/arch/arm/boot/dts/sama5d3_can.dtsi +@@ -37,13 +37,13 @@ + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <40>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <41>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + }; + }; +--- a/arch/arm/boot/dts/sama5d3_uart.dtsi ++++ b/arch/arm/boot/dts/sama5d3_uart.dtsi +@@ -42,13 +42,13 @@ + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <17>; +- atmel,clk-output-range = <0 66000000>; ++ atmel,clk-output-range = <0 83000000>; + }; + }; + }; diff --git a/queue-4.4/powerpc-pseries-allow-not-having-ibm-hypertas-functions-hcall-multi-tce-for-ddw.patch b/queue-4.4/powerpc-pseries-allow-not-having-ibm-hypertas-functions-hcall-multi-tce-for-ddw.patch new file mode 100644 index 00000000000..08876170e92 --- /dev/null +++ b/queue-4.4/powerpc-pseries-allow-not-having-ibm-hypertas-functions-hcall-multi-tce-for-ddw.patch @@ -0,0 +1,155 @@ +From 7559d3d295f3365ea7ac0c0274c05e633fe4f594 Mon Sep 17 00:00:00 2001 +From: Alexey Kardashevskiy +Date: Mon, 16 Dec 2019 15:19:22 +1100 +Subject: powerpc/pseries: Allow not having ibm, hypertas-functions::hcall-multi-tce for DDW + +From: Alexey Kardashevskiy + +commit 7559d3d295f3365ea7ac0c0274c05e633fe4f594 upstream. + +By default a pseries guest supports a H_PUT_TCE hypercall which maps +a single IOMMU page in a DMA window. Additionally the hypervisor may +support H_PUT_TCE_INDIRECT/H_STUFF_TCE which update multiple TCEs at once; +this is advertised via the device tree /rtas/ibm,hypertas-functions +property which Linux converts to FW_FEATURE_MULTITCE. + +FW_FEATURE_MULTITCE is checked when dma_iommu_ops is used; however +the code managing the huge DMA window (DDW) ignores it and calls +H_PUT_TCE_INDIRECT even if it is explicitly disabled via +the "multitce=off" kernel command line parameter. + +This adds FW_FEATURE_MULTITCE checking to the DDW code path. + +This changes tce_build_pSeriesLP to take liobn and page size as +the huge window does not have iommu_table descriptor which usually +the place to store these numbers. + +Fixes: 4e8b0cf46b25 ("powerpc/pseries: Add support for dynamic dma windows") +Signed-off-by: Alexey Kardashevskiy +Reviewed-by: Thiago Jung Bauermann +Tested-by: Thiago Jung Bauermann +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20191216041924.42318-3-aik@ozlabs.ru +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/platforms/pseries/iommu.c | 43 ++++++++++++++++++++++----------- + 1 file changed, 29 insertions(+), 14 deletions(-) + +--- a/arch/powerpc/platforms/pseries/iommu.c ++++ b/arch/powerpc/platforms/pseries/iommu.c +@@ -202,10 +202,10 @@ static unsigned long tce_get_pseries(str + return be64_to_cpu(*tcep); + } + +-static void tce_free_pSeriesLP(struct iommu_table*, long, long); ++static void tce_free_pSeriesLP(unsigned long liobn, long, long); + static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); + +-static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, ++static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift, + long npages, unsigned long uaddr, + enum dma_data_direction direction, + struct dma_attrs *attrs) +@@ -216,25 +216,25 @@ static int tce_build_pSeriesLP(struct io + int ret = 0; + long tcenum_start = tcenum, npages_start = npages; + +- rpn = __pa(uaddr) >> TCE_SHIFT; ++ rpn = __pa(uaddr) >> tceshift; + proto_tce = TCE_PCI_READ; + if (direction != DMA_TO_DEVICE) + proto_tce |= TCE_PCI_WRITE; + + while (npages--) { +- tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; +- rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); ++ tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift; ++ rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce); + + if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { + ret = (int)rc; +- tce_free_pSeriesLP(tbl, tcenum_start, ++ tce_free_pSeriesLP(liobn, tcenum_start, + (npages_start - (npages + 1))); + break; + } + + if (rc && printk_ratelimit()) { + printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); +- printk("\tindex = 0x%llx\n", (u64)tbl->it_index); ++ printk("\tindex = 0x%llx\n", (u64)liobn); + printk("\ttcenum = 0x%llx\n", (u64)tcenum); + printk("\ttce val = 0x%llx\n", tce ); + dump_stack(); +@@ -263,7 +263,8 @@ static int tce_buildmulti_pSeriesLP(stru + unsigned long flags; + + if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) { +- return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, ++ return tce_build_pSeriesLP(tbl->it_index, tcenum, ++ tbl->it_page_shift, npages, uaddr, + direction, attrs); + } + +@@ -279,8 +280,9 @@ static int tce_buildmulti_pSeriesLP(stru + /* If allocation fails, fall back to the loop implementation */ + if (!tcep) { + local_irq_restore(flags); +- return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, +- direction, attrs); ++ return tce_build_pSeriesLP(tbl->it_index, tcenum, ++ tbl->it_page_shift, ++ npages, uaddr, direction, attrs); + } + __this_cpu_write(tce_page, tcep); + } +@@ -331,16 +333,16 @@ static int tce_buildmulti_pSeriesLP(stru + return ret; + } + +-static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) ++static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages) + { + u64 rc; + + while (npages--) { +- rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); ++ rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0); + + if (rc && printk_ratelimit()) { + printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); +- printk("\tindex = 0x%llx\n", (u64)tbl->it_index); ++ printk("\tindex = 0x%llx\n", (u64)liobn); + printk("\ttcenum = 0x%llx\n", (u64)tcenum); + dump_stack(); + } +@@ -355,7 +357,7 @@ static void tce_freemulti_pSeriesLP(stru + u64 rc; + + if (!firmware_has_feature(FW_FEATURE_MULTITCE)) +- return tce_free_pSeriesLP(tbl, tcenum, npages); ++ return tce_free_pSeriesLP(tbl->it_index, tcenum, npages); + + rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); + +@@ -470,6 +472,19 @@ static int tce_setrange_multi_pSeriesLP( + u64 rc = 0; + long l, limit; + ++ if (!firmware_has_feature(FW_FEATURE_MULTITCE)) { ++ unsigned long tceshift = be32_to_cpu(maprange->tce_shift); ++ unsigned long dmastart = (start_pfn << PAGE_SHIFT) + ++ be64_to_cpu(maprange->dma_base); ++ unsigned long tcenum = dmastart >> tceshift; ++ unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift; ++ void *uaddr = __va(start_pfn << PAGE_SHIFT); ++ ++ return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn), ++ tcenum, tceshift, npages, (unsigned long) uaddr, ++ DMA_BIDIRECTIONAL, 0); ++ } ++ + local_irq_disable(); /* to protect tcep and the page behind it */ + tcep = __this_cpu_read(tce_page); + diff --git a/queue-4.4/rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch b/queue-4.4/rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch new file mode 100644 index 00000000000..7ee07a5a9b8 --- /dev/null +++ b/queue-4.4/rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch @@ -0,0 +1,35 @@ +From f236a2a2ebabad0848ad0995af7ad1dc7029e895 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Thu, 12 Dec 2019 16:31:10 +0100 +Subject: rtc: hym8563: Return -EINVAL if the time is known to be invalid + +From: Paul Kocialkowski + +commit f236a2a2ebabad0848ad0995af7ad1dc7029e895 upstream. + +The current code returns -EPERM when the voltage loss bit is set. +Since the bit indicates that the time value is not valid, return +-EINVAL instead, which is the appropriate error code for this +situation. + +Fixes: dcaf03849352 ("rtc: add hym8563 rtc-driver") +Signed-off-by: Paul Kocialkowski +Link: https://lore.kernel.org/r/20191212153111.966923-1-paul.kocialkowski@bootlin.com +Signed-off-by: Alexandre Belloni +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/rtc/rtc-hym8563.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/rtc/rtc-hym8563.c ++++ b/drivers/rtc/rtc-hym8563.c +@@ -105,7 +105,7 @@ static int hym8563_rtc_read_time(struct + + if (!hym8563->valid) { + dev_warn(&client->dev, "no valid clock/calendar values available\n"); +- return -EPERM; ++ return -EINVAL; + } + + ret = i2c_smbus_read_i2c_block_data(client, HYM8563_SEC, 7, buf); diff --git a/queue-4.4/series b/queue-4.4/series index a1efa7e3315..91e89930ac1 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -78,3 +78,8 @@ clocksource-prevent-double-add_timer_on-for-watchdog_timer.patch perf-core-fix-mlock-accounting-in-perf_mmap.patch asoc-pcm-update-fe-be-trigger-order-based-on-the-com.patch scsi-ufs-fix-ufshcd_probe_hba-reture-value-in-case-ufshcd_scsi_add_wlus-fails.patch +rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch +arc-add-missing-multicast-filter-number-to-gmac-node.patch +arm-dts-at91-sama5d3-fix-maximum-peripheral-clock-rates.patch +arm-dts-at91-sama5d3-define-clock-rate-range-for-tcb1.patch +powerpc-pseries-allow-not-having-ibm-hypertas-functions-hcall-multi-tce-for-ddw.patch