From: Julian Seward Date: Thu, 10 Nov 2005 19:33:56 +0000 (+0000) Subject: Add instruction-set tests for ppc32 (integer, FP, altivec). X-Git-Tag: svn/VALGRIND_3_1_0~157 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3dbed544553a81ee2d1702b4bd3561618e1d1cb0;p=thirdparty%2Fvalgrind.git Add instruction-set tests for ppc32 (integer, FP, altivec). git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5075 --- diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am index 561c2940d2..9b9758081a 100644 --- a/none/tests/ppc32/Makefile.am +++ b/none/tests/ppc32/Makefile.am @@ -2,10 +2,14 @@ noinst_SCRIPTS = filter_stderr EXTRA_DIST = $(noinst_SCRIPTS) \ - lsw.stderr.exp lsw.stdout.exp lsw.vgtest + lsw.stderr.exp lsw.stdout.exp lsw.vgtest \ + jm-insns.stderr.exp jm-insns.stdout.exp jm-insns.vgtest + jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.vgtest check_PROGRAMS = \ - lsw + lsw jm-insns AM_CFLAGS = $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/include AM_CXXFLAGS = $(AM_CFLAGS) + +jm_insns_CFLAGS = -Winline -Wall -O -mregnames -DHAS_ALTIVEC -maltivec diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c new file mode 100644 index 0000000000..80bc54d11e --- /dev/null +++ b/none/tests/ppc32/jm-insns.c @@ -0,0 +1,6433 @@ + +/* HOW TO COMPILE: + +gcc -Winline -Wall -O -mregnames -DHAS_ALTIVEC -maltivec + +This program is useful, but the register usage conventions in +it are a complete dog. In particular, _patch_op_imm has to +be inlined, else you wind up with it segfaulting in +completely different places due to corruption (of r20 in the +case I chased). +*/ + +/* + * test-ppc.c: + * PPC tests for qemu-PPC CPU emulation checks + * + * Copyright (c) 2005 Jocelyn Mayer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License V2 + * as published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Theory of operations: + * a few registers are reserved for the test program: + * r14 => r18 + * f14 => f18 + * I do preload test values in r14 thru r17 (or less, depending on the number + * of register operands needed), patch the test opcode if any immediate + * operands are required, execute the tested opcode. + * XER, CCR and FPSCR are cleared before every test. + * I always get the result in r17 and also save XER and CCR for fixed-point + * operations. I also check FPSCR for floating points operations. + * + * Improvments: + * a more clever FPSCR management is needed: for now, I always test + * the round-to-zero case. Other rounding modes also need to be tested. + */ + +/* + * Operation details: + * + * The 'test' functions (via all_tests[]) are wrappers of single asm instns + * + * The 'loops' (e.g. int_loops) do the actual work: + * - loops over as many arguments as the instn needs (regs | imms) + * - sets up the environment (reset cr,xer, assign src regs...) + * - maybe modifies the asm instn to test different imm args + * - calls the test function + * - retrieves relevant register data (rD,cr,xer,...) + * - prints argument and result data. + * + * More specifically... + * + * all_tests[i] holds insn tests + * - of which each holds: {instn_test_arr[], description, flags} + * + * flags hold 3 instn classifiers: {family, type, arg_type} + * + * // The main test loop: + * do_tests( user_ctl_flags ) { + * foreach(curr_test = all_test[i]) { + * + * // flags are used to control what tests are run: + * if (curr_test->flags && !user_ctl_flags) + * continue; + * + * // a 'loop_family_arr' is chosen based on the 'family' flag... + * switch(curr_test->flags->family) { + * case x: loop_family_arr = int_loops; + * ... + * } + * + * // ...and the actual test_loop to run is found by indexing into + * // the loop_family_arr with the 'arg_type' flag: + * test_loop = loop_family[curr_test->flags->arg_type] + * + * // finally, loop over all instn tests for this test: + * foreach (instn_test = curr_test->instn_test_arr[i]) { + * + * // and call the test_loop with the current instn_test function,name + * test_loop( instn_test->func, instn_test->name ) + * } + * } + * } +*/ + +#include + +register double f14 __asm__ ("f14"); +register double f15 __asm__ ("f15"); +register double f16 __asm__ ("f16"); +register double f17 __asm__ ("f17"); +register double f18 __asm__ ("f18"); +register uint32_t r14 __asm__ ("r14"); +register uint32_t r15 __asm__ ("r15"); +register uint32_t r16 __asm__ ("r16"); +register uint32_t r17 __asm__ ("r17"); +register uint32_t r18 __asm__ ("r18"); + +#if defined (HAS_ALTIVEC) +# include +#endif +#include +#include +#include +//#include +//#include +#include +#include +#include +#include +#include + +/* -------------- BEGIN #include "test-ppc.h" -------------- */ +/* + * test-ppc.h: + * PPC tests for qemu-PPC CPU emulation checks - definitions + * + * Copyright (c) 2005 Jocelyn Mayer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License V2 + * as published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#if !defined (__TEST_PPC_H__) +#define __TEST_PPC_H__ + +#include + +typedef void (*test_func_t) (void); +typedef struct test_t test_t; +typedef struct test_table_t test_table_t; +struct test_t { + test_func_t func; + const unsigned char *name; +}; + +struct test_table_t { + test_t *tests; + const unsigned char *name; + uint32_t flags; +}; + +typedef void (*test_loop_t) (const unsigned char *name, test_func_t func, + uint32_t flags); + +enum test_flags { + /* Nb arguments */ + PPC_ONE_ARG = 0x00000001, + PPC_TWO_ARGS = 0x00000002, + PPC_THREE_ARGS = 0x00000003, + PPC_CMP_ARGS = 0x00000004, // family: compare + PPC_CMPI_ARGS = 0x00000005, // family: compare + PPC_TWO_I16 = 0x00000006, // family: arith/logical + PPC_SPECIAL = 0x00000007, // family: logical + PPC_LD_ARGS = 0x00000008, // family: ldst + PPC_LDX_ARGS = 0x00000009, // family: ldst + PPC_ST_ARGS = 0x0000000A, // family: ldst + PPC_STX_ARGS = 0x0000000B, // family: ldst + PPC_NB_ARGS = 0x0000000F, + /* Type */ + PPC_ARITH = 0x00000100, + PPC_LOGICAL = 0x00000200, + PPC_COMPARE = 0x00000300, + PPC_CROP = 0x00000400, + PPC_LDST = 0x00000500, + PPC_TYPE = 0x00000F00, + /* Family */ + PPC_INTEGER = 0x00010000, + PPC_FLOAT = 0x00020000, + PPC_405 = 0x00030000, + PPC_ALTIVEC = 0x00040000, + PPC_FALTIVEC = 0x00050000, + PPC_FAMILY = 0x000F0000, + /* Flags: these may be combined, so use separate bitfields. */ + PPC_CR = 0x01000000, + PPC_XER_CA = 0x02000000, +}; + +#endif /* !defined (__TEST_PPC_H__) */ + +/* -------------- END #include "test-ppc.h" -------------- */ + + +#define USAGE_SIMPLE +//#define ALTIVEC_ARGS_LARGE + + +//#define DEBUG_ARGS_BUILD +#if defined (DEBUG_ARGS_BUILD) +#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0) +#else +#define AB_DPRINTF(fmt, args...) do { } while (0) +#endif + +//#define DEBUG_FILTER +#if defined (DEBUG_FILTER) +#define FDPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0) +#else +#define FDPRINTF(fmt, args...) do { } while (0) +#endif + + +#define unused __attribute__ (( unused )) + +/* -------------- BEGIN #include "ops-ppc.c" -------------- */ +/* + * WARNING: + * This file has been auto-generated by './gen-ppc' program + * Please don't edit by hand + */ + + +/* #include "test-ppc.h" */ + +static void test_add (void) +{ + __asm__ __volatile__ ("add 17, 14, 15"); +} + +static void test_addo (void) +{ + __asm__ __volatile__ ("addo 17, 14, 15"); +} + +static void test_addc (void) +{ + __asm__ __volatile__ ("addc 17, 14, 15"); +} + +static void test_addco (void) +{ + __asm__ __volatile__ ("addco 17, 14, 15"); +} + +static void test_divw (void) +{ + __asm__ __volatile__ ("divw 17, 14, 15"); +} + +static void test_divwo (void) +{ + __asm__ __volatile__ ("divwo 17, 14, 15"); +} + +static void test_divwu (void) +{ + __asm__ __volatile__ ("divwu 17, 14, 15"); +} + +static void test_divwuo (void) +{ + __asm__ __volatile__ ("divwuo 17, 14, 15"); +} + +static void test_mulhw (void) +{ + __asm__ __volatile__ ("mulhw 17, 14, 15"); +} + +static void test_mulhwu (void) +{ + __asm__ __volatile__ ("mulhwu 17, 14, 15"); +} + +static void test_mullw (void) +{ + __asm__ __volatile__ ("mullw 17, 14, 15"); +} + +static void test_mullwo (void) +{ + __asm__ __volatile__ ("mullwo 17, 14, 15"); +} + +static void test_subf (void) +{ + __asm__ __volatile__ ("subf 17, 14, 15"); +} + +static void test_subfo (void) +{ + __asm__ __volatile__ ("subfo 17, 14, 15"); +} + +static void test_subfc (void) +{ + __asm__ __volatile__ ("subfc 17, 14, 15"); +} + +static void test_subfco (void) +{ + __asm__ __volatile__ ("subfco 17, 14, 15"); +} + +static test_t tests_ia_ops_two[] = { + { &test_add , " add", }, + { &test_addo , " addo", }, + { &test_addc , " addc", }, + { &test_addco , " addco", }, + { &test_divw , " divw", }, + { &test_divwo , " divwo", }, + { &test_divwu , " divwu", }, + { &test_divwuo , " divwuo", }, + { &test_mulhw , " mulhw", }, + { &test_mulhwu , " mulhwu", }, + { &test_mullw , " mullw", }, + { &test_mullwo , " mullwo", }, + { &test_subf , " subf", }, + { &test_subfo , " subfo", }, + { &test_subfc , " subfc", }, + { &test_subfco , " subfco", }, + { NULL, NULL, }, +}; + +static void test_add_ (void) +{ + __asm__ __volatile__ ("add. 17, 14, 15"); +} + +static void test_addo_ (void) +{ + __asm__ __volatile__ ("addo. 17, 14, 15"); +} + +static void test_addc_ (void) +{ + __asm__ __volatile__ ("addc. 17, 14, 15"); +} + +static void test_addco_ (void) +{ + __asm__ __volatile__ ("addco. 17, 14, 15"); +} + +static void test_divw_ (void) +{ + __asm__ __volatile__ ("divw. 17, 14, 15"); +} + +static void test_divwo_ (void) +{ + __asm__ __volatile__ ("divwo. 17, 14, 15"); +} + +static void test_divwu_ (void) +{ + __asm__ __volatile__ ("divwu. 17, 14, 15"); +} + +static void test_divwuo_ (void) +{ + __asm__ __volatile__ ("divwuo. 17, 14, 15"); +} + +static void test_mulhw_ (void) +{ + __asm__ __volatile__ ("mulhw. 17, 14, 15"); +} + +static void test_mulhwu_ (void) +{ + __asm__ __volatile__ ("mulhwu. 17, 14, 15"); +} + +static void test_mullw_ (void) +{ + __asm__ __volatile__ ("mullw. 17, 14, 15"); +} + +static void test_mullwo_ (void) +{ + __asm__ __volatile__ ("mullwo. 17, 14, 15"); +} + +static void test_subf_ (void) +{ + __asm__ __volatile__ ("subf. 17, 14, 15"); +} + +static void test_subfo_ (void) +{ + __asm__ __volatile__ ("subfo. 17, 14, 15"); +} + +static void test_subfc_ (void) +{ + __asm__ __volatile__ ("subfc. 17, 14, 15"); +} + +static void test_subfco_ (void) +{ + __asm__ __volatile__ ("subfco. 17, 14, 15"); +} + +static test_t tests_iar_ops_two[] = { + { &test_add_ , " add.", }, + { &test_addo_ , " addo.", }, + { &test_addc_ , " addc.", }, + { &test_addco_ , " addco.", }, + { &test_divw_ , " divw.", }, + { &test_divwo_ , " divwo.", }, + { &test_divwu_ , " divwu.", }, + { &test_divwuo_ , " divwuo.", }, + { &test_mulhw_ , " mulhw.", }, + { &test_mulhwu_ , " mulhwu.", }, + { &test_mullw_ , " mullw.", }, + { &test_mullwo_ , " mullwo.", }, + { &test_subf_ , " subf.", }, + { &test_subfo_ , " subfo.", }, + { &test_subfc_ , " subfc.", }, + { &test_subfco_ , " subfco.", }, + { NULL, NULL, }, +}; + +static void test_adde (void) +{ + __asm__ __volatile__ ("adde 17, 14, 15"); +} + +static void test_addeo (void) +{ + __asm__ __volatile__ ("addeo 17, 14, 15"); +} + +static void test_subfe (void) +{ + __asm__ __volatile__ ("subfe 17, 14, 15"); +} + +static void test_subfeo (void) +{ + __asm__ __volatile__ ("subfeo 17, 14, 15"); +} + +static test_t tests_iac_ops_two[] = { + { &test_adde , " adde", }, + { &test_addeo , " addeo", }, + { &test_subfe , " subfe", }, + { &test_subfeo , " subfeo", }, + { NULL, NULL, }, +}; + +static void test_adde_ (void) +{ + __asm__ __volatile__ ("adde. 17, 14, 15"); +} + +static void test_addeo_ (void) +{ + __asm__ __volatile__ ("addeo. 17, 14, 15"); +} + +static void test_subfe_ (void) +{ + __asm__ __volatile__ ("subfe. 17, 14, 15"); +} + +static void test_subfeo_ (void) +{ + __asm__ __volatile__ ("subfeo. 17, 14, 15"); +} + +static test_t tests_iacr_ops_two[] = { + { &test_adde_ , " adde.", }, + { &test_addeo_ , " addeo.", }, + { &test_subfe_ , " subfe.", }, + { &test_subfeo_ , " subfeo.", }, + { NULL, NULL, }, +}; + +static void test_and (void) +{ + __asm__ __volatile__ ("and 17, 14, 15"); +} + +static void test_andc (void) +{ + __asm__ __volatile__ ("andc 17, 14, 15"); +} + +static void test_eqv (void) +{ + __asm__ __volatile__ ("eqv 17, 14, 15"); +} + +static void test_nand (void) +{ + __asm__ __volatile__ ("nand 17, 14, 15"); +} + +static void test_nor (void) +{ + __asm__ __volatile__ ("nor 17, 14, 15"); +} + +static void test_or (void) +{ + __asm__ __volatile__ ("or 17, 14, 15"); +} + +static void test_orc (void) +{ + __asm__ __volatile__ ("orc 17, 14, 15"); +} + +static void test_xor (void) +{ + __asm__ __volatile__ ("xor 17, 14, 15"); +} + +static void test_slw (void) +{ + __asm__ __volatile__ ("slw 17, 14, 15"); +} + +static void test_sraw (void) +{ + __asm__ __volatile__ ("sraw 17, 14, 15"); +} + +static void test_srw (void) +{ + __asm__ __volatile__ ("srw 17, 14, 15"); +} + +static test_t tests_il_ops_two[] = { + { &test_and , " and", }, + { &test_andc , " andc", }, + { &test_eqv , " eqv", }, + { &test_nand , " nand", }, + { &test_nor , " nor", }, + { &test_or , " or", }, + { &test_orc , " orc", }, + { &test_xor , " xor", }, + { &test_slw , " slw", }, + { &test_sraw , " sraw", }, + { &test_srw , " srw", }, + { NULL, NULL, }, +}; + +static void test_and_ (void) +{ + __asm__ __volatile__ ("and. 17, 14, 15"); +} + +static void test_andc_ (void) +{ + __asm__ __volatile__ ("andc. 17, 14, 15"); +} + +static void test_eqv_ (void) +{ + __asm__ __volatile__ ("eqv. 17, 14, 15"); +} + +static void test_nand_ (void) +{ + __asm__ __volatile__ ("nand. 17, 14, 15"); +} + +static void test_nor_ (void) +{ + __asm__ __volatile__ ("nor. 17, 14, 15"); +} + +static void test_or_ (void) +{ + __asm__ __volatile__ ("or. 17, 14, 15"); +} + +static void test_orc_ (void) +{ + __asm__ __volatile__ ("orc. 17, 14, 15"); +} + +static void test_xor_ (void) +{ + __asm__ __volatile__ ("xor. 17, 14, 15"); +} + +static void test_slw_ (void) +{ + __asm__ __volatile__ ("slw. 17, 14, 15"); +} + +static void test_sraw_ (void) +{ + __asm__ __volatile__ ("sraw. 17, 14, 15"); +} + +static void test_srw_ (void) +{ + __asm__ __volatile__ ("srw. 17, 14, 15"); +} + +static test_t tests_ilr_ops_two[] = { + { &test_and_ , " and.", }, + { &test_andc_ , " andc.", }, + { &test_eqv_ , " eqv.", }, + { &test_nand_ , " nand.", }, + { &test_nor_ , " nor.", }, + { &test_or_ , " or.", }, + { &test_orc_ , " orc.", }, + { &test_xor_ , " xor.", }, + { &test_slw_ , " slw.", }, + { &test_sraw_ , " sraw.", }, + { &test_srw_ , " srw.", }, + { NULL, NULL, }, +}; + +static void test_cmp (void) +{ + __asm__ __volatile__ ("cmp 2, 14, 15"); +} + +static void test_cmpl (void) +{ + __asm__ __volatile__ ("cmpl 2, 14, 15"); +} + +static test_t tests_icr_ops_two[] = { + { &test_cmp , " cmp", }, + { &test_cmpl , " cmpl", }, + { NULL, NULL, }, +}; + +static void test_cmpi (void) +{ + __asm__ __volatile__ ("cmpi 2, 14, 15"); +} + +static void test_cmpli (void) +{ + __asm__ __volatile__ ("cmpli 2, 14, 15"); +} + +static test_t tests_icr_ops_two_i16[] = { + { &test_cmpi , " cmpi", }, + { &test_cmpli , " cmpli", }, + { NULL, NULL, }, +}; + +static void test_addi (void) +{ + __asm__ __volatile__ ("addi 17, 14, 0"); +} + +static void test_addic (void) +{ + __asm__ __volatile__ ("addic 17, 14, 0"); +} + +static void test_addis (void) +{ + __asm__ __volatile__ ("addis 17, 14, 0"); +} + +static void test_mulli (void) +{ + __asm__ __volatile__ ("mulli 17, 14, 0"); +} + +static void test_subfic (void) +{ + __asm__ __volatile__ ("subfic 17, 14, 0"); +} + +static test_t tests_ia_ops_two_i16[] = { + { &test_addi , " addi", }, + { &test_addic , " addic", }, + { &test_addis , " addis", }, + { &test_mulli , " mulli", }, + { &test_subfic , " subfic", }, + { NULL, NULL, }, +}; + +static void test_addic_ (void) +{ + __asm__ __volatile__ ("addic. 17, 14, 0"); +} + +static test_t tests_iar_ops_two_i16[] = { + { &test_addic_ , " addic.", }, + { NULL, NULL, }, +}; + +static void test_ori (void) +{ + __asm__ __volatile__ ("ori 17, 14, 0"); +} + +static void test_oris (void) +{ + __asm__ __volatile__ ("oris 17, 14, 0"); +} + +static void test_xori (void) +{ + __asm__ __volatile__ ("xori 17, 14, 0"); +} + +static void test_xoris (void) +{ + __asm__ __volatile__ ("xoris 17, 14, 0"); +} + +static test_t tests_il_ops_two_i16[] = { + { &test_ori , " ori", }, + { &test_oris , " oris", }, + { &test_xori , " xori", }, + { &test_xoris , " xoris", }, + { NULL, NULL, }, +}; + +static void test_andi_ (void) +{ + __asm__ __volatile__ ("andi. 17, 14, 0"); +} + +static void test_andis_ (void) +{ + __asm__ __volatile__ ("andis. 17, 14, 0"); +} + +static test_t tests_ilr_ops_two_i16[] = { + { &test_andi_ , " andi.", }, + { &test_andis_ , " andis.", }, + { NULL, NULL, }, +}; + +static void test_crand (void) +{ + __asm__ __volatile__ ("crand 17, 14, 15"); +} + +static void test_crandc (void) +{ + __asm__ __volatile__ ("crandc 17, 14, 15"); +} + +static void test_creqv (void) +{ + __asm__ __volatile__ ("creqv 17, 14, 15"); +} + +static void test_crnand (void) +{ + __asm__ __volatile__ ("crnand 17, 14, 15"); +} + +static void test_crnor (void) +{ + __asm__ __volatile__ ("crnor 17, 14, 15"); +} + +static void test_cror (void) +{ + __asm__ __volatile__ ("cror 17, 14, 15"); +} + +static void test_crorc (void) +{ + __asm__ __volatile__ ("crorc 17, 14, 15"); +} + +static void test_crxor (void) +{ + __asm__ __volatile__ ("crxor 17, 14, 15"); +} + +static test_t tests_crl_ops_two[] = { + { &test_crand , " crand", }, + { &test_crandc , " crandc", }, + { &test_creqv , " creqv", }, + { &test_crnand , " crnand", }, + { &test_crnor , " crnor", }, + { &test_cror , " cror", }, + { &test_crorc , " crorc", }, + { &test_crxor , " crxor", }, + { NULL, NULL, }, +}; + +static void test_addme (void) +{ + __asm__ __volatile__ ("addme 17, 14"); +} + +static void test_addmeo (void) +{ + __asm__ __volatile__ ("addmeo 17, 14"); +} + +static void test_addze (void) +{ + __asm__ __volatile__ ("addze 17, 14"); +} + +static void test_addzeo (void) +{ + __asm__ __volatile__ ("addzeo 17, 14"); +} + +static void test_subfme (void) +{ + __asm__ __volatile__ ("subfme 17, 14"); +} + +static void test_subfmeo (void) +{ + __asm__ __volatile__ ("subfmeo 17, 14"); +} + +static void test_subfze (void) +{ + __asm__ __volatile__ ("subfze 17, 14"); +} + +static void test_subfzeo (void) +{ + __asm__ __volatile__ ("subfzeo 17, 14"); +} + +static test_t tests_iac_ops_one[] = { + { &test_addme , " addme", }, + { &test_addmeo , " addmeo", }, + { &test_addze , " addze", }, + { &test_addzeo , " addzeo", }, + { &test_subfme , " subfme", }, + { &test_subfmeo , " subfmeo", }, + { &test_subfze , " subfze", }, + { &test_subfzeo , " subfzeo", }, + { NULL, NULL, }, +}; + +static void test_addme_ (void) +{ + __asm__ __volatile__ ("addme. 17, 14"); +} + +static void test_addmeo_ (void) +{ + __asm__ __volatile__ ("addmeo. 17, 14"); +} + +static void test_addze_ (void) +{ + __asm__ __volatile__ ("addze. 17, 14"); +} + +static void test_addzeo_ (void) +{ + __asm__ __volatile__ ("addzeo. 17, 14"); +} + +static void test_subfme_ (void) +{ + __asm__ __volatile__ ("subfme. 17, 14"); +} + +static void test_subfmeo_ (void) +{ + __asm__ __volatile__ ("subfmeo. 17, 14"); +} + +static void test_subfze_ (void) +{ + __asm__ __volatile__ ("subfze. 17, 14"); +} + +static void test_subfzeo_ (void) +{ + __asm__ __volatile__ ("subfzeo. 17, 14"); +} + +static test_t tests_iacr_ops_one[] = { + { &test_addme_ , " addme.", }, + { &test_addmeo_ , " addmeo.", }, + { &test_addze_ , " addze.", }, + { &test_addzeo_ , " addzeo.", }, + { &test_subfme_ , " subfme.", }, + { &test_subfmeo_ , " subfmeo.", }, + { &test_subfze_ , " subfze.", }, + { &test_subfzeo_ , " subfzeo.", }, + { NULL, NULL, }, +}; + +static void test_cntlzw (void) +{ + __asm__ __volatile__ ("cntlzw 17, 14"); +} + +static void test_extsb (void) +{ + __asm__ __volatile__ ("extsb 17, 14"); +} + +static void test_extsh (void) +{ + __asm__ __volatile__ ("extsh 17, 14"); +} + +static void test_neg (void) +{ + __asm__ __volatile__ ("neg 17, 14"); +} + +static void test_nego (void) +{ + __asm__ __volatile__ ("nego 17, 14"); +} + +static test_t tests_il_ops_one[] = { + { &test_cntlzw , " cntlzw", }, + { &test_extsb , " extsb", }, + { &test_extsh , " extsh", }, + { &test_neg , " neg", }, + { &test_nego , " nego", }, + { NULL, NULL, }, +}; + +static void test_cntlzw_ (void) +{ + __asm__ __volatile__ ("cntlzw. 17, 14"); +} + +static void test_extsb_ (void) +{ + __asm__ __volatile__ ("extsb. 17, 14"); +} + +static void test_extsh_ (void) +{ + __asm__ __volatile__ ("extsh. 17, 14"); +} + +static void test_neg_ (void) +{ + __asm__ __volatile__ ("neg. 17, 14"); +} + +static void test_nego_ (void) +{ + __asm__ __volatile__ ("nego. 17, 14"); +} + +static test_t tests_ilr_ops_one[] = { + { &test_cntlzw_ , " cntlzw.", }, + { &test_extsb_ , " extsb.", }, + { &test_extsh_ , " extsh.", }, + { &test_neg_ , " neg.", }, + { &test_nego_ , " nego.", }, + { NULL, NULL, }, +}; + +static void test_rlwimi (void) +{ + __asm__ __volatile__ ("rlwimi 17, 14, 0, 0, 0"); +} + +static void test_rlwinm (void) +{ + __asm__ __volatile__ ("rlwinm 17, 14, 0, 0, 0"); +} + +static void test_rlwnm (void) +{ + __asm__ __volatile__ ("rlwnm 17, 14, 15, 0, 0"); +} + +static void test_srawi (void) +{ + __asm__ __volatile__ ("srawi 17, 14, 0"); +} + +static void test_mfcr (void) +{ + __asm__ __volatile__ ("mfcr 17"); +} + +static void test_mfspr (void) +{ + __asm__ __volatile__ ("mfspr 17, 1"); +} + +static void test_mtspr (void) +{ + __asm__ __volatile__ ("mtspr 1, 14"); +} + +static test_t tests_il_ops_spe[] = { + { &test_rlwimi , " rlwimi", }, + { &test_rlwinm , " rlwinm", }, + { &test_rlwnm , " rlwnm", }, + { &test_srawi , " srawi", }, + { &test_mfcr , " mfcr", }, + { &test_mfspr , " mfspr", }, + { &test_mtspr , " mtspr", }, + { NULL, NULL, }, +}; + +static void test_rlwimi_ (void) +{ + __asm__ __volatile__ ("rlwimi. 17, 14, 0, 0, 0"); +} + +static void test_rlwinm_ (void) +{ + __asm__ __volatile__ ("rlwinm. 17, 14, 0, 0, 0"); +} + +static void test_rlwnm_ (void) +{ + __asm__ __volatile__ ("rlwnm. 17, 14, 15, 0, 0"); +} + +static void test_srawi_ (void) +{ + __asm__ __volatile__ ("srawi. 17, 14, 0"); +} + +static void test_mcrf (void) +{ + __asm__ __volatile__ ("mcrf 0, 0"); +} + +static void test_mcrxr (void) +{ + __asm__ __volatile__ ("mcrxr 0"); +} + +static void test_mtcrf (void) +{ + __asm__ __volatile__ ("mtcrf 0, 14"); +} + +static test_t tests_ilr_ops_spe[] = { + { &test_rlwimi_ , " rlwimi.", }, + { &test_rlwinm_ , " rlwinm.", }, + { &test_rlwnm_ , " rlwnm.", }, + { &test_srawi_ , " srawi.", }, + { &test_mcrf , " mcrf", }, + { &test_mcrxr , " mcrxr", }, + { &test_mtcrf , " mtcrf", }, + { NULL, NULL, }, +}; + +static void test_lbz (void) +{ + __asm__ __volatile__ ("lbz 17,0(14)"); +} + +static void test_lbzu (void) +{ + __asm__ __volatile__ ("lbzu 17,0(14)"); +} + +static void test_lha (void) +{ + __asm__ __volatile__ ("lha 17,0(14)"); +} + +static void test_lhau (void) +{ + __asm__ __volatile__ ("lhau 17,0(14)"); +} + +static void test_lhz (void) +{ + __asm__ __volatile__ ("lhz 17,0(14)"); +} + +static void test_lhzu (void) +{ + __asm__ __volatile__ ("lhzu 17,0(14)"); +} + +static void test_lwz (void) +{ + __asm__ __volatile__ ("lwz 17,0(14)"); +} + +static void test_lwzu (void) +{ + __asm__ __volatile__ ("lwzu 17,0(14)"); +} + +static test_t tests_ild_ops_two_i16[] = { + { &test_lbz , " lbz", }, + { &test_lbzu , " lbzu", }, + { &test_lha , " lha", }, + { &test_lhau , " lhau", }, + { &test_lhz , " lhz", }, + { &test_lhzu , " lhzu", }, + { &test_lwz , " lwz", }, + { &test_lwzu , " lwzu", }, + { NULL, NULL, }, +}; + +static void test_lbzx (void) +{ + __asm__ __volatile__ ("lbzx 17,14,15"); +} + +static void test_lbzux (void) +{ + __asm__ __volatile__ ("lbzux 17,14,15"); +} + +static void test_lhax (void) +{ + __asm__ __volatile__ ("lhax 17,14,15"); +} + +static void test_lhaux (void) +{ + __asm__ __volatile__ ("lhaux 17,14,15"); +} + +static void test_lhzx (void) +{ + __asm__ __volatile__ ("lhzx 17,14,15"); +} + +static void test_lhzux (void) +{ + __asm__ __volatile__ ("lhzux 17,14,15"); +} + +static void test_lwzx (void) +{ + __asm__ __volatile__ ("lwzx 17,14,15"); +} + +static void test_lwzux (void) +{ + __asm__ __volatile__ ("lwzux 17,14,15"); +} + +static test_t tests_ild_ops_two[] = { + { &test_lbzx , " lbzx", }, + { &test_lbzux , " lbzux", }, + { &test_lhax , " lhax", }, + { &test_lhaux , " lhaux", }, + { &test_lhzx , " lhzx", }, + { &test_lhzux , " lhzux", }, + { &test_lwzx , " lwzx", }, + { &test_lwzux , " lwzux", }, + { NULL, NULL, }, +}; + +static void test_stb (void) +{ + __asm__ __volatile__ ("stb 14,0(15)"); +} + +static void test_stbu (void) +{ + __asm__ __volatile__ ("stbu 14,0(15)"); +} + +static void test_sth (void) +{ + __asm__ __volatile__ ("sth 14,0(15)"); +} + +static void test_sthu (void) +{ + __asm__ __volatile__ ("sthu 14,0(15)"); +} + +static void test_stw (void) +{ + __asm__ __volatile__ ("stw 14,0(15)"); +} + +static void test_stwu (void) +{ + __asm__ __volatile__ ("stwu 14,0(15)"); +} + +static test_t tests_ist_ops_three_i16[] = { + { &test_stb , " stb", }, + { &test_stbu , " stbu", }, + { &test_sth , " sth", }, + { &test_sthu , " sthu", }, + { &test_stw , " stw", }, + { &test_stwu , " stwu", }, + { NULL, NULL, }, +}; + +static void test_stbx (void) +{ + __asm__ __volatile__ ("stbx 14,15,16"); +} + +static void test_stbux (void) +{ + __asm__ __volatile__ ("stbux 14,15,16"); +} + +static void test_sthx (void) +{ + __asm__ __volatile__ ("sthx 14,15,16"); +} + +static void test_sthux (void) +{ + __asm__ __volatile__ ("sthux 14,15,16"); +} + +static void test_stwx (void) +{ + __asm__ __volatile__ ("stwx 14,15,16"); +} + +static void test_stwux (void) +{ + __asm__ __volatile__ ("stwux 14,15,16"); +} + +static test_t tests_ist_ops_three[] = { + { &test_stbx , " stbx", }, + { &test_stbux , " stbux", }, + { &test_sthx , " sthx", }, + { &test_sthux , " sthux", }, + { &test_stwx , " stwx", }, + { &test_stwux , " stwux", }, + { NULL, NULL, }, +}; + +#if !defined (NO_FLOAT) +static void test_fsel (void) +{ + __asm__ __volatile__ ("fsel 17, 14, 15, 16"); +} + +static void test_fmadd (void) +{ + __asm__ __volatile__ ("fmadd 17, 14, 15, 16"); +} + +static void test_fmadds (void) +{ + __asm__ __volatile__ ("fmadds 17, 14, 15, 16"); +} + +static void test_fmsub (void) +{ + __asm__ __volatile__ ("fmsub 17, 14, 15, 16"); +} + +static void test_fmsubs (void) +{ + __asm__ __volatile__ ("fmsubs 17, 14, 15, 16"); +} + +static void test_fnmadd (void) +{ + __asm__ __volatile__ ("fnmadd 17, 14, 15, 16"); +} + +static void test_fnmadds (void) +{ + __asm__ __volatile__ ("fnmadds 17, 14, 15, 16"); +} + +static void test_fnmsub (void) +{ + __asm__ __volatile__ ("fnmsub 17, 14, 15, 16"); +} + +static void test_fnmsubs (void) +{ + __asm__ __volatile__ ("fnmsubs 17, 14, 15, 16"); +} + +static test_t tests_fa_ops_three[] = { + { &test_fsel , " fsel", }, + { &test_fmadd , " fmadd", }, + { &test_fmadds , " fmadds", }, + { &test_fmsub , " fmsub", }, + { &test_fmsubs , " fmsubs", }, + { &test_fnmadd , " fnmadd", }, + { &test_fnmadds , " fnmadds", }, + { &test_fnmsub , " fnmsub", }, + { &test_fnmsubs , " fnmsubs", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fsel_ (void) +{ + __asm__ __volatile__ ("fsel. 17, 14, 15, 16"); +} + +static void test_fmadd_ (void) +{ + __asm__ __volatile__ ("fmadd. 17, 14, 15, 16"); +} + +static void test_fmadds_ (void) +{ + __asm__ __volatile__ ("fmadds. 17, 14, 15, 16"); +} + +static void test_fmsub_ (void) +{ + __asm__ __volatile__ ("fmsub. 17, 14, 15, 16"); +} + +static void test_fmsubs_ (void) +{ + __asm__ __volatile__ ("fmsubs. 17, 14, 15, 16"); +} + +static void test_fnmadd_ (void) +{ + __asm__ __volatile__ ("fnmadd. 17, 14, 15, 16"); +} + +static void test_fnmadds_ (void) +{ + __asm__ __volatile__ ("fnmadds. 17, 14, 15, 16"); +} + +static void test_fnmsub_ (void) +{ + __asm__ __volatile__ ("fnmsub. 17, 14, 15, 16"); +} + +static void test_fnmsubs_ (void) +{ + __asm__ __volatile__ ("fnmsubs. 17, 14, 15, 16"); +} + +static test_t tests_far_ops_three[] = { + { &test_fsel_ , " fsel.", }, + { &test_fmadd_ , " fmadd.", }, + { &test_fmadds_ , " fmadds.", }, + { &test_fmsub_ , " fmsub.", }, + { &test_fmsubs_ , " fmsubs.", }, + { &test_fnmadd_ , " fnmadd.", }, + { &test_fnmadds_ , " fnmadds.", }, + { &test_fnmsub_ , " fnmsub.", }, + { &test_fnmsubs_ , " fnmsubs.", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fadd (void) +{ + __asm__ __volatile__ ("fadd 17, 14, 15"); +} + +static void test_fadds (void) +{ + __asm__ __volatile__ ("fadds 17, 14, 15"); +} + +static void test_fsub (void) +{ + __asm__ __volatile__ ("fsub 17, 14, 15"); +} + +static void test_fsubs (void) +{ + __asm__ __volatile__ ("fsubs 17, 14, 15"); +} + +static void test_fmul (void) +{ + __asm__ __volatile__ ("fmul 17, 14, 15"); +} + +static void test_fmuls (void) +{ + __asm__ __volatile__ ("fmuls 17, 14, 15"); +} + +static void test_fdiv (void) +{ + __asm__ __volatile__ ("fdiv 17, 14, 15"); +} + +static void test_fdivs (void) +{ + __asm__ __volatile__ ("fdivs 17, 14, 15"); +} + +static test_t tests_fa_ops_two[] = { + { &test_fadd , " fadd", }, + { &test_fadds , " fadds", }, + { &test_fsub , " fsub", }, + { &test_fsubs , " fsubs", }, + { &test_fmul , " fmul", }, + { &test_fmuls , " fmuls", }, + { &test_fdiv , " fdiv", }, + { &test_fdivs , " fdivs", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fadd_ (void) +{ + __asm__ __volatile__ ("fadd. 17, 14, 15"); +} + +static void test_fadds_ (void) +{ + __asm__ __volatile__ ("fadds. 17, 14, 15"); +} + +static void test_fsub_ (void) +{ + __asm__ __volatile__ ("fsub. 17, 14, 15"); +} + +static void test_fsubs_ (void) +{ + __asm__ __volatile__ ("fsubs. 17, 14, 15"); +} + +static void test_fmul_ (void) +{ + __asm__ __volatile__ ("fmul. 17, 14, 15"); +} + +static void test_fmuls_ (void) +{ + __asm__ __volatile__ ("fmuls. 17, 14, 15"); +} + +static void test_fdiv_ (void) +{ + __asm__ __volatile__ ("fdiv. 17, 14, 15"); +} + +static void test_fdivs_ (void) +{ + __asm__ __volatile__ ("fdivs. 17, 14, 15"); +} + +static test_t tests_far_ops_two[] = { + { &test_fadd_ , " fadd.", }, + { &test_fadds_ , " fadds.", }, + { &test_fsub_ , " fsub.", }, + { &test_fsubs_ , " fsubs.", }, + { &test_fmul_ , " fmul.", }, + { &test_fmuls_ , " fmuls.", }, + { &test_fdiv_ , " fdiv.", }, + { &test_fdivs_ , " fdivs.", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fcmpo (void) +{ + __asm__ __volatile__ ("fcmpo 2, 14, 15"); +} + +static void test_fcmpu (void) +{ + __asm__ __volatile__ ("fcmpu 2, 14, 15"); +} + +static test_t tests_fcr_ops_two[] = { + { &test_fcmpo , " fcmpo", }, + { &test_fcmpu , " fcmpu", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fres (void) +{ + __asm__ __volatile__ ("fres 17, 14"); +} + +static void test_frsqrte (void) +{ + __asm__ __volatile__ ("frsqrte 17, 14"); +} + +static void test_frsp (void) +{ + __asm__ __volatile__ ("frsp 17, 14"); +} + +static void test_fctiw (void) +{ + __asm__ __volatile__ ("fctiw 17, 14"); +} + +static void test_fctiwz (void) +{ + __asm__ __volatile__ ("fctiwz 17, 14"); +} + +static void test_fmr (void) +{ + __asm__ __volatile__ ("fmr 17, 14"); +} + +static void test_fneg (void) +{ + __asm__ __volatile__ ("fneg 17, 14"); +} + +static void test_fabs (void) +{ + __asm__ __volatile__ ("fabs 17, 14"); +} + +static void test_fnabs (void) +{ + __asm__ __volatile__ ("fnabs 17, 14"); +} + +static test_t tests_fa_ops_one[] = { + { &test_fres , " fres", }, + { &test_frsqrte , " frsqrte", }, + { &test_frsp , " frsp", }, + { &test_fctiw , " fctiw", }, + { &test_fctiwz , " fctiwz", }, + { &test_fmr , " fmr", }, + { &test_fneg , " fneg", }, + { &test_fabs , " fabs", }, + { &test_fnabs , " fnabs", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static void test_fres_ (void) +{ + __asm__ __volatile__ ("fres. 17, 14"); +} + +static void test_frsqrte_ (void) +{ + __asm__ __volatile__ ("frsqrte. 17, 14"); +} + +static void test_frsp_ (void) +{ + __asm__ __volatile__ ("frsp. 17, 14"); +} + +static void test_fctiw_ (void) +{ + __asm__ __volatile__ ("fctiw. 17, 14"); +} + +static void test_fctiwz_ (void) +{ + __asm__ __volatile__ ("fctiwz. 17, 14"); +} + +static void test_fmr_ (void) +{ + __asm__ __volatile__ ("fmr. 17, 14"); +} + +static void test_fneg_ (void) +{ + __asm__ __volatile__ ("fneg. 17, 14"); +} + +static void test_fabs_ (void) +{ + __asm__ __volatile__ ("fabs. 17, 14"); +} + +static void test_fnabs_ (void) +{ + __asm__ __volatile__ ("fnabs. 17, 14"); +} + +static test_t tests_far_ops_one[] = { + { &test_fres_ , " fres.", }, + { &test_frsqrte_ , " frsqrte.", }, + { &test_frsp_ , " frsp.", }, + { &test_fctiw_ , " fctiw.", }, + { &test_fctiwz_ , " fctiwz.", }, + { &test_fmr_ , " fmr.", }, + { &test_fneg_ , " fneg.", }, + { &test_fabs_ , " fabs.", }, + { &test_fnabs_ , " fnabs.", }, + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static test_t tests_fl_ops_spe[] = { + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if !defined (NO_FLOAT) +static test_t tests_flr_ops_spe[] = { + { NULL, NULL, }, +}; +#endif /* !defined (NO_FLOAT) */ + +#if defined (HAS_ALTIVEC) +static void test_vmhaddshs (void) +{ + __asm__ __volatile__ ("vmhaddshs 17, 14, 15, 16"); +} + +static void test_vmhraddshs (void) +{ + __asm__ __volatile__ ("vmhraddshs 17, 14, 15, 16"); +} + +static void test_vmladduhm (void) +{ + __asm__ __volatile__ ("vmladduhm 17, 14, 15, 16"); +} + +static void test_vmsumubm (void) +{ + __asm__ __volatile__ ("vmsumubm 17, 14, 15, 16"); +} + +static void test_vmsumuhm (void) +{ + __asm__ __volatile__ ("vmsumuhm 17, 14, 15, 16"); +} + +static void test_vmsumshs (void) +{ + __asm__ __volatile__ ("vmsumshs 17, 14, 15, 16"); +} + +static void test_vmsumuhs (void) +{ + __asm__ __volatile__ ("vmsumuhs 17, 14, 15, 16"); +} + +static void test_vmsummbm (void) +{ + __asm__ __volatile__ ("vmsummbm 17, 14, 15, 16"); +} + +static void test_vmsumshm (void) +{ + __asm__ __volatile__ ("vmsumshm 17, 14, 15, 16"); +} + +static test_t tests_aa_ops_three[] = { + { &test_vmhaddshs , " vmhaddshs", }, + { &test_vmhraddshs , " vmhraddshs", }, + { &test_vmladduhm , " vmladduhm", }, + { &test_vmsumubm , " vmsumubm", }, + { &test_vmsumuhm , " vmsumuhm", }, + { &test_vmsumshs , " vmsumshs", }, + { &test_vmsumuhs , " vmsumuhs", }, + { &test_vmsummbm , " vmsummbm", }, + { &test_vmsumshm , " vmsumshm", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vperm (void) +{ + __asm__ __volatile__ ("vperm 17, 14, 15, 16"); +} + +static void test_vsel (void) +{ + __asm__ __volatile__ ("vsel 17, 14, 15, 16"); +} + +static test_t tests_al_ops_three[] = { + { &test_vperm , " vperm", }, + { &test_vsel , " vsel", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vaddubm (void) +{ + __asm__ __volatile__ ("vaddubm 17, 14, 15"); +} + +static void test_vadduhm (void) +{ + __asm__ __volatile__ ("vadduhm 17, 14, 15"); +} + +static void test_vadduwm (void) +{ + __asm__ __volatile__ ("vadduwm 17, 14, 15"); +} + +static void test_vaddubs (void) +{ + __asm__ __volatile__ ("vaddubs 17, 14, 15"); +} + +static void test_vadduhs (void) +{ + __asm__ __volatile__ ("vadduhs 17, 14, 15"); +} + +static void test_vadduws (void) +{ + __asm__ __volatile__ ("vadduws 17, 14, 15"); +} + +static void test_vaddsbs (void) +{ + __asm__ __volatile__ ("vaddsbs 17, 14, 15"); +} + +static void test_vaddshs (void) +{ + __asm__ __volatile__ ("vaddshs 17, 14, 15"); +} + +static void test_vaddsws (void) +{ + __asm__ __volatile__ ("vaddsws 17, 14, 15"); +} + +static void test_vaddcuw (void) +{ + __asm__ __volatile__ ("vaddcuw 17, 14, 15"); +} + +static void test_vsububm (void) +{ + __asm__ __volatile__ ("vsububm 17, 14, 15"); +} + +static void test_vsubuhm (void) +{ + __asm__ __volatile__ ("vsubuhm 17, 14, 15"); +} + +static void test_vsubuwm (void) +{ + __asm__ __volatile__ ("vsubuwm 17, 14, 15"); +} + +static void test_vsububs (void) +{ + __asm__ __volatile__ ("vsububs 17, 14, 15"); +} + +static void test_vsubuhs (void) +{ + __asm__ __volatile__ ("vsubuhs 17, 14, 15"); +} + +static void test_vsubuws (void) +{ + __asm__ __volatile__ ("vsubuws 17, 14, 15"); +} + +static void test_vsubsbs (void) +{ + __asm__ __volatile__ ("vsubsbs 17, 14, 15"); +} + +static void test_vsubshs (void) +{ + __asm__ __volatile__ ("vsubshs 17, 14, 15"); +} + +static void test_vsubsws (void) +{ + __asm__ __volatile__ ("vsubsws 17, 14, 15"); +} + +static void test_vsubcuw (void) +{ + __asm__ __volatile__ ("vsubcuw 17, 14, 15"); +} + +static void test_vmuloub (void) +{ + __asm__ __volatile__ ("vmuloub 17, 14, 15"); +} + +static void test_vmulouh (void) +{ + __asm__ __volatile__ ("vmulouh 17, 14, 15"); +} + +static void test_vmulosb (void) +{ + __asm__ __volatile__ ("vmulosb 17, 14, 15"); +} + +static void test_vmulosh (void) +{ + __asm__ __volatile__ ("vmulosh 17, 14, 15"); +} + +static void test_vmuleub (void) +{ + __asm__ __volatile__ ("vmuleub 17, 14, 15"); +} + +static void test_vmuleuh (void) +{ + __asm__ __volatile__ ("vmuleuh 17, 14, 15"); +} + +static void test_vmulesb (void) +{ + __asm__ __volatile__ ("vmulesb 17, 14, 15"); +} + +static void test_vmulesh (void) +{ + __asm__ __volatile__ ("vmulesh 17, 14, 15"); +} + +static void test_vsumsws (void) +{ + __asm__ __volatile__ ("vsumsws 17, 14, 15"); +} + +static void test_vsum2sws (void) +{ + __asm__ __volatile__ ("vsum2sws 17, 14, 15"); +} + +static void test_vsum4ubs (void) +{ + __asm__ __volatile__ ("vsum4ubs 17, 14, 15"); +} + +static void test_vsum4sbs (void) +{ + __asm__ __volatile__ ("vsum4sbs 17, 14, 15"); +} + +static void test_vsum4shs (void) +{ + __asm__ __volatile__ ("vsum4shs 17, 14, 15"); +} + +static void test_vavgub (void) +{ + __asm__ __volatile__ ("vavgub 17, 14, 15"); +} + +static void test_vavguh (void) +{ + __asm__ __volatile__ ("vavguh 17, 14, 15"); +} + +static void test_vavguw (void) +{ + __asm__ __volatile__ ("vavguw 17, 14, 15"); +} + +static void test_vavgsb (void) +{ + __asm__ __volatile__ ("vavgsb 17, 14, 15"); +} + +static void test_vavgsh (void) +{ + __asm__ __volatile__ ("vavgsh 17, 14, 15"); +} + +static void test_vavgsw (void) +{ + __asm__ __volatile__ ("vavgsw 17, 14, 15"); +} + +static void test_vmaxub (void) +{ + __asm__ __volatile__ ("vmaxub 17, 14, 15"); +} + +static void test_vmaxuh (void) +{ + __asm__ __volatile__ ("vmaxuh 17, 14, 15"); +} + +static void test_vmaxuw (void) +{ + __asm__ __volatile__ ("vmaxuw 17, 14, 15"); +} + +static void test_vmaxsb (void) +{ + __asm__ __volatile__ ("vmaxsb 17, 14, 15"); +} + +static void test_vmaxsh (void) +{ + __asm__ __volatile__ ("vmaxsh 17, 14, 15"); +} + +static void test_vmaxsw (void) +{ + __asm__ __volatile__ ("vmaxsw 17, 14, 15"); +} + +static void test_vminub (void) +{ + __asm__ __volatile__ ("vminub 17, 14, 15"); +} + +static void test_vminuh (void) +{ + __asm__ __volatile__ ("vminuh 17, 14, 15"); +} + +static void test_vminuw (void) +{ + __asm__ __volatile__ ("vminuw 17, 14, 15"); +} + +static void test_vminsb (void) +{ + __asm__ __volatile__ ("vminsb 17, 14, 15"); +} + +static void test_vminsh (void) +{ + __asm__ __volatile__ ("vminsh 17, 14, 15"); +} + +static void test_vminsw (void) +{ + __asm__ __volatile__ ("vminsw 17, 14, 15"); +} + +static test_t tests_aa_ops_two[] = { + { &test_vaddubm , " vaddubm", }, + { &test_vadduhm , " vadduhm", }, + { &test_vadduwm , " vadduwm", }, + { &test_vaddubs , " vaddubs", }, + { &test_vadduhs , " vadduhs", }, + { &test_vadduws , " vadduws", }, + { &test_vaddsbs , " vaddsbs", }, + { &test_vaddshs , " vaddshs", }, + { &test_vaddsws , " vaddsws", }, + { &test_vaddcuw , " vaddcuw", }, + { &test_vsububm , " vsububm", }, + { &test_vsubuhm , " vsubuhm", }, + { &test_vsubuwm , " vsubuwm", }, + { &test_vsububs , " vsububs", }, + { &test_vsubuhs , " vsubuhs", }, + { &test_vsubuws , " vsubuws", }, + { &test_vsubsbs , " vsubsbs", }, + { &test_vsubshs , " vsubshs", }, + { &test_vsubsws , " vsubsws", }, + { &test_vsubcuw , " vsubcuw", }, + { &test_vmuloub , " vmuloub", }, + { &test_vmulouh , " vmulouh", }, + { &test_vmulosb , " vmulosb", }, + { &test_vmulosh , " vmulosh", }, + { &test_vmuleub , " vmuleub", }, + { &test_vmuleuh , " vmuleuh", }, + { &test_vmulesb , " vmulesb", }, + { &test_vmulesh , " vmulesh", }, + { &test_vsumsws , " vsumsws", }, + { &test_vsum2sws , " vsum2sws", }, + { &test_vsum4ubs , " vsum4ubs", }, + { &test_vsum4sbs , " vsum4sbs", }, + { &test_vsum4shs , " vsum4shs", }, + { &test_vavgub , " vavgub", }, + { &test_vavguh , " vavguh", }, + { &test_vavguw , " vavguw", }, + { &test_vavgsb , " vavgsb", }, + { &test_vavgsh , " vavgsh", }, + { &test_vavgsw , " vavgsw", }, + { &test_vmaxub , " vmaxub", }, + { &test_vmaxuh , " vmaxuh", }, + { &test_vmaxuw , " vmaxuw", }, + { &test_vmaxsb , " vmaxsb", }, + { &test_vmaxsh , " vmaxsh", }, + { &test_vmaxsw , " vmaxsw", }, + { &test_vminub , " vminub", }, + { &test_vminuh , " vminuh", }, + { &test_vminuw , " vminuw", }, + { &test_vminsb , " vminsb", }, + { &test_vminsh , " vminsh", }, + { &test_vminsw , " vminsw", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vand (void) +{ + __asm__ __volatile__ ("vand 17, 14, 15"); +} + +static void test_vor (void) +{ + __asm__ __volatile__ ("vor 17, 14, 15"); +} + +static void test_vxor (void) +{ + __asm__ __volatile__ ("vxor 17, 14, 15"); +} + +static void test_vandc (void) +{ + __asm__ __volatile__ ("vandc 17, 14, 15"); +} + +static void test_vnor (void) +{ + __asm__ __volatile__ ("vnor 17, 14, 15"); +} + +static void test_vrlb (void) +{ + __asm__ __volatile__ ("vrlb 17, 14, 15"); +} + +static void test_vrlh (void) +{ + __asm__ __volatile__ ("vrlh 17, 14, 15"); +} + +static void test_vrlw (void) +{ + __asm__ __volatile__ ("vrlw 17, 14, 15"); +} + +static void test_vslb (void) +{ + __asm__ __volatile__ ("vslb 17, 14, 15"); +} + +static void test_vslh (void) +{ + __asm__ __volatile__ ("vslh 17, 14, 15"); +} + +static void test_vslw (void) +{ + __asm__ __volatile__ ("vslw 17, 14, 15"); +} + +static void test_vsrb (void) +{ + __asm__ __volatile__ ("vsrb 17, 14, 15"); +} + +static void test_vsrh (void) +{ + __asm__ __volatile__ ("vsrh 17, 14, 15"); +} + +static void test_vsrw (void) +{ + __asm__ __volatile__ ("vsrw 17, 14, 15"); +} + +static void test_vsrab (void) +{ + __asm__ __volatile__ ("vsrab 17, 14, 15"); +} + +static void test_vsrah (void) +{ + __asm__ __volatile__ ("vsrah 17, 14, 15"); +} + +static void test_vsraw (void) +{ + __asm__ __volatile__ ("vsraw 17, 14, 15"); +} + +static void test_vpkuhum (void) +{ + __asm__ __volatile__ ("vpkuhum 17, 14, 15"); +} + +static void test_vpkuwum (void) +{ + __asm__ __volatile__ ("vpkuwum 17, 14, 15"); +} + +static void test_vpkuhus (void) +{ + __asm__ __volatile__ ("vpkuhus 17, 14, 15"); +} + +static void test_vpkuwus (void) +{ + __asm__ __volatile__ ("vpkuwus 17, 14, 15"); +} + +static void test_vpkshus (void) +{ + __asm__ __volatile__ ("vpkshus 17, 14, 15"); +} + +static void test_vpkswus (void) +{ + __asm__ __volatile__ ("vpkswus 17, 14, 15"); +} + +static void test_vpkshss (void) +{ + __asm__ __volatile__ ("vpkshss 17, 14, 15"); +} + +static void test_vpkswss (void) +{ + __asm__ __volatile__ ("vpkswss 17, 14, 15"); +} + +static void test_vpkpx (void) +{ + __asm__ __volatile__ ("vpkpx 17, 14, 15"); +} + +static void test_vmrghb (void) +{ + __asm__ __volatile__ ("vmrghb 17, 14, 15"); +} + +static void test_vmrghh (void) +{ + __asm__ __volatile__ ("vmrghh 17, 14, 15"); +} + +static void test_vmrghw (void) +{ + __asm__ __volatile__ ("vmrghw 17, 14, 15"); +} + +static void test_vmrglb (void) +{ + __asm__ __volatile__ ("vmrglb 17, 14, 15"); +} + +static void test_vmrglh (void) +{ + __asm__ __volatile__ ("vmrglh 17, 14, 15"); +} + +static void test_vmrglw (void) +{ + __asm__ __volatile__ ("vmrglw 17, 14, 15"); +} + +static void test_vslo (void) +{ + __asm__ __volatile__ ("vslo 17, 14, 15"); +} + +static void test_vsro (void) +{ + __asm__ __volatile__ ("vsro 17, 14, 15"); +} + +static test_t tests_al_ops_two[] = { + { &test_vand , " vand", }, + { &test_vor , " vor", }, + { &test_vxor , " vxor", }, + { &test_vandc , " vandc", }, + { &test_vnor , " vnor", }, + { &test_vrlb , " vrlb", }, + { &test_vrlh , " vrlh", }, + { &test_vrlw , " vrlw", }, + { &test_vslb , " vslb", }, + { &test_vslh , " vslh", }, + { &test_vslw , " vslw", }, + { &test_vsrb , " vsrb", }, + { &test_vsrh , " vsrh", }, + { &test_vsrw , " vsrw", }, + { &test_vsrab , " vsrab", }, + { &test_vsrah , " vsrah", }, + { &test_vsraw , " vsraw", }, + { &test_vpkuhum , " vpkuhum", }, + { &test_vpkuwum , " vpkuwum", }, + { &test_vpkuhus , " vpkuhus", }, + { &test_vpkuwus , " vpkuwus", }, + { &test_vpkshus , " vpkshus", }, + { &test_vpkswus , " vpkswus", }, + { &test_vpkshss , " vpkshss", }, + { &test_vpkswss , " vpkswss", }, + { &test_vpkpx , " vpkpx", }, + { &test_vmrghb , " vmrghb", }, + { &test_vmrghh , " vmrghh", }, + { &test_vmrghw , " vmrghw", }, + { &test_vmrglb , " vmrglb", }, + { &test_vmrglh , " vmrglh", }, + { &test_vmrglw , " vmrglw", }, + { &test_vslo , " vslo", }, + { &test_vsro , " vsro", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vupkhsb (void) +{ + __asm__ __volatile__ ("vupkhsb 17, 14"); +} + +static void test_vupkhsh (void) +{ + __asm__ __volatile__ ("vupkhsh 17, 14"); +} + +static void test_vupkhpx (void) +{ + __asm__ __volatile__ ("vupkhpx 17, 14"); +} + +static void test_vupklsb (void) +{ + __asm__ __volatile__ ("vupklsb 17, 14"); +} + +static void test_vupklsh (void) +{ + __asm__ __volatile__ ("vupklsh 17, 14"); +} + +static void test_vupklpx (void) +{ + __asm__ __volatile__ ("vupklpx 17, 14"); +} + +static test_t tests_al_ops_one[] = { + { &test_vupkhsb , " vupkhsb", }, + { &test_vupkhsh , " vupkhsh", }, + { &test_vupkhpx , " vupkhpx", }, + { &test_vupklsb , " vupklsb", }, + { &test_vupklsh , " vupklsh", }, + { &test_vupklpx , " vupklpx", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vcmpgtub (void) +{ + __asm__ __volatile__ ("vcmpgtub 17, 14, 15"); +} + +static void test_vcmpgtuh (void) +{ + __asm__ __volatile__ ("vcmpgtuh 17, 14, 15"); +} + +static void test_vcmpgtuw (void) +{ + __asm__ __volatile__ ("vcmpgtuw 17, 14, 15"); +} + +static void test_vcmpgtsb (void) +{ + __asm__ __volatile__ ("vcmpgtsb 17, 14, 15"); +} + +static void test_vcmpgtsh (void) +{ + __asm__ __volatile__ ("vcmpgtsh 17, 14, 15"); +} + +static void test_vcmpgtsw (void) +{ + __asm__ __volatile__ ("vcmpgtsw 17, 14, 15"); +} + +static void test_vcmpequb (void) +{ + __asm__ __volatile__ ("vcmpequb 17, 14, 15"); +} + +static void test_vcmpequh (void) +{ + __asm__ __volatile__ ("vcmpequh 17, 14, 15"); +} + +static void test_vcmpequw (void) +{ + __asm__ __volatile__ ("vcmpequw 17, 14, 15"); +} + +static test_t tests_ac_ops_two[] = { + { &test_vcmpgtub , " vcmpgtub", }, + { &test_vcmpgtuh , " vcmpgtuh", }, + { &test_vcmpgtuw , " vcmpgtuw", }, + { &test_vcmpgtsb , " vcmpgtsb", }, + { &test_vcmpgtsh , " vcmpgtsh", }, + { &test_vcmpgtsw , " vcmpgtsw", }, + { &test_vcmpequb , " vcmpequb", }, + { &test_vcmpequh , " vcmpequh", }, + { &test_vcmpequw , " vcmpequw", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vcmpgtub_ (void) +{ + __asm__ __volatile__ ("vcmpgtub. 17, 14, 15"); +} + +static void test_vcmpgtuh_ (void) +{ + __asm__ __volatile__ ("vcmpgtuh. 17, 14, 15"); +} + +static void test_vcmpgtuw_ (void) +{ + __asm__ __volatile__ ("vcmpgtuw. 17, 14, 15"); +} + +static void test_vcmpgtsb_ (void) +{ + __asm__ __volatile__ ("vcmpgtsb. 17, 14, 15"); +} + +static void test_vcmpgtsh_ (void) +{ + __asm__ __volatile__ ("vcmpgtsh. 17, 14, 15"); +} + +static void test_vcmpgtsw_ (void) +{ + __asm__ __volatile__ ("vcmpgtsw. 17, 14, 15"); +} + +static void test_vcmpequb_ (void) +{ + __asm__ __volatile__ ("vcmpequb. 17, 14, 15"); +} + +static void test_vcmpequh_ (void) +{ + __asm__ __volatile__ ("vcmpequh. 17, 14, 15"); +} + +static void test_vcmpequw_ (void) +{ + __asm__ __volatile__ ("vcmpequw. 17, 14, 15"); +} + +static test_t tests_acr_ops_two[] = { + { &test_vcmpgtub_ , " vcmpgtub.", }, + { &test_vcmpgtuh_ , " vcmpgtuh.", }, + { &test_vcmpgtuw_ , " vcmpgtuw.", }, + { &test_vcmpgtsb_ , " vcmpgtsb.", }, + { &test_vcmpgtsh_ , " vcmpgtsh.", }, + { &test_vcmpgtsw_ , " vcmpgtsw.", }, + { &test_vcmpequb_ , " vcmpequb.", }, + { &test_vcmpequh_ , " vcmpequh.", }, + { &test_vcmpequw_ , " vcmpequw.", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vsl (void) +{ + __asm__ __volatile__ ("vsl 17, 14, 15"); +} + +static void test_vsr (void) +{ + __asm__ __volatile__ ("vsr 17, 14, 15"); +} + +static void test_vspltb (void) +{ + __asm__ __volatile__ ("vspltb 17, 14, 0"); +} + +static void test_vsplth (void) +{ + __asm__ __volatile__ ("vsplth 17, 14, 0"); +} + +static void test_vspltw (void) +{ + __asm__ __volatile__ ("vspltw 17, 14, 0"); +} + +static void test_vspltisb (void) +{ + __asm__ __volatile__ ("vspltisb 17, 0"); +} + +static void test_vspltish (void) +{ + __asm__ __volatile__ ("vspltish 17, 0"); +} + +static void test_vspltisw (void) +{ + __asm__ __volatile__ ("vspltisw 17, 0"); +} + +static void test_vsldoi (void) +{ + __asm__ __volatile__ ("vsldoi 17, 14, 15, 0"); +} + +static test_t tests_av_int_ops_spe[] = { + { &test_vsl , " vsl", }, + { &test_vsr , " vsr", }, + { &test_vspltb , " vspltb", }, + { &test_vsplth , " vsplth", }, + { &test_vspltw , " vspltw", }, + { &test_vspltisb , " vspltisb", }, + { &test_vspltish , " vspltish", }, + { &test_vspltisw , " vspltisw", }, + { &test_vsldoi , " vsldoi", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vmaddfp (void) +{ + __asm__ __volatile__ ("vmaddfp 17, 14, 15, 16"); +} + +static void test_vnmsubfp (void) +{ + __asm__ __volatile__ ("vnmsubfp 17, 14, 15, 16"); +} + +static test_t tests_afa_ops_three[] = { + { &test_vmaddfp , " vmaddfp", }, + { &test_vnmsubfp , " vnmsubfp", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vaddfp (void) +{ + __asm__ __volatile__ ("vaddfp 17, 14, 15"); +} + +static void test_vsubfp (void) +{ + __asm__ __volatile__ ("vsubfp 17, 14, 15"); +} + +static void test_vmaxfp (void) +{ + __asm__ __volatile__ ("vmaxfp 17, 14, 15"); +} + +static void test_vminfp (void) +{ + __asm__ __volatile__ ("vminfp 17, 14, 15"); +} + +static test_t tests_afa_ops_two[] = { + { &test_vaddfp , " vaddfp", }, + { &test_vsubfp , " vsubfp", }, + { &test_vmaxfp , " vmaxfp", }, + { &test_vminfp , " vminfp", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vrfin (void) +{ + __asm__ __volatile__ ("vrfin 17, 14"); +} + +static void test_vrfiz (void) +{ + __asm__ __volatile__ ("vrfiz 17, 14"); +} + +static void test_vrfip (void) +{ + __asm__ __volatile__ ("vrfip 17, 14"); +} + +static void test_vrfim (void) +{ + __asm__ __volatile__ ("vrfim 17, 14"); +} + +static void test_vrefp (void) +{ + __asm__ __volatile__ ("vrefp 17, 14"); +} + +static void test_vrsqrtefp (void) +{ + __asm__ __volatile__ ("vrsqrtefp 17, 14"); +} + +static void test_vlogefp (void) +{ + __asm__ __volatile__ ("vlogefp 17, 14"); +} + +static void test_vexptefp (void) +{ + __asm__ __volatile__ ("vexptefp 17, 14"); +} + +static test_t tests_afa_ops_one[] = { + { &test_vrfin , " vrfin", }, + { &test_vrfiz , " vrfiz", }, + { &test_vrfip , " vrfip", }, + { &test_vrfim , " vrfim", }, + { &test_vrefp , " vrefp", }, + { &test_vrsqrtefp , " vrsqrtefp", }, + { &test_vlogefp , " vlogefp", }, + { &test_vexptefp , " vexptefp", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vcmpgtfp (void) +{ + __asm__ __volatile__ ("vcmpgtfp 17, 14, 15"); +} + +static void test_vcmpeqfp (void) +{ + __asm__ __volatile__ ("vcmpeqfp 17, 14, 15"); +} + +static void test_vcmpgefp (void) +{ + __asm__ __volatile__ ("vcmpgefp 17, 14, 15"); +} + +static void test_vcmpbfp (void) +{ + __asm__ __volatile__ ("vcmpbfp 17, 14, 15"); +} + +static test_t tests_afc_ops_two[] = { + { &test_vcmpgtfp , " vcmpgtfp", }, + { &test_vcmpeqfp , " vcmpeqfp", }, + { &test_vcmpgefp , " vcmpgefp", }, + { &test_vcmpbfp , " vcmpbfp", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (HAS_ALTIVEC) +static void test_vcmpgtfp_ (void) +{ + __asm__ __volatile__ ("vcmpgtfp. 17, 14, 15"); +} + +static void test_vcmpeqfp_ (void) +{ + __asm__ __volatile__ ("vcmpeqfp. 17, 14, 15"); +} + +static void test_vcmpgefp_ (void) +{ + __asm__ __volatile__ ("vcmpgefp. 17, 14, 15"); +} + +static void test_vcmpbfp_ (void) +{ + __asm__ __volatile__ ("vcmpbfp. 17, 14, 15"); +} + +static test_t tests_afcr_ops_two[] = { + { &test_vcmpgtfp_ , " vcmpgtfp.", }, + { &test_vcmpeqfp_ , " vcmpeqfp.", }, + { &test_vcmpgefp_ , " vcmpgefp.", }, + { &test_vcmpbfp_ , " vcmpbfp.", }, + { NULL, NULL, }, +}; +#endif /* defined (HAS_ALTIVEC) */ + +#if defined (IS_PPC405) +static void test_macchw (void) +{ + __asm__ __volatile__ ("macchw 17, 14, 15"); +} + +static void test_macchwo (void) +{ + __asm__ __volatile__ ("macchwo 17, 14, 15"); +} + +static void test_macchws (void) +{ + __asm__ __volatile__ ("macchws 17, 14, 15"); +} + +static void test_macchwso (void) +{ + __asm__ __volatile__ ("macchwso 17, 14, 15"); +} + +static void test_macchwsu (void) +{ + __asm__ __volatile__ ("macchwsu 17, 14, 15"); +} + +static void test_macchwsuo (void) +{ + __asm__ __volatile__ ("macchwsuo 17, 14, 15"); +} + +static void test_macchwu (void) +{ + __asm__ __volatile__ ("macchwu 17, 14, 15"); +} + +static void test_macchwuo (void) +{ + __asm__ __volatile__ ("macchwuo 17, 14, 15"); +} + +static void test_machhw (void) +{ + __asm__ __volatile__ ("machhw 17, 14, 15"); +} + +static void test_machhwo (void) +{ + __asm__ __volatile__ ("machhwo 17, 14, 15"); +} + +static void test_machhws (void) +{ + __asm__ __volatile__ ("machhws 17, 14, 15"); +} + +static void test_machhwso (void) +{ + __asm__ __volatile__ ("machhwso 17, 14, 15"); +} + +static void test_machhwsu (void) +{ + __asm__ __volatile__ ("machhwsu 17, 14, 15"); +} + +static void test_machhwsuo (void) +{ + __asm__ __volatile__ ("machhwsuo 17, 14, 15"); +} + +static void test_machhwu (void) +{ + __asm__ __volatile__ ("machhwu 17, 14, 15"); +} + +static void test_machhwuo (void) +{ + __asm__ __volatile__ ("machhwuo 17, 14, 15"); +} + +static void test_maclhw (void) +{ + __asm__ __volatile__ ("maclhw 17, 14, 15"); +} + +static void test_maclhwo (void) +{ + __asm__ __volatile__ ("maclhwo 17, 14, 15"); +} + +static void test_maclhws (void) +{ + __asm__ __volatile__ ("maclhws 17, 14, 15"); +} + +static void test_maclhwso (void) +{ + __asm__ __volatile__ ("maclhwso 17, 14, 15"); +} + +static void test_maclhwsu (void) +{ + __asm__ __volatile__ ("maclhwsu 17, 14, 15"); +} + +static void test_maclhwsuo (void) +{ + __asm__ __volatile__ ("maclhwsuo 17, 14, 15"); +} + +static void test_maclhwu (void) +{ + __asm__ __volatile__ ("maclhwu 17, 14, 15"); +} + +static void test_maclhwuo (void) +{ + __asm__ __volatile__ ("maclhwuo 17, 14, 15"); +} + +static void test_mulchw (void) +{ + __asm__ __volatile__ ("mulchw 17, 14, 15"); +} + +static void test_mulchwu (void) +{ + __asm__ __volatile__ ("mulchwu 17, 14, 15"); +} + +static void test_mulhhw (void) +{ + __asm__ __volatile__ ("mulhhw 17, 14, 15"); +} + +static void test_mulhhwu (void) +{ + __asm__ __volatile__ ("mulhhwu 17, 14, 15"); +} + +static void test_mullhw (void) +{ + __asm__ __volatile__ ("mullhw 17, 14, 15"); +} + +static void test_mullhwu (void) +{ + __asm__ __volatile__ ("mullhwu 17, 14, 15"); +} + +static void test_nmacchw (void) +{ + __asm__ __volatile__ ("nmacchw 17, 14, 15"); +} + +static void test_nmacchwo (void) +{ + __asm__ __volatile__ ("nmacchwo 17, 14, 15"); +} + +static void test_nmacchws (void) +{ + __asm__ __volatile__ ("nmacchws 17, 14, 15"); +} + +static void test_nmacchwso (void) +{ + __asm__ __volatile__ ("nmacchwso 17, 14, 15"); +} + +static void test_nmachhw (void) +{ + __asm__ __volatile__ ("nmachhw 17, 14, 15"); +} + +static void test_nmachhwo (void) +{ + __asm__ __volatile__ ("nmachhwo 17, 14, 15"); +} + +static void test_nmachhws (void) +{ + __asm__ __volatile__ ("nmachhws 17, 14, 15"); +} + +static void test_nmachhwso (void) +{ + __asm__ __volatile__ ("nmachhwso 17, 14, 15"); +} + +static void test_nmaclhw (void) +{ + __asm__ __volatile__ ("nmaclhw 17, 14, 15"); +} + +static void test_nmaclhwo (void) +{ + __asm__ __volatile__ ("nmaclhwo 17, 14, 15"); +} + +static void test_nmaclhws (void) +{ + __asm__ __volatile__ ("nmaclhws 17, 14, 15"); +} + +static void test_nmaclhwso (void) +{ + __asm__ __volatile__ ("nmaclhwso 17, 14, 15"); +} + +static test_t tests_p4m_ops_two[] = { + { &test_macchw , " macchw", }, + { &test_macchwo , " macchwo", }, + { &test_macchws , " macchws", }, + { &test_macchwso , " macchwso", }, + { &test_macchwsu , " macchwsu", }, + { &test_macchwsuo , " macchwsuo", }, + { &test_macchwu , " macchwu", }, + { &test_macchwuo , " macchwuo", }, + { &test_machhw , " machhw", }, + { &test_machhwo , " machhwo", }, + { &test_machhws , " machhws", }, + { &test_machhwso , " machhwso", }, + { &test_machhwsu , " machhwsu", }, + { &test_machhwsuo , " machhwsuo", }, + { &test_machhwu , " machhwu", }, + { &test_machhwuo , " machhwuo", }, + { &test_maclhw , " maclhw", }, + { &test_maclhwo , " maclhwo", }, + { &test_maclhws , " maclhws", }, + { &test_maclhwso , " maclhwso", }, + { &test_maclhwsu , " maclhwsu", }, + { &test_maclhwsuo , " maclhwsuo", }, + { &test_maclhwu , " maclhwu", }, + { &test_maclhwuo , " maclhwuo", }, + { &test_mulchw , " mulchw", }, + { &test_mulchwu , " mulchwu", }, + { &test_mulhhw , " mulhhw", }, + { &test_mulhhwu , " mulhhwu", }, + { &test_mullhw , " mullhw", }, + { &test_mullhwu , " mullhwu", }, + { &test_nmacchw , " nmacchw", }, + { &test_nmacchwo , " nmacchwo", }, + { &test_nmacchws , " nmacchws", }, + { &test_nmacchwso , " nmacchwso", }, + { &test_nmachhw , " nmachhw", }, + { &test_nmachhwo , " nmachhwo", }, + { &test_nmachhws , " nmachhws", }, + { &test_nmachhwso , " nmachhwso", }, + { &test_nmaclhw , " nmaclhw", }, + { &test_nmaclhwo , " nmaclhwo", }, + { &test_nmaclhws , " nmaclhws", }, + { &test_nmaclhwso , " nmaclhwso", }, + { NULL, NULL, }, +}; +#endif /* defined (IS_PPC405) */ + +#if defined (IS_PPC405) +static void test_macchw_ (void) +{ + __asm__ __volatile__ ("macchw. 17, 14, 15"); +} + +static void test_macchwo_ (void) +{ + __asm__ __volatile__ ("macchwo. 17, 14, 15"); +} + +static void test_macchws_ (void) +{ + __asm__ __volatile__ ("macchws. 17, 14, 15"); +} + +static void test_macchwso_ (void) +{ + __asm__ __volatile__ ("macchwso. 17, 14, 15"); +} + +static void test_macchwsu_ (void) +{ + __asm__ __volatile__ ("macchwsu. 17, 14, 15"); +} + +static void test_macchwsuo_ (void) +{ + __asm__ __volatile__ ("macchwsuo. 17, 14, 15"); +} + +static void test_macchwu_ (void) +{ + __asm__ __volatile__ ("macchwu. 17, 14, 15"); +} + +static void test_macchwuo_ (void) +{ + __asm__ __volatile__ ("macchwuo. 17, 14, 15"); +} + +static void test_machhw_ (void) +{ + __asm__ __volatile__ ("machhw. 17, 14, 15"); +} + +static void test_machhwo_ (void) +{ + __asm__ __volatile__ ("machhwo. 17, 14, 15"); +} + +static void test_machhws_ (void) +{ + __asm__ __volatile__ ("machhws. 17, 14, 15"); +} + +static void test_machhwso_ (void) +{ + __asm__ __volatile__ ("machhwso. 17, 14, 15"); +} + +static void test_machhwsu_ (void) +{ + __asm__ __volatile__ ("machhwsu. 17, 14, 15"); +} + +static void test_machhwsuo_ (void) +{ + __asm__ __volatile__ ("machhwsuo. 17, 14, 15"); +} + +static void test_machhwu_ (void) +{ + __asm__ __volatile__ ("machhwu. 17, 14, 15"); +} + +static void test_machhwuo_ (void) +{ + __asm__ __volatile__ ("machhwuo. 17, 14, 15"); +} + +static void test_maclhw_ (void) +{ + __asm__ __volatile__ ("maclhw. 17, 14, 15"); +} + +static void test_maclhwo_ (void) +{ + __asm__ __volatile__ ("maclhwo. 17, 14, 15"); +} + +static void test_maclhws_ (void) +{ + __asm__ __volatile__ ("maclhws. 17, 14, 15"); +} + +static void test_maclhwso_ (void) +{ + __asm__ __volatile__ ("maclhwso. 17, 14, 15"); +} + +static void test_maclhwsu_ (void) +{ + __asm__ __volatile__ ("maclhwsu. 17, 14, 15"); +} + +static void test_maclhwsuo_ (void) +{ + __asm__ __volatile__ ("maclhwsuo. 17, 14, 15"); +} + +static void test_maclhwu_ (void) +{ + __asm__ __volatile__ ("maclhwu. 17, 14, 15"); +} + +static void test_maclhwuo_ (void) +{ + __asm__ __volatile__ ("maclhwuo. 17, 14, 15"); +} + +static void test_mulchw_ (void) +{ + __asm__ __volatile__ ("mulchw. 17, 14, 15"); +} + +static void test_mulchwu_ (void) +{ + __asm__ __volatile__ ("mulchwu. 17, 14, 15"); +} + +static void test_mulhhw_ (void) +{ + __asm__ __volatile__ ("mulhhw. 17, 14, 15"); +} + +static void test_mulhhwu_ (void) +{ + __asm__ __volatile__ ("mulhhwu. 17, 14, 15"); +} + +static void test_mullhw_ (void) +{ + __asm__ __volatile__ ("mullhw. 17, 14, 15"); +} + +static void test_mullhwu_ (void) +{ + __asm__ __volatile__ ("mullhwu. 17, 14, 15"); +} + +static void test_nmacchw_ (void) +{ + __asm__ __volatile__ ("nmacchw. 17, 14, 15"); +} + +static void test_nmacchwo_ (void) +{ + __asm__ __volatile__ ("nmacchwo. 17, 14, 15"); +} + +static void test_nmacchws_ (void) +{ + __asm__ __volatile__ ("nmacchws. 17, 14, 15"); +} + +static void test_nmacchwso_ (void) +{ + __asm__ __volatile__ ("nmacchwso. 17, 14, 15"); +} + +static void test_nmachhw_ (void) +{ + __asm__ __volatile__ ("nmachhw. 17, 14, 15"); +} + +static void test_nmachhwo_ (void) +{ + __asm__ __volatile__ ("nmachhwo. 17, 14, 15"); +} + +static void test_nmachhws_ (void) +{ + __asm__ __volatile__ ("nmachhws. 17, 14, 15"); +} + +static void test_nmachhwso_ (void) +{ + __asm__ __volatile__ ("nmachhwso. 17, 14, 15"); +} + +static void test_nmaclhw_ (void) +{ + __asm__ __volatile__ ("nmaclhw. 17, 14, 15"); +} + +static void test_nmaclhwo_ (void) +{ + __asm__ __volatile__ ("nmaclhwo. 17, 14, 15"); +} + +static void test_nmaclhws_ (void) +{ + __asm__ __volatile__ ("nmaclhws. 17, 14, 15"); +} + +static void test_nmaclhwso_ (void) +{ + __asm__ __volatile__ ("nmaclhwso. 17, 14, 15"); +} + +static test_t tests_p4mc_ops_two[] = { + { &test_macchw_ , " macchw.", }, + { &test_macchwo_ , " macchwo.", }, + { &test_macchws_ , " macchws.", }, + { &test_macchwso_ , " macchwso.", }, + { &test_macchwsu_ , " macchwsu.", }, + { &test_macchwsuo_ , " macchwsuo.", }, + { &test_macchwu_ , " macchwu.", }, + { &test_macchwuo_ , " macchwuo.", }, + { &test_machhw_ , " machhw.", }, + { &test_machhwo_ , " machhwo.", }, + { &test_machhws_ , " machhws.", }, + { &test_machhwso_ , " machhwso.", }, + { &test_machhwsu_ , " machhwsu.", }, + { &test_machhwsuo_ , " machhwsuo.", }, + { &test_machhwu_ , " machhwu.", }, + { &test_machhwuo_ , " machhwuo.", }, + { &test_maclhw_ , " maclhw.", }, + { &test_maclhwo_ , " maclhwo.", }, + { &test_maclhws_ , " maclhws.", }, + { &test_maclhwso_ , " maclhwso.", }, + { &test_maclhwsu_ , " maclhwsu.", }, + { &test_maclhwsuo_ , " maclhwsuo.", }, + { &test_maclhwu_ , " maclhwu.", }, + { &test_maclhwuo_ , " maclhwuo.", }, + { &test_mulchw_ , " mulchw.", }, + { &test_mulchwu_ , " mulchwu.", }, + { &test_mulhhw_ , " mulhhw.", }, + { &test_mulhhwu_ , " mulhhwu.", }, + { &test_mullhw_ , " mullhw.", }, + { &test_mullhwu_ , " mullhwu.", }, + { &test_nmacchw_ , " nmacchw.", }, + { &test_nmacchwo_ , " nmacchwo.", }, + { &test_nmacchws_ , " nmacchws.", }, + { &test_nmacchwso_ , " nmacchwso.", }, + { &test_nmachhw_ , " nmachhw.", }, + { &test_nmachhwo_ , " nmachhwo.", }, + { &test_nmachhws_ , " nmachhws.", }, + { &test_nmachhwso_ , " nmachhwso.", }, + { &test_nmaclhw_ , " nmaclhw.", }, + { &test_nmaclhwo_ , " nmaclhwo.", }, + { &test_nmaclhws_ , " nmaclhws.", }, + { &test_nmaclhwso_ , " nmaclhwso.", }, + { NULL, NULL, }, +}; +#endif /* defined (IS_PPC405) */ + +static test_table_t all_tests[] = { + { + tests_ia_ops_two , + "PPC integer arith insns with two args", + 0x00010102, + }, + { + tests_iar_ops_two , + "PPC integer arith insns with two args with flags update", + 0x01010102, + }, + { + tests_iac_ops_two , + "PPC integer arith insns with two args and carry", + 0x02010102, + }, + { + tests_iacr_ops_two , + "PPC integer arith insns with two args and carry with flags update", + 0x03010102, + }, + { + tests_il_ops_two , + "PPC integer logical insns with two args", + 0x00010202, + }, + { + tests_ilr_ops_two , + "PPC integer logical insns with two args with flags update", + 0x01010202, + }, + { + tests_icr_ops_two , + "PPC integer compare insns (two args)", + 0x01010304, + }, + { + tests_icr_ops_two_i16 , + "PPC integer compare with immediate insns (two args)", + 0x01010305, + }, + { + tests_ia_ops_two_i16 , + "PPC integer arith insns\n with one register + one 16 bits immediate args", + 0x00010106, + }, + { + tests_iar_ops_two_i16 , + "PPC integer arith insns\n with one register + one 16 bits immediate args with flags update", + 0x01010106, + }, + { + tests_il_ops_two_i16 , + "PPC integer logical insns\n with one register + one 16 bits immediate args", + 0x00010206, + }, + { + tests_ilr_ops_two_i16 , + "PPC integer logical insns\n with one register + one 16 bits immediate args with flags update", + 0x01010206, + }, + { + tests_crl_ops_two , + "PPC condition register logical insns - two operands", + 0x01010202, + }, + { + tests_iac_ops_one , + "PPC integer arith insns with one arg and carry", + 0x02010101, + }, + { + tests_iacr_ops_one , + "PPC integer arith insns with one arg and carry with flags update", + 0x03010101, + }, + { + tests_il_ops_one , + "PPC integer logical insns with one arg", + 0x00010201, + }, + { + tests_ilr_ops_one , + "PPC integer logical insns with one arg with flags update", + 0x01010201, + }, + { + tests_il_ops_spe , + "PPC logical insns with special forms", + 0x00010207, + }, + { + tests_ilr_ops_spe , + "PPC logical insns with special forms with flags update", + 0x01010207, + }, + { + tests_ild_ops_two_i16 , + "PPC integer load insns\n with one register + one 16 bits immediate args with flags update", + 0x00010508, + }, + { + tests_ild_ops_two , + "PPC integer load insns with two register args", + 0x00010509, + }, + { + tests_ist_ops_three_i16, + "PPC integer store insns\n with one register + one 16 bits immediate args with flags update", + 0x0001050a, + }, + { + tests_ist_ops_three , + "PPC integer store insns with three register args", + 0x0001050b, + }, +#if !defined (NO_FLOAT) + { + tests_fa_ops_three , + "PPC floating point arith insns with three args", + 0x00020103, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_far_ops_three , + "PPC floating point arith insns\n with three args with flags update", + 0x01020103, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_fa_ops_two , + "PPC floating point arith insns with two args", + 0x00020102, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_far_ops_two , + "PPC floating point arith insns\n with two args with flags update", + 0x01020102, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_fcr_ops_two , + "PPC floating point compare insns (two args)", + 0x01020304, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_fa_ops_one , + "PPC floating point arith insns with one arg", + 0x00020101, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_far_ops_one , + "PPC floating point arith insns\n with one arg with flags update", + 0x01020101, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_fl_ops_spe , + "PPC floating point status register manipulation insns", + 0x00020207, + }, +#endif /* !defined (NO_FLOAT) */ +#if !defined (NO_FLOAT) + { + tests_flr_ops_spe , + "PPC floating point status register manipulation insns\n with flags update", + 0x01020207, + }, +#endif /* !defined (NO_FLOAT) */ +#if defined (HAS_ALTIVEC) + { + tests_aa_ops_three , + "PPC altivec integer arith insns with three args", + 0x00040103, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_al_ops_three , + "PPC altivec integer logical insns with three args", + 0x00040203, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_aa_ops_two , + "PPC altivec integer arith insns with two args", + 0x00040102, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_al_ops_two , + "PPC altivec integer logical insns with two args", + 0x00040202, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_al_ops_one , + "PPC altivec integer logical insns with one arg", + 0x00040201, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_ac_ops_two , + "Altivec integer compare insns", + 0x00040302, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_acr_ops_two , + "Altivec integer compare insns with flags update", + 0x01040302, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_av_int_ops_spe , + "Altivec integer special insns", + 0x00040207, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_afa_ops_three , + "Altivec floating point arith insns with three args", + 0x00050103, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_afa_ops_two , + "Altivec floating point arith insns with two args", + 0x00050102, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_afa_ops_one , + "Altivec floating point arith insns with one arg", + 0x00050101, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_afc_ops_two , + "Altivec floating point compare insns", + 0x00050302, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (HAS_ALTIVEC) + { + tests_afcr_ops_two , + "Altivec floating point compare insns with flags update", + 0x01050302, + }, +#endif /* defined (HAS_ALTIVEC) */ +#if defined (IS_PPC405) + { + tests_p4m_ops_two , + "PPC 405 mac insns with three args", + 0x00030102, + }, +#endif /* defined (IS_PPC405) */ +#if defined (IS_PPC405) + { + tests_p4mc_ops_two , + "PPC 405 mac insns with three args with flags update", + 0x01030102, + }, +#endif /* defined (IS_PPC405) */ + { NULL, NULL, 0x00000000, }, +}; + +/* -------------- END #include "ops-ppc.c" -------------- */ + +static int verbose = 0; +static int arg_list_size = 0; + +static double *fargs; +static int nb_fargs; +static uint32_t *iargs; +static int nb_iargs; +static uint16_t *ii16; +static int nb_ii16; +#if defined (HAS_ALTIVEC) +static vector unsigned int* viargs; +static int nb_viargs; +static vector float* vfargs; +static int nb_vfargs; + +//#define TEST_VSCR_SAT +#endif + +static inline void register_farg (void *farg, + int s, uint16_t exp, uint64_t mant) +{ + uint64_t tmp; + + tmp = ((uint64_t)s << 63) | ((uint64_t)exp << 52) | mant; + *(uint64_t *)farg = tmp; + AB_DPRINTF("%d %03x %013llx => %016llx %0e\n", + s, exp, mant, *(uint64_t *)farg, *(double *)farg); +} + +static void build_fargs_table (void) +{ + /* Sign goes from zero to one + * Exponent goes from 0 to ((1 << 12) - 1) + * Mantissa goes from 1 to ((1 << 52) - 1) + * + special values: + * +0.0 : 0 0x000 0x0000000000000 + * -0.0 : 1 0x000 0x0000000000000 + * +infinity : 0 0x7FF 0x0000000000000 + * -infinity : 1 0x7FF 0x0000000000000 + * +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF + * -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF + * +QNaN : 0 0x7FF 0x8000000000000 + * -QNaN : 1 0x7FF 0x8000000000000 + * (8 values) + */ + uint64_t mant; + uint16_t exp, e0, e1; + int s; + int i=0; + + if ( arg_list_size == 1 ) { // Large + fargs = malloc(200 * sizeof(double)); + for (s=0; s<2; s++) { + for (e0=0; e0<2; e0++) { + for (e1=0x000; ; e1 = ((e1 + 1) << 2) + 6) { + if (e1 >= 0x400) + e1 = 0x3fe; + exp = (e0 << 10) | e1; + for (mant = 0x0000000000001ULL; mant < (1ULL << 52); + /* Add 'random' bits */ + mant = ((mant + 0x4A6) << 13) + 0x359) { + register_farg(&fargs[i++], s, exp, mant); + } + if (e1 == 0x3fe) + break; + } + } + } + } else { // Default + fargs = malloc(16 * sizeof(double)); + for (s=0; s<2; s++) { // x2 +// for (e0=0; e0<2; e0++) { + for (e1=0x001; ; e1 = ((e1 + 1) << 13) + 7) { // x2 +// for (e1=0x000; ; e1 = ((e1 + 1) << 5) + 7) { // x3 + if (e1 >= 0x400) + e1 = 0x3fe; +// exp = (e0 << 10) | e1; + exp = e1; + for (mant = 0x0000000000001ULL; mant < (1ULL << 52); + /* Add 'random' bits */ + mant = ((mant + 0x4A6) << 29) + 0x359) { // x2 + register_farg(&fargs[i++], s, exp, mant); + } + if (e1 == 0x3fe) + break; + } +// } + } + } + + /* Special values */ + /* +0.0 : 0 0x000 0x0000000000000 */ + s = 0; + exp = 0x000; + mant = 0x0000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + /* -0.0 : 1 0x000 0x0000000000000 */ + s = 1; + exp = 0x000; + mant = 0x0000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + /* +infinity : 0 0x7FF 0x0000000000000 */ + s = 0; + exp = 0x7FF; + mant = 0x0000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + /* -infinity : 1 0x7FF 0x0000000000000 */ + s = 1; + exp = 0x7FF; + mant = 0x0000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + /* +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF */ + s = 0; + exp = 0x7FF; + mant = 0x7FFFFFFFFFFFFULL; + register_farg(&fargs[i++], s, exp, mant); + /* -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF */ + s = 1; + exp = 0x7FF; + mant = 0x7FFFFFFFFFFFFULL; + register_farg(&fargs[i++], s, exp, mant); + /* +QNaN : 0 0x7FF 0x8000000000000 */ + s = 0; + exp = 0x7FF; + mant = 0x8000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + /* -QNaN : 1 0x7FF 0x8000000000000 */ + s = 1; + exp = 0x7FF; + mant = 0x8000000000000ULL; + register_farg(&fargs[i++], s, exp, mant); + AB_DPRINTF("Registered %d fargs values\n", i); + nb_fargs = i; +} + +static void build_iargs_table (void) +{ + uint64_t tmp; + int i=0; + + if (arg_list_size == 1) { // Large + iargs = malloc(400 * sizeof(uint32_t)); + for (tmp=0; ; tmp = tmp + 1 + (tmp >> 1)) { + if (tmp >= 0x100000000ULL) + tmp = 0xFFFFFFFF; + iargs[i++] = tmp; + AB_DPRINTF("val %08llx\n", tmp); + if (tmp == 0xFFFFFFFF) + break; + } + } else { // Default + iargs = malloc(10 * sizeof(uint32_t)); + // for (tmp = 0; ; tmp = 71*tmp + 1 + (tmp>>1)) { // gives 8 + // for (tmp = 0; ; tmp = 100000*tmp + 1 + (tmp>>1)) { // gives 4 + for (tmp=0; ; tmp = 999999*tmp + 999999) { // gives 3 + if (tmp >= 0x100000000ULL) + tmp = 0xFFFFFFFF; + iargs[i++] = tmp; + AB_DPRINTF("val %08llx\n", tmp); + if (tmp == 0xFFFFFFFF) + break; + } + } + AB_DPRINTF("Registered %d iargs values\n", i); + nb_iargs = i; +} + +static void build_ii16_table (void) +{ + uint32_t tmp; + int i=0; + + if (arg_list_size == 1) { // Large + ii16 = malloc(200 * sizeof(uint32_t)); + for (tmp=0; ; tmp = tmp + 1 + (tmp >> 2)) { + if (tmp >= 0x10000) + tmp = 0xFFFF; + ii16[i++] = tmp; + AB_DPRINTF("val %08x\n", tmp); + if (tmp == 0xFFFF) + break; + } + } else { // Default + ii16 = malloc(10 * sizeof(uint32_t)); + for (tmp=0; ; tmp = 999*tmp + 999) { // gives 3 + if (tmp >= 0x10000) + tmp = 0xFFFF; + ii16[i++] = tmp; + AB_DPRINTF("val %08x\n", tmp); + if (tmp == 0xFFFF) + break; + } + } + AB_DPRINTF("Registered %d ii16 values\n", i); + nb_ii16 = i; +} + +#if defined (HAS_ALTIVEC) +static void build_viargs_table (void) +{ + unsigned int i=0; + +#if !defined (ALTIVEC_ARGS_LARGE) + i=2; + viargs = memalign(16, i * sizeof(vector unsigned int)); + viargs[0] = (vector unsigned int) { 0x01020304,0x05060708,0x090A0B0C,0x0E0D0E0F }; + viargs[1] = (vector unsigned int) { 0xF1F2F3F4,0xF5F6F7F8,0xF9FAFBFC,0xFEFDFEFF }; +#else + // build from iargs table (large/default already set) + viargs = malloc(nb_iargs * sizeof(vector unsigned int)); + for (i=0; i %08x %0e\n", + s, exp, mant, *((uint32_t*)&tmp), f); +} + +static void build_vfargs_table (void) +{ + /* Sign goes from zero to one + * Exponent goes from 0 to ((1 << 9) - 1) + * Mantissa goes from 1 to ((1 << 24) - 1) + * + special values: + * +0.0 : 0 0x00 0x00000000 + * -0.0 : 1 0x00 0x00000000 + * +infinity : 0 0xFF 0x00000000 + * -infinity : 1 0xFF 0x00000000 + * +SNaN : 0 0xFF 0x7FFFFFFF + * -SNaN : 1 0xFF 0x7FFFFFFF + * +QNaN : 0 0xFF 0x80000000 + * -QNaN : 1 0xFF 0x80000000 + * (8 values) + */ + uint32_t mant; + uint8_t exp; + int s; + int i=0; + + nb_vfargs = 8; + + vfargs = memalign(16, nb_vfargs * sizeof(vector float)); + + /* Special values */ + /* +0.0 : 0 0x00 0x000000 */ + s = 0; + exp = 0x00; + mant = 0x000000; + register_vfarg(&vfargs[i++], s, exp, mant); + /* -0.0 : 1 0x00 0x000000 */ + s = 1; + exp = 0x00; + mant = 0x000000; + register_vfarg(&vfargs[i++], s, exp, mant); + + /* +infinity : 0 0xFF 0x000000 */ + s = 0; + exp = 0xFF; + mant = 0x000000; + register_vfarg(&vfargs[i++], s, exp, mant); + /* -infinity : 1 0xFF 0x000000 */ + s = 1; + exp = 0xFF; + mant = 0x000000; + register_vfarg(&vfargs[i++], s, exp, mant); + + /* NaN: exponent all 1s, non-zero fraction */ + /* SNaN is a NaN with the most significant fraction bit clear.*/ + /* +SNaN : 0 0xFF 0x3FFFFF */ + s = 0; + exp = 0xFF; + mant = 0x3FFFFF; + register_vfarg(&vfargs[i++], s, exp, mant); + /* -SNaN : 1 0xFF 0x3FFFFF */ + s = 1; + exp = 0xFF; + mant = 0x3FFFFF; + register_vfarg(&vfargs[i++], s, exp, mant); + + /* QNaN is a NaN with the most significant fraction bit set */ + /* +QNaN : 0 0xFF 0x400000 */ + s = 0; + exp = 0xFF; + mant = 0x400000; + register_vfarg(&vfargs[i++], s, exp, mant); + /* -QNaN : 1 0xFF 0x400000 */ + s = 1; + exp = 0xFF; + mant = 0x400000; + register_vfarg(&vfargs[i++], s, exp, mant); + AB_DPRINTF("Registered %d vfargs values\n", i); + + assert(i == nb_vfargs); +} +#endif + +#if 0 +static void dump_iargs (void) +{ + int i; + for (i = 0; i < nb_iargs; i++) { + printf("iarg %d: %08x %08x %08x\n", i, iargs[i], + (unsigned int)&iargs[i], (unsigned int)iargs); + } +} + +static void dump_iargs16 (void) +{ + int i; + for (i = 0; i < nb_ii16; i++) { + printf("iarg16 %d: %08x %08x %08x\n", i, ii16[i], + (unsigned int)&ii16[i], (unsigned int)ii16); + } +} + +static void dump_vfargs (void) +{ + int i=0; + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], iargs[j], iargs[k], res, flags, xer); + } + if (verbose) printf("\n"); + } + } +} + +static void test_int_two_args (const unsigned char *name, test_func_t func, + uint32_t test_flags) +{ + volatile uint32_t res, flags, xer, xer_orig, tmpcr, tmpxer; + int i, j; + + xer_orig = 0x00000000; + redo: + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], iargs[j], res, flags, xer); + } + if (verbose) printf("\n"); + } + if (test_flags & PPC_XER_CA && xer_orig == 0x00000000) { + xer_orig = 0x20000000; + goto redo; + } +} + +static void test_int_one_arg (const unsigned char *name, test_func_t func, + uint32_t test_flags) +{ + volatile uint32_t res, flags, xer, xer_orig, tmpcr, tmpxer; + int i; + + xer_orig = 0x00000000; + redo: + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], res, flags, xer); + } + if (test_flags & PPC_XER_CA && xer_orig == 0x00000000) { + xer_orig = 0x20000000; + goto redo; + } +} + +static inline void invalidate_icache ( void *ptr, int nbytes ) +{ + unsigned int startaddr = (unsigned int) ptr; + unsigned int endaddr = startaddr + nbytes; + unsigned int cls = 32; /*VG_(cache_line_size_ppc32);*/ + unsigned int addr; + + startaddr &= ~(cls - 1); + for (addr = startaddr; addr < endaddr; addr += cls) + asm volatile("dcbst 0,%0" : : "r" (addr)); + asm volatile("sync"); + for (addr = startaddr; addr < endaddr; addr += cls) + asm volatile("icbi 0,%0" : : "r" (addr)); + asm volatile("sync; isync"); +} + +/* for god knows what reason, if this isn't inlined, the + program segfaults. */ +static inline void _patch_op_imm (void *out, void *in, + uint16_t imm, int sh, int len) +{ + volatile uint32_t *p, *q; + + p = out; + q = in; + *p = (*q & ~(((1 << len) - 1) << sh)) | ((imm & ((1 << len) - 1)) << sh); +} + +static inline void patch_op_imm (void *out, void *in, + uint16_t imm, int sh, int len) +{ + volatile uint32_t *p; + + p = out; + _patch_op_imm(out, in, imm, sh, len); + invalidate_icache(out, 4); +} + +static inline void patch_op_imm16 (void *out, void *in, uint16_t imm) +{ + patch_op_imm(out, in, imm, 0, 16); +} + +static void test_int_one_reg_imm16 (const unsigned char *name, + test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j; + + for (i=0; i func %s from %p to %p (%08x %08x)\n", + name, func, func_buf, func_buf[0], func_buf[1]); +#endif + r14 = iargs[i]; + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 18"); + (*func)(); + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + res = r17; + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + printf("%s %08x, %08x => %08x (%08x %08x)\n", + name, iargs[i], ii16[j], res, flags, xer); + } + if (verbose) printf("\n"); + } +} + +/* Special test cases for: + * rlwimi + * rlwinm + * rlwnm + * srawi + * mcrf + * mcrfs + * mcrxr_cb + * mfcr_cb + * mfspr_cb + * mftb_cb + * mtcrf_cb + * mtspr_cb + */ + +static void rlwi_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j, k, l; + + int arg_step = (arg_list_size == 0) ? 31 : 3; + + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], j, k, l, res, flags, xer); + } + if (verbose) printf("\n"); + } + } + } +} + +static void rlwnm_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j, k, l; + + int arg_step = (arg_list_size == 0) ? 31 : 3; + + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], iargs[j], k, l, res, flags, xer); + } + if (verbose) printf("\n"); + } + } + } +} + +static void srawi_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j; + + int arg_step = (arg_list_size == 0) ? 31 : 1; + + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], j, res, flags, xer); + } + if (verbose) printf("\n"); + } +} + +static void mcrf_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t flags, xer, tmpcr, tmpxer; + int i, j, k; + + int arg_step = (arg_list_size == 0) ? 7 : 1; + + for (i=0; i (%08x %08x)\n", + name, j, k, iargs[i], flags, xer); + } + if (verbose) printf("\n"); + } + } +} + +#if 0 +static void mcrfs_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{} +#endif + + +static void mcrxr_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t flags, xer, tmpcr, tmpxer; + int i, j, k; + + int arg_step = 1; //(arg_list_size == 0) ? 7 : 1; + + for (i=0; i<16; i+=arg_step) { + j = i << 28; + for (k=0; k<8; k+=arg_step) { + p = (void *)func; + func_buf[1] = p[1]; + patch_op_imm(func_buf, p, k, 23, 3); + func = (void *)func_buf; + r14 = j; + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 14"); + (*func)(); + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + printf("%s %d (%08x) => (%08x %08x)\n", + name, k, j, flags, xer); + } + if (verbose) printf("\n"); + } +} + +static void mfcr_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i; + + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], res, flags, xer); + } +} + +// NOTE: Not using func: calling function kills lr +static void mfspr_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t res, flags, xer, ctr, lr, tmpcr, tmpxer; + int j, k; + + // Call func, just to stop compiler complaining + (*func)(); + + // mfxer + j = 1; + for (k=0; k %08x (%08x %08x, %08x, %08x)\n", + name, j, iargs[k], res, flags, xer, lr, ctr); + } + if (verbose) printf("\n"); + + // mflr + j = 8; + for (k=0; k %08x (%08x %08x, %08x, %08x)\n", + name, j, iargs[k], res, flags, xer, lr, ctr); + } + if (verbose) printf("\n"); + + // mfctr + j = 9; + for (k=0; k %08x (%08x %08x, %08x, %08x)\n", + name, 9, iargs[k], res, flags, xer, lr, ctr); + } +} + +#if 0 +static void mftb_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ +// How to test this? +// 1) TBU won't change for a while +// 2) TBL will have changed every loop iter + + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j; + + i = 269; + for (j=0; j<16; j++) { + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 18"); + + __asm__ __volatile__ ("mftb 17, 269"); // func + + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + res = r17; + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + printf("%s %d => %08x (%08x %08x)\n", + name, i, res, flags, xer); + } + if (verbose) printf("\n"); + + i = 268; + for (j=0; j<16; j++) { + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 18"); + + __asm__ __volatile__ ("mftb 17, 268"); // func + + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + res = r17; + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + printf("%s %d => %08x (%08x %08x)\n", + name, i, res, flags, xer); + } +} +#endif + +static void mtcrf_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t flags, xer, tmpcr, tmpxer; + int i, j; + + int arg_step = (arg_list_size == 0) ? 99 : 1; + + for (i=0; i (%08x %08x)\n", + name, j, iargs[i], flags, xer); + } + if (verbose) printf("\n"); + } +} + +// NOTE: Not using func: calling function kills lr +static void mtspr_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, xer, ctr, lr, tmpcr, tmpxer; + int j, k; + + // Call func, just to stop compiler complaining + (*func)(); + + // mtxer + j = 1; + for (k=0; k (%08x %08x, %08x, %08x)\n", + name, j, iargs[k], flags, xer, lr, ctr); + } + if (verbose) printf("\n"); + + // mtlr + j = 8; + for (k=0; k (%08x %08x, %08x, %08x)\n", + name, j, iargs[k], flags, xer, lr, ctr); + } + if (verbose) printf("\n"); + + // mtctr + j = 9; + for (k=0; k (%08x %08x, %08x, %08x)\n", + name, j, iargs[k], flags, xer, lr, ctr); + } +} + + + +typedef struct special_t special_t; + +struct special_t { + const unsigned char *name; + void (*test_cb)(const unsigned char *name, test_func_t func, + unused uint32_t test_flags); +}; + +static void test_special (special_t *table, + const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + const unsigned char *tmp; + int i; + + for (tmp = name; isspace(*tmp); tmp++) + continue; + for (i=0; table[i].name != NULL; i++) { +#if 0 + fprintf(stderr, "look for handler for '%s' (%s)\n", name, + table[i].name); +#endif + if (strcmp(table[i].name, tmp) == 0) { + (*table[i].test_cb)(name, func, test_flags); + return; + } + } + fprintf(stderr, "ERROR: no test found for op '%s'\n", name); +} + +static special_t special_int_ops[] = { + { + "rlwimi", /* One register + 3 5 bits immediate arguments */ + &rlwi_cb, + }, + { + "rlwimi.", /* One register + 3 5 bits immediate arguments */ + &rlwi_cb, + }, + { + "rlwinm", /* One register + 3 5 bits immediate arguments */ + &rlwi_cb, + }, + { + "rlwinm.", /* One register + 3 5 bits immediate arguments */ + &rlwi_cb, + }, + { + "rlwnm", /* Two registers + 2 5 bits immediate arguments */ + &rlwnm_cb, + }, + { + "rlwnm.", /* Two registers + 2 5 bits immediate arguments */ + &rlwnm_cb, + }, + { + "srawi", /* One register + 1 5 bits immediate arguments */ + &srawi_cb, + }, + { + "srawi.", /* One register + 1 5 bits immediate arguments */ + &srawi_cb, + }, + { + "mcrf", /* 2 3 bits immediate arguments */ + &mcrf_cb, + }, +#if 0 + { + "mcrfs", /* 2 3 bits immediate arguments */ + &mcrfs_cb, + }, +#endif + { + "mcrxr", /* 1 3 bits immediate argument */ + &mcrxr_cb, + }, + { + "mfcr", /* No arguments */ + &mfcr_cb, + }, + { + "mfspr", /* 1 10 bits immediate argument */ + &mfspr_cb, + }, +#if 0 + { // Move from time base + "mftb", /* 1 10 bits immediate arguments */ + &mftb_cb, + }, +#endif + { + "mtcrf", /* One register + 1 8 bits immediate arguments */ + &mtcrf_cb, + }, + { + "mtspr", /* One register + 1 10 bits immediate arguments */ + &mtspr_cb, + }, + { + NULL, + NULL, + }, +}; + +static void test_int_special (const unsigned char *name, test_func_t func, + uint32_t test_flags) +{ + test_special(special_int_ops, name, func, test_flags); +} + + +static void test_int_ld_one_reg_imm16 (const unsigned char *name, + test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t res, rA, flags, xer, tmpcr, tmpxer; + int i, j; + + // +ve d + for (i=0; i %08x, (%08x %08x)\n", + name, j, /*&iargs[0], */ iargs[i], res, /*rA, */ flags, xer); + } + if (verbose) printf("\n"); + + // -ve d + for (i = -nb_iargs+1; i<=0; i++) { + j = i * 4; // sizeof(uint32_t) + p = (void *)func; + func_buf[1] = p[1]; + patch_op_imm16(func_buf, p, j); + func = (void *)func_buf; + r14 = (uint32_t)&iargs[nb_iargs-1]; + + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 18"); + (*func)(); + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + res = r17; + rA = r14; + + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + + printf("%s %d, (%08x) => %08x (%08x %08x)\n", + name, j, /*&iargs[nb_iargs-1], */ iargs[nb_iargs-1+i], res, /*rA, */ flags, xer); + } +} + +static void test_int_ld_two_regs (const unsigned char *name, + test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t res, rA, flags, xer, tmpcr, tmpxer; + int i, j; + + // +ve d + for (i=0; i %08x (%08x %08x)\n", + name, /*&iargs[0], */ j, iargs[i], res, /*rA, */ flags, xer); + } +} + +static void test_int_st_two_regs_imm16 (const unsigned char *name, + test_func_t func, + unused uint32_t test_flags) +{ + uint32_t func_buf[2], *p; + volatile uint32_t rA, flags, xer, tmpcr, tmpxer; + int i, j; + uint32_t *iargs_priv; + + // private iargs table to store to + iargs_priv = malloc(nb_iargs * sizeof(uint32_t)); + for (i=0; i %08x, (%08x %08x)\n", + name, iargs[i], j, /*&iargs_priv[0], */ iargs_priv[i], /*rA, */ flags, xer); + } + if (verbose) printf("\n"); + + // -ve d + for (i = -nb_iargs+1; i<=0; i++) { + j = i * 4; // sizeof(uint32_t) + p = (void *)func; + func_buf[1] = p[1]; + patch_op_imm16(func_buf, p, j); + func = (void *)func_buf; + r14 = iargs[nb_iargs-1+i]; // read from iargs + r15 = (uint32_t)&iargs_priv[nb_iargs-1]; // store to r15 + j + + /* Save flags */ + __asm__ __volatile__ ("mfcr 18"); + tmpcr = r18; + __asm__ __volatile__ ("mfxer 18"); + tmpxer = r18; + + /* Set up flags for test */ + r18 = 0; + __asm__ __volatile__ ("mtcr 18"); + __asm__ __volatile__ ("mtxer 18"); + (*func)(); + __asm__ __volatile__ ("mfcr 18"); + flags = r18; + __asm__ __volatile__ ("mfxer 18"); + xer = r18; + rA = r15; + + /* Restore flags */ + r18 = tmpcr; + __asm__ __volatile__ ("mtcr 18"); + r18 = tmpxer; + __asm__ __volatile__ ("mtxer 18"); + + printf("%s %08x, %d => %08x, (%08x %08x)\n", + name, iargs[nb_iargs-1+i], j, /*&iargs_priv[nb_iargs-1], */ iargs_priv[nb_iargs-1+i], /*rA, */ flags, xer); + } + free(iargs_priv); +} + +static void test_int_st_three_regs (const unsigned char *name, + test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t rA, flags, xer, tmpcr, tmpxer; + int i, j; + uint32_t *iargs_priv; + + // private iargs table to store to + iargs_priv = malloc(nb_iargs * sizeof(uint32_t)); + for (i=0; i %08x, (%08x %08x)\n", + name, iargs[i], /*&iargs_priv[0], */ j, iargs_priv[i], /*rA, */ flags, xer); + } + free(iargs_priv); +} + + +/* Used in do_tests, indexed by flags->nb_args + Elements correspond to enum test_flags::num args +*/ +static test_loop_t int_loops[] = { + &test_int_one_arg, + &test_int_two_args, + &test_int_three_args, + &test_int_two_args, + &test_int_one_reg_imm16, + &test_int_one_reg_imm16, + &test_int_special, + &test_int_ld_one_reg_imm16, + &test_int_ld_two_regs, + &test_int_st_two_regs_imm16, + &test_int_st_three_regs, +}; + +#if !defined (NO_FLOAT) +static void test_float_three_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + double res; + uint64_t u0, u1, u2, ur; + volatile uint32_t flags, tmpcr, tmpxer; + int i, j, k; + + for (i=0; i %016llx (%08x)\n", + name, u0, u1, u2, ur, flags); + } + if (verbose) printf("\n"); + } + } +} + +static void test_float_two_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + double res; + uint64_t u0, u1, ur; + volatile uint32_t flags, tmpcr, tmpxer; + int i, j; + + for (i=0; i %016llx (%08x)\n", + name, u0, u1, ur, flags); + } + if (verbose) printf("\n"); + } +} + +static void test_float_one_arg (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + double res; + uint64_t u0, ur; + volatile uint32_t flags, tmpcr, tmpxer; + int i; + + for (i=0; i %016llx (%08x)\n", name, u0, ur, flags); + } +} + +/* Special test cases for: + * mffs + * mtfsb0 + * mtfsb1 + */ +static special_t special_float_ops[] = { +#if 0 + { + "mffs", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mffs.", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mtfsb0", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mtfsb0.", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mtfsb1", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mtfsb1.", /* One 5 bits immediate argument */ + &mffs_cb, + }, + { + "mtfsf", /* One register + 1 8 bits immediate argument */ + &mtfsf_cb, + }, + { + "mtfsf.", /* One register + 1 8 bits immediate argument */ + &mtfsf_cb, + }, + { + "mtfsfi", /* One 5 bits argument + 1 5 bits argument */ + &mtfsfi_cb, + }, + { + "mtfsfi.", /* One 5 bits argument + 1 5 bits argument */ + &mtfsfi_cb, + }, +#endif + { + NULL, + NULL, + }, +}; + +static void test_float_special (const unsigned char *name, test_func_t func, + uint32_t test_flags) +{ + test_special(special_float_ops, name, func, test_flags); +} + +/* Used in do_tests, indexed by flags->nb_args + Elements correspond to enum test_flags::num args +*/ +static test_loop_t float_loops[] = { + &test_float_one_arg, + &test_float_two_args, + &test_float_three_args, + &test_float_two_args, + NULL, + NULL, + &test_float_special, + NULL, + NULL, + NULL, + NULL, +}; +#endif /* !defined (NO_FLOAT) */ + + +#if defined (HAS_ALTIVEC) + +/* Ref: vector insns to test setting CR, VSCR: + volatile vector unsigned int v1 = + // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF }; + (vector unsigned int){ 0x80808080,0x80808080,0x80808080,0x80808080 }; + volatile vector unsigned int v2 = + // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF }; + (vector unsigned int){ 0x01010101,0x01010101,0x01010101,0x01010101 }; + //__asm__ __volatile__ ("vcmpequw. 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets CR[6] + //__asm__ __volatile__ ("vpkswss 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets VSCR[SAT] + __asm__ __volatile__ ("vsubsbs 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets VSCR[SAT] +*/ + +#define DEFAULT_VSCR 0x00010000 + +static void test_av_int_one_arg (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i; + + for (i=0; i r14 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src = (unsigned int*)&vec_in; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %08x %08x %08x %08x\n", name, + src[0], src[1], src[2], src[3]); + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } +} + +static void test_av_int_two_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i,j; + + for (i=0; i r14,r15 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_in2; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: ", name); + printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]); + printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]); + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } +} + +static void test_av_int_three_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i,j,k; + + for (i=0; i r14,r15,r16 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2)); + __asm__ __volatile__ ("vor 16,%0,%0" : : "vr" (vec_in3)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_in2; + unsigned int* src3 = (unsigned int*)&vec_in3; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name, + src1[0], src1[1], src1[2], src1[3], + src2[0], src2[1], src2[2], src2[3], + src3[0], src3[1], src3[2], src3[3]); + + printf("%s: => %08x%08x%08x%08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } + } +} + + +static void vs128_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i,j; + + for (i=0; i r14,r15 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_shft)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_shft; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: ", name); + printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]); + printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]); + + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } +} + +static void vsplt_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + uint32_t func_buf[2], *p; + int i,j; + + for (i=0; i r14 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: ", name); + printf("%08x %08x %08x %08x, %u\n", src1[0], src1[1], src1[2], src1[3], j); + + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } +} + +static void vspltis_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + uint32_t func_buf[2], *p; + int i; + + for (i=0; i<32; i++) { + vector unsigned int vec_out = (vector unsigned int){ 0,0,0,0 }; + + /* Patch up the instruction */ + p = (void *)func; + func_buf[1] = p[1]; + patch_op_imm(func_buf, p, i, 16, 5); + func = (void *)func_buf; + + /* Save flags */ + __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + + // reset VSCR and CR + vector unsigned int vscr = (vector unsigned int){ 0,0,0,0x00010000 }; + flags = 0; + __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) ); + __asm__ __volatile__ ("mtcr %0" : : "r" (flags)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %2d => ", name, i); + + printf("%08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } +} + +static void vsldoi_cb (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + uint32_t func_buf[2], *p; + int i,j,k; + + for (i=0; i r14,r15 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_in2; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: ", name); + printf("%08x%08x%08x%08x, %08x%08x%08x%08x, %u\n", + src1[0], src1[1], src1[2], src1[3], + src2[0], src2[1], src2[2], src2[3], k); + + printf("%s: => %08x %08x %08x %08x] ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } + } +} + +static special_t special_av_int_ops[] = { + { + "vsr", /* Two registers arguments */ + &vs128_cb, + }, + { + "vsl", /* Two registers arguments */ + &vs128_cb, + }, + { + "vspltb", /* One reg, one 5-bit uimm arguments */ + &vsplt_cb, + }, + { + "vsplth", /* One reg, one 5-bit uimm arguments */ + &vsplt_cb, + }, + { + "vspltw", /* One reg, one 5-bit uimm arguments */ + &vsplt_cb, + }, + { + "vspltisb", /* One reg, one 5-bit uimm arguments */ + &vspltis_cb, + }, + { + "vspltish", /* One reg, one 5-bit uimm arguments */ + &vspltis_cb, + }, + { + "vspltisw", /* One reg, one 5-bit uimm arguments */ + &vspltis_cb, + }, + { + "vsldoi", /* Two regs, one 4-bit uimm arguments */ + &vsldoi_cb, + }, +}; + +static void test_av_int_special (const unsigned char *name, test_func_t func, + uint32_t test_flags) +{ + test_special(special_av_int_ops, name, func, test_flags); +} + +/* Used in do_tests, indexed by flags->nb_args + Elements correspond to enum test_flags::num args +*/ +static test_loop_t altivec_int_loops[] = { + &test_av_int_one_arg, + &test_av_int_two_args, + &test_av_int_three_args, + &test_av_int_two_args, + NULL, + NULL, + &test_av_int_special, + NULL, + NULL, + NULL, + NULL, +}; + + +static void test_av_float_one_arg (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i; + + for (i=0; i r14 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src = (unsigned int*)&vec_in; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %08x %08x %08x %08x\n", name, + src[0], src[1], src[2], src[3]); + + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } +} + +static void test_av_float_two_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i,j; + + for (i=0; i r14,r15 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_in2; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x\n", name, + src1[0], src1[1], src1[2], src1[3], + src2[0], src2[1], src2[2], src2[3]); + + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } +} + +static void test_av_float_three_args (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t flags, tmpcr; + volatile vector unsigned int tmpvscr; + int i,j,k; + + for (i=0; i r14,r15,r16 + __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1)); + __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2)); + __asm__ __volatile__ ("vor 16,%0,%0" : : "vr" (vec_in3)); + + // do stuff + (*func)(); + + // retrieve output <- r17 + __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + + // get CR,VSCR flags + __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); + __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + + /* Restore flags */ + __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); + __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr)); + + unsigned int* src1 = (unsigned int*)&vec_in1; + unsigned int* src2 = (unsigned int*)&vec_in2; + unsigned int* src3 = (unsigned int*)&vec_in3; + unsigned int* dst = (unsigned int*)&vec_out; + printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name, + src1[0], src1[1], src1[2], src1[3], + src2[0], src2[1], src2[2], src2[3], + src3[0], src3[1], src3[2], src3[3]); + + printf("%s: => %08x %08x %08x %08x ", name, + dst[0], dst[1], dst[2], dst[3]); +#if defined TEST_VSCR_SAT + unsigned int* p_vscr = (unsigned int*)𝓋 + printf("(%08x, %08x)\n", flags, p_vscr[3]); +#else + printf("(%08x)\n", flags); +#endif + } + if (verbose) printf("\n"); + } + } +} + +/* Used in do_tests, indexed by flags->nb_args + Elements correspond to enum test_flags::num args +*/ +static test_loop_t altivec_float_loops[] = { + &test_av_float_one_arg, + &test_av_float_two_args, + &test_av_float_three_args, + &test_av_float_two_args, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +#endif /* defined (HAS_ALTIVEC) */ + + +#if defined (IS_PPC405) +static void test_ppc405 (const unsigned char *name, test_func_t func, + unused uint32_t test_flags) +{ + volatile uint32_t res, flags, xer, tmpcr, tmpxer; + int i, j, k; + + for (i=0; i %08x (%08x %08x)\n", + name, iargs[i], iargs[j], iargs[k], res, flags, xer); + } + if (verbose) printf("\n"); + } + } +} +#endif /* defined (IS_PPC405) */ + +static int check_filter (unsigned char *filter) +{ + unsigned char *c; + int ret = 1; + + if (filter != NULL) { + c = strchr(filter, '*'); + if (c != NULL) { + *c = '\0'; + ret = 0; + } + } + + return ret; +} + +static int check_name (const unsigned char *name, const unsigned char *filter, + int exact) +{ + int nlen, flen; + int ret = 0; + + if (filter != NULL) { + for (; isspace(*name); name++) + continue; + FDPRINTF("Check '%s' againt '%s' (%s match)\n", + name, filter, exact ? "exact" : "starting"); + nlen = strlen(name); + flen = strlen(filter); + if (exact) { + if (nlen == flen && memcmp(name, filter, flen) == 0) + ret = 1; + } else { + if (flen <= nlen && memcmp(name, filter, flen) == 0) + ret = 1; + } + } else { + ret = 1; + } + return ret; +} + + + +typedef struct insn_sel_flags_t_struct { + int one_arg, two_args, three_args; + int arith, logical, compare, ldst; + int integer, floats, p405, altivec, faltivec; + int cr; +} insn_sel_flags_t; + +static void do_tests ( insn_sel_flags_t seln_flags, + unsigned char *filter) +{ +#if defined (IS_PPC405) + test_loop_t tmpl; +#endif + test_loop_t *loop; + test_t *tests; + int nb_args, type, family; + int i, j, n; + int exact; + + exact = check_filter(filter); + n = 0; + for (i=0; all_tests[i].name != NULL; i++) { + nb_args = all_tests[i].flags & PPC_NB_ARGS; + /* Check number of arguments */ + if ((nb_args == 1 && !seln_flags.one_arg) || + (nb_args == 2 && !seln_flags.two_args) || + (nb_args == 3 && !seln_flags.three_args)) + continue; + /* Check instruction type */ + type = all_tests[i].flags & PPC_TYPE; + if ((type == PPC_ARITH && !seln_flags.arith) || + (type == PPC_LOGICAL && !seln_flags.logical) || + (type == PPC_COMPARE && !seln_flags.compare) || + (type == PPC_LDST && !seln_flags.ldst)) + continue; + /* Check instruction family */ + family = all_tests[i].flags & PPC_FAMILY; + if ((family == PPC_INTEGER && !seln_flags.integer) || + (family == PPC_FLOAT && !seln_flags.floats) || + (family == PPC_405 && !seln_flags.p405) || + (family == PPC_ALTIVEC && !seln_flags.altivec) || + (family == PPC_FALTIVEC && !seln_flags.faltivec)) + continue; + /* Check flags update */ + if (((all_tests[i].flags & PPC_CR) && seln_flags.cr == 0) || + (!(all_tests[i].flags & PPC_CR) && seln_flags.cr == 1)) + continue; + /* All passed, do the tests */ + tests = all_tests[i].tests; + /* Select the test loop */ + switch (family) { + case PPC_INTEGER: + loop = &int_loops[nb_args - 1]; + break; + case PPC_FLOAT: +#if !defined (NO_FLOAT) + loop = &float_loops[nb_args - 1]; + break; +#else + fprintf(stderr, "Sorry. " + "PPC floating point instructions tests " + "are disabled on your host\n"); +#endif /* !defined (NO_FLOAT) */ + + case PPC_405: +#if defined (IS_PPC405) + tmpl = &test_ppc405; + loop = &tmpl; + break; +#else + fprintf(stderr, "Sorry. " + "PPC405 instructions tests are disabled on your host\n"); + continue; +#endif /* defined (IS_PPC405) */ + case PPC_ALTIVEC: +#if defined (HAS_ALTIVEC) + loop = &altivec_int_loops[nb_args - 1]; + break; +#else + fprintf(stderr, "Sorry. " + "Altivec instructions tests are disabled on your host\n"); + continue; +#endif + case PPC_FALTIVEC: +#if defined (HAS_ALTIVEC) + loop = &altivec_float_loops[nb_args - 1]; + break; +#else + fprintf(stderr, "Sorry. " + "Altivec float instructions tests " + "are disabled on your host\n"); +#endif + continue; + default: + printf("ERROR: unknown insn family %08x\n", family); + continue; + } + if (1 || verbose > 0) + printf("%s:\n", all_tests[i].name); + for (j=0; tests[j].name != NULL; j++) { + if (check_name(tests[j].name, filter, exact)) { + if (verbose > 1) + printf("Test instruction %s\n", tests[j].name); + (*loop)(tests[j].name, tests[j].func, all_tests[i].flags); + printf("\n"); + n++; + } + } + if (verbose) printf("\n"); + } + printf("All done. Tested %d different instructions\n", n); +} + + +static void usage (void) +{ +#if !defined (USAGE_SIMPLE) + fprintf(stderr, + "test-ppc [-1] [-2] [-3] [-*] [-t ] [-f ] [-u] " + "[-n ] [-r ] [-h]\n" + "\t-1: test opcodes with one argument\n" + "\t-2: test opcodes with two arguments\n" + "\t-3: test opcodes with three arguments\n" + "\t-*: launch test without checking the number of arguments\n" + "\t-t: launch test for instructions of type \n" + "\t recognized types:\n" + "\t\tarith (or a)\n" + "\t\tlogical (or l)\n" + "\t\tcompare (or c)\n" + "\t\tstoreload (or s)\n" + "\t-f: launch test for instructions of family \n" + "\t recognized families:\n" + "\t\tinteger (or i)\n" + "\t\tfloat (or f)\n" + "\t\tppc405 (or mac)\n" + "\t\taltivec (or a)\n" + "\t-u: test instructions that update flags\n" + "\t-n: filter instructions with \n" + "\t can be in two forms:\n" + "\t\tname : filter functions that exactly match \n" + "\t\tname* : filter functions that start with \n" + "\t-r: set size of arg tables to use to define \n" + "\t recognized types:\n" + "\t\tlarge (or l)\n" + "\t\tsmall (or s) - default\n" + "\t-v: verbose (-v -v for more)\n" + "\t-h: print this help\n" + ); +#else + fprintf(stderr, + "test-ppc [-a]\n" + "\t-a: include tests for altivec instructions\n" + ); +#endif +} + +int main (int argc, char **argv) +{ +#if !defined (USAGE_SIMPLE) + unsigned char *tmp, *filter = NULL; + insn_sel_flags_t flags; + int c; + + flags.one_arg = 0; + flags.two_args = 0; + flags.three_args = 0; + flags.arith = 0; + flags.logical = 0; + flags.compare = 0; + flags.ldst = 0; + flags.integer = 0; + flags.floats = 0; + flags.p405 = 0; + flags.altivec = 0; + flags.faltivec = 0; + flags.cr = -1; + + while ((c = getopt(argc, argv, "123t:f:n:r:uvh")) != -1) { + switch (c) { + case '1': + flags.one_arg = 1; + break; + case '2': + flags.two_args = 1; + break; + case '3': + flags.three_args = 1; + break; + case 't': + tmp = optarg; + if (strcmp(tmp, "arith") == 0 || strcmp(tmp, "a") == 0) { + flags.arith = 1; + } else if (strcmp(tmp, "logical") == 0 || strcmp(tmp, "l") == 0) { + flags.logical = 1; + } else if (strcmp(tmp, "compare") == 0 || strcmp(tmp, "c") == 0) { + flags.compare = 1; + } else if (strcmp(tmp, "storeload") == 0 || strcmp(tmp, "s") == 0) { + flags.ldst = 1; + } else { + goto bad_arg; + } + break; + case 'f': + tmp = optarg; + if (strcmp(tmp, "integer") == 0 || strcmp(tmp, "i") == 0) { + flags.integer = 1; + } else if (strcmp(tmp, "float") == 0 || strcmp(tmp, "f") == 0) { + flags.floats = 1; + } else if (strcmp(tmp, "ppc405") == 0 || strcmp(tmp, "mac") == 0) { + flags.p405 = 1; + } else if (strcmp(tmp, "altivec") == 0 || strcmp(tmp, "a") == 0) { + flags.altivec = 1; + flags.faltivec = 1; + } else { + goto bad_arg; + } + break; + case 'n': + filter = optarg; + break; + case 'r': + tmp = optarg; + if (strcmp(tmp, "large") == 0 || strcmp(tmp, "l") == 0) { + arg_list_size = 1; + } else if (strcmp(tmp, "small") == 0 || strcmp(tmp, "s") == 0) { + arg_list_size = 0; + } else { + goto bad_arg; + } + break; + + case 'u': + flags.cr = 1; + break; + case 'h': + usage(); + return 0; + case 'v': + verbose++; + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + return 1; + bad_arg: + usage(); + fprintf(stderr, "Bad argument for '%c': '%s'\n", c, tmp); + return 1; + } + } + if (argc != optind) { + usage(); + fprintf(stderr, "Bad number of arguments\n"); + return 1; + } + + // Default n_args + if (flags.one_arg == 0 && flags.two_args == 0 && flags.three_args == 0) { + flags.one_arg = 1; + flags.two_args = 1; + flags.three_args = 1; + } + // Default type + if (flags.arith == 0 && flags.logical == 0 && + flags.compare == 0 && flags.ldst == 0) { + flags.arith = 1; + flags.logical = 1; + flags.compare = 1; + flags.ldst = 1; + } + // Default family + if (flags.integer == 0 && flags.floats == 0 && + flags.p405 == 0 && flags.altivec == 0 && flags.faltivec == 0) { + flags.integer = 1; + flags.floats = 1; + flags.p405 = 1; + flags.altivec = 1; + flags.faltivec = 1; + } + // Default cr update + if (flags.cr == -1) + flags.cr = 2; // both + +#else + /* Simple usage: + ./test-ppc => all insns, except AV + ./test-ppc -a => all insns, including AV + */ + unsigned char *filter = NULL; + insn_sel_flags_t flags; + int c; + + // Args + flags.one_arg = 1; + flags.two_args = 1; + flags.three_args = 1; + // Type + flags.arith = 1; + flags.logical = 1; + flags.compare = 1; + flags.ldst = 1; + // Family + flags.integer = 1; + flags.floats = 0; + flags.p405 = 0; + flags.altivec = 0; + flags.faltivec = 0; + // Flags + flags.cr = 2; + + while ((c = getopt(argc, argv, "ahv")) != -1) { + switch (c) { + case 'a': + flags.altivec = 1; +// flags.faltivec = 1; // TODO: not yet supported + break; + case 'h': + usage(); + return 0; + case 'v': + verbose++; + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + return 1; + } + } + + arg_list_size = 0; +#endif + + + // NO FLOAT ALTIVEC + flags.faltivec = 0; + + + build_iargs_table(); + build_fargs_table(); + build_ii16_table(); +#if defined (HAS_ALTIVEC) + build_viargs_table(); + build_vfargs_table(); +#endif + // dump_iargs(); + // dump_iargs16(); + // dump_vfargs(); + + if (verbose > 1) { + printf("\nInstruction Selection:\n"); + printf(" n_args: \n"); + printf(" one_arg = %d\n", flags.one_arg); + printf(" two_args = %d\n", flags.two_args); + printf(" three_args = %d\n", flags.three_args); + printf(" type: \n"); + printf(" arith = %d\n", flags.arith); + printf(" logical = %d\n", flags.logical); + printf(" compare = %d\n", flags.compare); + printf(" ldst = %d\n", flags.ldst); + printf(" family: \n"); + printf(" integer = %d\n", flags.integer); + printf(" floats = %d\n", flags.floats); + printf(" p405 = %d\n", flags.p405); + printf(" altivec = %d\n", flags.altivec); + printf(" faltivec = %d\n", flags.faltivec); + printf(" cr update: \n"); + printf(" cr = %d\n", flags.cr); + printf("\n"); + printf(" num args: \n"); + printf(" iargs - %d\n", nb_iargs); + printf(" fargs - %d\n", nb_fargs); +#if defined (HAS_ALTIVEC) + printf(" viargs - %d\n", nb_viargs); + printf(" vfargs - %d\n", nb_vfargs); +#endif + printf("\n"); + } + + do_tests( flags, filter ); + + return 0; +} diff --git a/none/tests/ppc32/jm-insns.stderr.exp b/none/tests/ppc32/jm-insns.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc32/jm-insns.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/jm-insns.stdout.exp b/none/tests/ppc32/jm-insns.stdout.exp new file mode 100644 index 0000000000..5bed30d323 --- /dev/null +++ b/none/tests/ppc32/jm-insns.stdout.exp @@ -0,0 +1,1632 @@ +PPC integer arith insns with two args: + add 00000000, 00000000 => 00000000 (00000000 00000000) + add 00000000, 000f423f => 000f423f (00000000 00000000) + add 00000000, ffffffff => ffffffff (00000000 00000000) + add 000f423f, 00000000 => 000f423f (00000000 00000000) + add 000f423f, 000f423f => 001e847e (00000000 00000000) + add 000f423f, ffffffff => 000f423e (00000000 00000000) + add ffffffff, 00000000 => ffffffff (00000000 00000000) + add ffffffff, 000f423f => 000f423e (00000000 00000000) + add ffffffff, ffffffff => fffffffe (00000000 00000000) + + addo 00000000, 00000000 => 00000000 (00000000 00000000) + addo 00000000, 000f423f => 000f423f (00000000 00000000) + addo 00000000, ffffffff => ffffffff (00000000 00000000) + addo 000f423f, 00000000 => 000f423f (00000000 00000000) + addo 000f423f, 000f423f => 001e847e (00000000 00000000) + addo 000f423f, ffffffff => 000f423e (00000000 00000000) + addo ffffffff, 00000000 => ffffffff (00000000 00000000) + addo ffffffff, 000f423f => 000f423e (00000000 00000000) + addo ffffffff, ffffffff => fffffffe (00000000 00000000) + + addc 00000000, 00000000 => 00000000 (00000000 00000000) + addc 00000000, 000f423f => 000f423f (00000000 00000000) + addc 00000000, ffffffff => ffffffff (00000000 00000000) + addc 000f423f, 00000000 => 000f423f (00000000 00000000) + addc 000f423f, 000f423f => 001e847e (00000000 00000000) + addc 000f423f, ffffffff => 000f423e (00000000 20000000) + addc ffffffff, 00000000 => ffffffff (00000000 00000000) + addc ffffffff, 000f423f => 000f423e (00000000 20000000) + addc ffffffff, ffffffff => fffffffe (00000000 20000000) + + addco 00000000, 00000000 => 00000000 (00000000 00000000) + addco 00000000, 000f423f => 000f423f (00000000 00000000) + addco 00000000, ffffffff => ffffffff (00000000 00000000) + addco 000f423f, 00000000 => 000f423f (00000000 00000000) + addco 000f423f, 000f423f => 001e847e (00000000 00000000) + addco 000f423f, ffffffff => 000f423e (00000000 20000000) + addco ffffffff, 00000000 => ffffffff (00000000 00000000) + addco ffffffff, 000f423f => 000f423e (00000000 20000000) + addco ffffffff, ffffffff => fffffffe (00000000 20000000) + + divw 00000000, 00000000 => 00000000 (00000000 00000000) + divw 00000000, 000f423f => 00000000 (00000000 00000000) + divw 00000000, ffffffff => 00000000 (00000000 00000000) + divw 000f423f, 00000000 => 00000000 (00000000 00000000) + divw 000f423f, 000f423f => 00000001 (00000000 00000000) + divw 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + divw ffffffff, 00000000 => 00000000 (00000000 00000000) + divw ffffffff, 000f423f => 00000000 (00000000 00000000) + divw ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwo 00000000, 00000000 => 00000000 (00000000 c0000000) + divwo 00000000, 000f423f => 00000000 (00000000 00000000) + divwo 00000000, ffffffff => 00000000 (00000000 00000000) + divwo 000f423f, 00000000 => 00000000 (00000000 c0000000) + divwo 000f423f, 000f423f => 00000001 (00000000 00000000) + divwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + divwo ffffffff, 00000000 => 00000000 (00000000 c0000000) + divwo ffffffff, 000f423f => 00000000 (00000000 00000000) + divwo ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwu 00000000, 00000000 => 00000000 (00000000 00000000) + divwu 00000000, 000f423f => 00000000 (00000000 00000000) + divwu 00000000, ffffffff => 00000000 (00000000 00000000) + divwu 000f423f, 00000000 => 00000000 (00000000 00000000) + divwu 000f423f, 000f423f => 00000001 (00000000 00000000) + divwu 000f423f, ffffffff => 00000000 (00000000 00000000) + divwu ffffffff, 00000000 => 00000000 (00000000 00000000) + divwu ffffffff, 000f423f => 000010c6 (00000000 00000000) + divwu ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwuo 00000000, 00000000 => 00000000 (00000000 c0000000) + divwuo 00000000, 000f423f => 00000000 (00000000 00000000) + divwuo 00000000, ffffffff => 00000000 (00000000 00000000) + divwuo 000f423f, 00000000 => 00000000 (00000000 c0000000) + divwuo 000f423f, 000f423f => 00000001 (00000000 00000000) + divwuo 000f423f, ffffffff => 00000000 (00000000 00000000) + divwuo ffffffff, 00000000 => 00000000 (00000000 c0000000) + divwuo ffffffff, 000f423f => 000010c6 (00000000 00000000) + divwuo ffffffff, ffffffff => 00000001 (00000000 00000000) + + mulhw 00000000, 00000000 => 00000000 (00000000 00000000) + mulhw 00000000, 000f423f => 00000000 (00000000 00000000) + mulhw 00000000, ffffffff => 00000000 (00000000 00000000) + mulhw 000f423f, 00000000 => 00000000 (00000000 00000000) + mulhw 000f423f, 000f423f => 000000e8 (00000000 00000000) + mulhw 000f423f, ffffffff => ffffffff (00000000 00000000) + mulhw ffffffff, 00000000 => 00000000 (00000000 00000000) + mulhw ffffffff, 000f423f => ffffffff (00000000 00000000) + mulhw ffffffff, ffffffff => 00000000 (00000000 00000000) + + mulhwu 00000000, 00000000 => 00000000 (00000000 00000000) + mulhwu 00000000, 000f423f => 00000000 (00000000 00000000) + mulhwu 00000000, ffffffff => 00000000 (00000000 00000000) + mulhwu 000f423f, 00000000 => 00000000 (00000000 00000000) + mulhwu 000f423f, 000f423f => 000000e8 (00000000 00000000) + mulhwu 000f423f, ffffffff => 000f423e (00000000 00000000) + mulhwu ffffffff, 00000000 => 00000000 (00000000 00000000) + mulhwu ffffffff, 000f423f => 000f423e (00000000 00000000) + mulhwu ffffffff, ffffffff => fffffffe (00000000 00000000) + + mullw 00000000, 00000000 => 00000000 (00000000 00000000) + mullw 00000000, 000f423f => 00000000 (00000000 00000000) + mullw 00000000, ffffffff => 00000000 (00000000 00000000) + mullw 000f423f, 00000000 => 00000000 (00000000 00000000) + mullw 000f423f, 000f423f => d4868b81 (00000000 00000000) + mullw 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + mullw ffffffff, 00000000 => 00000000 (00000000 00000000) + mullw ffffffff, 000f423f => fff0bdc1 (00000000 00000000) + mullw ffffffff, ffffffff => 00000001 (00000000 00000000) + + mullwo 00000000, 00000000 => 00000000 (00000000 00000000) + mullwo 00000000, 000f423f => 00000000 (00000000 00000000) + mullwo 00000000, ffffffff => 00000000 (00000000 00000000) + mullwo 000f423f, 00000000 => 00000000 (00000000 00000000) + mullwo 000f423f, 000f423f => d4868b81 (00000000 c0000000) + mullwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + mullwo ffffffff, 00000000 => 00000000 (00000000 00000000) + mullwo ffffffff, 000f423f => fff0bdc1 (00000000 00000000) + mullwo ffffffff, ffffffff => 00000001 (00000000 00000000) + + subf 00000000, 00000000 => 00000000 (00000000 00000000) + subf 00000000, 000f423f => 000f423f (00000000 00000000) + subf 00000000, ffffffff => ffffffff (00000000 00000000) + subf 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subf 000f423f, 000f423f => 00000000 (00000000 00000000) + subf 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + subf ffffffff, 00000000 => 00000001 (00000000 00000000) + subf ffffffff, 000f423f => 000f4240 (00000000 00000000) + subf ffffffff, ffffffff => 00000000 (00000000 00000000) + + subfo 00000000, 00000000 => 00000000 (00000000 00000000) + subfo 00000000, 000f423f => 000f423f (00000000 00000000) + subfo 00000000, ffffffff => ffffffff (00000000 00000000) + subfo 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfo 000f423f, 000f423f => 00000000 (00000000 00000000) + subfo 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + subfo ffffffff, 00000000 => 00000001 (00000000 00000000) + subfo ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfo ffffffff, ffffffff => 00000000 (00000000 00000000) + + subfc 00000000, 00000000 => 00000000 (00000000 20000000) + subfc 00000000, 000f423f => 000f423f (00000000 20000000) + subfc 00000000, ffffffff => ffffffff (00000000 20000000) + subfc 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfc 000f423f, 000f423f => 00000000 (00000000 20000000) + subfc 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfc ffffffff, 00000000 => 00000001 (00000000 00000000) + subfc ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfc ffffffff, ffffffff => 00000000 (00000000 20000000) + + subfco 00000000, 00000000 => 00000000 (00000000 20000000) + subfco 00000000, 000f423f => 000f423f (00000000 20000000) + subfco 00000000, ffffffff => ffffffff (00000000 20000000) + subfco 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfco 000f423f, 000f423f => 00000000 (00000000 20000000) + subfco 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfco ffffffff, 00000000 => 00000001 (00000000 00000000) + subfco ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfco ffffffff, ffffffff => 00000000 (00000000 20000000) + +PPC integer arith insns with two args with flags update: + add. 00000000, 00000000 => 00000000 (20000000 00000000) + add. 00000000, 000f423f => 000f423f (40000000 00000000) + add. 00000000, ffffffff => ffffffff (80000000 00000000) + add. 000f423f, 00000000 => 000f423f (40000000 00000000) + add. 000f423f, 000f423f => 001e847e (40000000 00000000) + add. 000f423f, ffffffff => 000f423e (40000000 00000000) + add. ffffffff, 00000000 => ffffffff (80000000 00000000) + add. ffffffff, 000f423f => 000f423e (40000000 00000000) + add. ffffffff, ffffffff => fffffffe (80000000 00000000) + + addo. 00000000, 00000000 => 00000000 (20000000 00000000) + addo. 00000000, 000f423f => 000f423f (40000000 00000000) + addo. 00000000, ffffffff => ffffffff (80000000 00000000) + addo. 000f423f, 00000000 => 000f423f (40000000 00000000) + addo. 000f423f, 000f423f => 001e847e (40000000 00000000) + addo. 000f423f, ffffffff => 000f423e (40000000 00000000) + addo. ffffffff, 00000000 => ffffffff (80000000 00000000) + addo. ffffffff, 000f423f => 000f423e (40000000 00000000) + addo. ffffffff, ffffffff => fffffffe (80000000 00000000) + + addc. 00000000, 00000000 => 00000000 (20000000 00000000) + addc. 00000000, 000f423f => 000f423f (40000000 00000000) + addc. 00000000, ffffffff => ffffffff (80000000 00000000) + addc. 000f423f, 00000000 => 000f423f (40000000 00000000) + addc. 000f423f, 000f423f => 001e847e (40000000 00000000) + addc. 000f423f, ffffffff => 000f423e (40000000 20000000) + addc. ffffffff, 00000000 => ffffffff (80000000 00000000) + addc. ffffffff, 000f423f => 000f423e (40000000 20000000) + addc. ffffffff, ffffffff => fffffffe (80000000 20000000) + + addco. 00000000, 00000000 => 00000000 (20000000 00000000) + addco. 00000000, 000f423f => 000f423f (40000000 00000000) + addco. 00000000, ffffffff => ffffffff (80000000 00000000) + addco. 000f423f, 00000000 => 000f423f (40000000 00000000) + addco. 000f423f, 000f423f => 001e847e (40000000 00000000) + addco. 000f423f, ffffffff => 000f423e (40000000 20000000) + addco. ffffffff, 00000000 => ffffffff (80000000 00000000) + addco. ffffffff, 000f423f => 000f423e (40000000 20000000) + addco. ffffffff, ffffffff => fffffffe (80000000 20000000) + + divw. 00000000, 00000000 => 00000000 (20000000 00000000) + divw. 00000000, 000f423f => 00000000 (20000000 00000000) + divw. 00000000, ffffffff => 00000000 (20000000 00000000) + divw. 000f423f, 00000000 => 00000000 (20000000 00000000) + divw. 000f423f, 000f423f => 00000001 (40000000 00000000) + divw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + divw. ffffffff, 00000000 => 00000000 (20000000 00000000) + divw. ffffffff, 000f423f => 00000000 (20000000 00000000) + divw. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwo. 00000000, 00000000 => 00000000 (30000000 c0000000) + divwo. 00000000, 000f423f => 00000000 (20000000 00000000) + divwo. 00000000, ffffffff => 00000000 (20000000 00000000) + divwo. 000f423f, 00000000 => 00000000 (30000000 c0000000) + divwo. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + divwo. ffffffff, 00000000 => 00000000 (30000000 c0000000) + divwo. ffffffff, 000f423f => 00000000 (20000000 00000000) + divwo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwu. 00000000, 00000000 => 00000000 (20000000 00000000) + divwu. 00000000, 000f423f => 00000000 (20000000 00000000) + divwu. 00000000, ffffffff => 00000000 (20000000 00000000) + divwu. 000f423f, 00000000 => 00000000 (20000000 00000000) + divwu. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwu. 000f423f, ffffffff => 00000000 (20000000 00000000) + divwu. ffffffff, 00000000 => 00000000 (20000000 00000000) + divwu. ffffffff, 000f423f => 000010c6 (40000000 00000000) + divwu. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwuo. 00000000, 00000000 => 00000000 (30000000 c0000000) + divwuo. 00000000, 000f423f => 00000000 (20000000 00000000) + divwuo. 00000000, ffffffff => 00000000 (20000000 00000000) + divwuo. 000f423f, 00000000 => 00000000 (30000000 c0000000) + divwuo. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwuo. 000f423f, ffffffff => 00000000 (20000000 00000000) + divwuo. ffffffff, 00000000 => 00000000 (30000000 c0000000) + divwuo. ffffffff, 000f423f => 000010c6 (40000000 00000000) + divwuo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + mulhw. 00000000, 00000000 => 00000000 (20000000 00000000) + mulhw. 00000000, 000f423f => 00000000 (20000000 00000000) + mulhw. 00000000, ffffffff => 00000000 (20000000 00000000) + mulhw. 000f423f, 00000000 => 00000000 (20000000 00000000) + mulhw. 000f423f, 000f423f => 000000e8 (40000000 00000000) + mulhw. 000f423f, ffffffff => ffffffff (80000000 00000000) + mulhw. ffffffff, 00000000 => 00000000 (20000000 00000000) + mulhw. ffffffff, 000f423f => ffffffff (80000000 00000000) + mulhw. ffffffff, ffffffff => 00000000 (20000000 00000000) + + mulhwu. 00000000, 00000000 => 00000000 (20000000 00000000) + mulhwu. 00000000, 000f423f => 00000000 (20000000 00000000) + mulhwu. 00000000, ffffffff => 00000000 (20000000 00000000) + mulhwu. 000f423f, 00000000 => 00000000 (20000000 00000000) + mulhwu. 000f423f, 000f423f => 000000e8 (40000000 00000000) + mulhwu. 000f423f, ffffffff => 000f423e (40000000 00000000) + mulhwu. ffffffff, 00000000 => 00000000 (20000000 00000000) + mulhwu. ffffffff, 000f423f => 000f423e (40000000 00000000) + mulhwu. ffffffff, ffffffff => fffffffe (80000000 00000000) + + mullw. 00000000, 00000000 => 00000000 (20000000 00000000) + mullw. 00000000, 000f423f => 00000000 (20000000 00000000) + mullw. 00000000, ffffffff => 00000000 (20000000 00000000) + mullw. 000f423f, 00000000 => 00000000 (20000000 00000000) + mullw. 000f423f, 000f423f => d4868b81 (80000000 00000000) + mullw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + mullw. ffffffff, 00000000 => 00000000 (20000000 00000000) + mullw. ffffffff, 000f423f => fff0bdc1 (80000000 00000000) + mullw. ffffffff, ffffffff => 00000001 (40000000 00000000) + + mullwo. 00000000, 00000000 => 00000000 (20000000 00000000) + mullwo. 00000000, 000f423f => 00000000 (20000000 00000000) + mullwo. 00000000, ffffffff => 00000000 (20000000 00000000) + mullwo. 000f423f, 00000000 => 00000000 (20000000 00000000) + mullwo. 000f423f, 000f423f => d4868b81 (90000000 c0000000) + mullwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + mullwo. ffffffff, 00000000 => 00000000 (20000000 00000000) + mullwo. ffffffff, 000f423f => fff0bdc1 (80000000 00000000) + mullwo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + subf. 00000000, 00000000 => 00000000 (20000000 00000000) + subf. 00000000, 000f423f => 000f423f (40000000 00000000) + subf. 00000000, ffffffff => ffffffff (80000000 00000000) + subf. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subf. 000f423f, 000f423f => 00000000 (20000000 00000000) + subf. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + subf. ffffffff, 00000000 => 00000001 (40000000 00000000) + subf. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subf. ffffffff, ffffffff => 00000000 (20000000 00000000) + + subfo. 00000000, 00000000 => 00000000 (20000000 00000000) + subfo. 00000000, 000f423f => 000f423f (40000000 00000000) + subfo. 00000000, ffffffff => ffffffff (80000000 00000000) + subfo. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfo. 000f423f, 000f423f => 00000000 (20000000 00000000) + subfo. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + subfo. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfo. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfo. ffffffff, ffffffff => 00000000 (20000000 00000000) + + subfc. 00000000, 00000000 => 00000000 (20000000 20000000) + subfc. 00000000, 000f423f => 000f423f (40000000 20000000) + subfc. 00000000, ffffffff => ffffffff (80000000 20000000) + subfc. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfc. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfc. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfc. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfc. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfc. ffffffff, ffffffff => 00000000 (20000000 20000000) + + subfco. 00000000, 00000000 => 00000000 (20000000 20000000) + subfco. 00000000, 000f423f => 000f423f (40000000 20000000) + subfco. 00000000, ffffffff => ffffffff (80000000 20000000) + subfco. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfco. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfco. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfco. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfco. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfco. ffffffff, ffffffff => 00000000 (20000000 20000000) + +PPC integer arith insns with two args and carry: + adde 00000000, 00000000 => 00000000 (00000000 00000000) + adde 00000000, 000f423f => 000f423f (00000000 00000000) + adde 00000000, ffffffff => ffffffff (00000000 00000000) + adde 000f423f, 00000000 => 000f423f (00000000 00000000) + adde 000f423f, 000f423f => 001e847e (00000000 00000000) + adde 000f423f, ffffffff => 000f423e (00000000 20000000) + adde ffffffff, 00000000 => ffffffff (00000000 00000000) + adde ffffffff, 000f423f => 000f423e (00000000 20000000) + adde ffffffff, ffffffff => fffffffe (00000000 20000000) + adde 00000000, 00000000 => 00000001 (00000000 00000000) + adde 00000000, 000f423f => 000f4240 (00000000 00000000) + adde 00000000, ffffffff => 00000000 (00000000 20000000) + adde 000f423f, 00000000 => 000f4240 (00000000 00000000) + adde 000f423f, 000f423f => 001e847f (00000000 00000000) + adde 000f423f, ffffffff => 000f423f (00000000 20000000) + adde ffffffff, 00000000 => 00000000 (00000000 20000000) + adde ffffffff, 000f423f => 000f423f (00000000 20000000) + adde ffffffff, ffffffff => ffffffff (00000000 20000000) + + addeo 00000000, 00000000 => 00000000 (00000000 00000000) + addeo 00000000, 000f423f => 000f423f (00000000 00000000) + addeo 00000000, ffffffff => ffffffff (00000000 00000000) + addeo 000f423f, 00000000 => 000f423f (00000000 00000000) + addeo 000f423f, 000f423f => 001e847e (00000000 00000000) + addeo 000f423f, ffffffff => 000f423e (00000000 20000000) + addeo ffffffff, 00000000 => ffffffff (00000000 00000000) + addeo ffffffff, 000f423f => 000f423e (00000000 20000000) + addeo ffffffff, ffffffff => fffffffe (00000000 20000000) + addeo 00000000, 00000000 => 00000001 (00000000 00000000) + addeo 00000000, 000f423f => 000f4240 (00000000 00000000) + addeo 00000000, ffffffff => 00000000 (00000000 20000000) + addeo 000f423f, 00000000 => 000f4240 (00000000 00000000) + addeo 000f423f, 000f423f => 001e847f (00000000 00000000) + addeo 000f423f, ffffffff => 000f423f (00000000 20000000) + addeo ffffffff, 00000000 => 00000000 (00000000 20000000) + addeo ffffffff, 000f423f => 000f423f (00000000 20000000) + addeo ffffffff, ffffffff => ffffffff (00000000 20000000) + + subfe 00000000, 00000000 => ffffffff (00000000 00000000) + subfe 00000000, 000f423f => 000f423e (00000000 20000000) + subfe 00000000, ffffffff => fffffffe (00000000 20000000) + subfe 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + subfe 000f423f, 000f423f => ffffffff (00000000 00000000) + subfe 000f423f, ffffffff => fff0bdbf (00000000 20000000) + subfe ffffffff, 00000000 => 00000000 (00000000 00000000) + subfe ffffffff, 000f423f => 000f423f (00000000 00000000) + subfe ffffffff, ffffffff => ffffffff (00000000 00000000) + subfe 00000000, 00000000 => 00000000 (00000000 20000000) + subfe 00000000, 000f423f => 000f423f (00000000 20000000) + subfe 00000000, ffffffff => ffffffff (00000000 20000000) + subfe 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfe 000f423f, 000f423f => 00000000 (00000000 20000000) + subfe 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfe ffffffff, 00000000 => 00000001 (00000000 00000000) + subfe ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfe ffffffff, ffffffff => 00000000 (00000000 20000000) + + subfeo 00000000, 00000000 => ffffffff (00000000 00000000) + subfeo 00000000, 000f423f => 000f423e (00000000 20000000) + subfeo 00000000, ffffffff => fffffffe (00000000 20000000) + subfeo 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + subfeo 000f423f, 000f423f => ffffffff (00000000 00000000) + subfeo 000f423f, ffffffff => fff0bdbf (00000000 20000000) + subfeo ffffffff, 00000000 => 00000000 (00000000 00000000) + subfeo ffffffff, 000f423f => 000f423f (00000000 00000000) + subfeo ffffffff, ffffffff => ffffffff (00000000 00000000) + subfeo 00000000, 00000000 => 00000000 (00000000 20000000) + subfeo 00000000, 000f423f => 000f423f (00000000 20000000) + subfeo 00000000, ffffffff => ffffffff (00000000 20000000) + subfeo 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfeo 000f423f, 000f423f => 00000000 (00000000 20000000) + subfeo 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfeo ffffffff, 00000000 => 00000001 (00000000 00000000) + subfeo ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfeo ffffffff, ffffffff => 00000000 (00000000 20000000) + +PPC integer arith insns with two args and carry with flags update: + adde. 00000000, 00000000 => 00000000 (20000000 00000000) + adde. 00000000, 000f423f => 000f423f (40000000 00000000) + adde. 00000000, ffffffff => ffffffff (80000000 00000000) + adde. 000f423f, 00000000 => 000f423f (40000000 00000000) + adde. 000f423f, 000f423f => 001e847e (40000000 00000000) + adde. 000f423f, ffffffff => 000f423e (40000000 20000000) + adde. ffffffff, 00000000 => ffffffff (80000000 00000000) + adde. ffffffff, 000f423f => 000f423e (40000000 20000000) + adde. ffffffff, ffffffff => fffffffe (80000000 20000000) + adde. 00000000, 00000000 => 00000001 (40000000 00000000) + adde. 00000000, 000f423f => 000f4240 (40000000 00000000) + adde. 00000000, ffffffff => 00000000 (20000000 20000000) + adde. 000f423f, 00000000 => 000f4240 (40000000 00000000) + adde. 000f423f, 000f423f => 001e847f (40000000 00000000) + adde. 000f423f, ffffffff => 000f423f (40000000 20000000) + adde. ffffffff, 00000000 => 00000000 (20000000 20000000) + adde. ffffffff, 000f423f => 000f423f (40000000 20000000) + adde. ffffffff, ffffffff => ffffffff (80000000 20000000) + + addeo. 00000000, 00000000 => 00000000 (20000000 00000000) + addeo. 00000000, 000f423f => 000f423f (40000000 00000000) + addeo. 00000000, ffffffff => ffffffff (80000000 00000000) + addeo. 000f423f, 00000000 => 000f423f (40000000 00000000) + addeo. 000f423f, 000f423f => 001e847e (40000000 00000000) + addeo. 000f423f, ffffffff => 000f423e (40000000 20000000) + addeo. ffffffff, 00000000 => ffffffff (80000000 00000000) + addeo. ffffffff, 000f423f => 000f423e (40000000 20000000) + addeo. ffffffff, ffffffff => fffffffe (80000000 20000000) + addeo. 00000000, 00000000 => 00000001 (40000000 00000000) + addeo. 00000000, 000f423f => 000f4240 (40000000 00000000) + addeo. 00000000, ffffffff => 00000000 (20000000 20000000) + addeo. 000f423f, 00000000 => 000f4240 (40000000 00000000) + addeo. 000f423f, 000f423f => 001e847f (40000000 00000000) + addeo. 000f423f, ffffffff => 000f423f (40000000 20000000) + addeo. ffffffff, 00000000 => 00000000 (20000000 20000000) + addeo. ffffffff, 000f423f => 000f423f (40000000 20000000) + addeo. ffffffff, ffffffff => ffffffff (80000000 20000000) + + subfe. 00000000, 00000000 => ffffffff (80000000 00000000) + subfe. 00000000, 000f423f => 000f423e (40000000 20000000) + subfe. 00000000, ffffffff => fffffffe (80000000 20000000) + subfe. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + subfe. 000f423f, 000f423f => ffffffff (80000000 00000000) + subfe. 000f423f, ffffffff => fff0bdbf (80000000 20000000) + subfe. ffffffff, 00000000 => 00000000 (20000000 00000000) + subfe. ffffffff, 000f423f => 000f423f (40000000 00000000) + subfe. ffffffff, ffffffff => ffffffff (80000000 00000000) + subfe. 00000000, 00000000 => 00000000 (20000000 20000000) + subfe. 00000000, 000f423f => 000f423f (40000000 20000000) + subfe. 00000000, ffffffff => ffffffff (80000000 20000000) + subfe. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfe. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfe. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfe. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfe. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfe. ffffffff, ffffffff => 00000000 (20000000 20000000) + + subfeo. 00000000, 00000000 => ffffffff (80000000 00000000) + subfeo. 00000000, 000f423f => 000f423e (40000000 20000000) + subfeo. 00000000, ffffffff => fffffffe (80000000 20000000) + subfeo. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + subfeo. 000f423f, 000f423f => ffffffff (80000000 00000000) + subfeo. 000f423f, ffffffff => fff0bdbf (80000000 20000000) + subfeo. ffffffff, 00000000 => 00000000 (20000000 00000000) + subfeo. ffffffff, 000f423f => 000f423f (40000000 00000000) + subfeo. ffffffff, ffffffff => ffffffff (80000000 00000000) + subfeo. 00000000, 00000000 => 00000000 (20000000 20000000) + subfeo. 00000000, 000f423f => 000f423f (40000000 20000000) + subfeo. 00000000, ffffffff => ffffffff (80000000 20000000) + subfeo. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfeo. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfeo. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfeo. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfeo. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfeo. ffffffff, ffffffff => 00000000 (20000000 20000000) + +PPC integer logical insns with two args: + and 00000000, 00000000 => 00000000 (00000000 00000000) + and 00000000, 000f423f => 00000000 (00000000 00000000) + and 00000000, ffffffff => 00000000 (00000000 00000000) + and 000f423f, 00000000 => 00000000 (00000000 00000000) + and 000f423f, 000f423f => 000f423f (00000000 00000000) + and 000f423f, ffffffff => 000f423f (00000000 00000000) + and ffffffff, 00000000 => 00000000 (00000000 00000000) + and ffffffff, 000f423f => 000f423f (00000000 00000000) + and ffffffff, ffffffff => ffffffff (00000000 00000000) + + andc 00000000, 00000000 => 00000000 (00000000 00000000) + andc 00000000, 000f423f => 00000000 (00000000 00000000) + andc 00000000, ffffffff => 00000000 (00000000 00000000) + andc 000f423f, 00000000 => 000f423f (00000000 00000000) + andc 000f423f, 000f423f => 00000000 (00000000 00000000) + andc 000f423f, ffffffff => 00000000 (00000000 00000000) + andc ffffffff, 00000000 => ffffffff (00000000 00000000) + andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + andc ffffffff, ffffffff => 00000000 (00000000 00000000) + + eqv 00000000, 00000000 => ffffffff (00000000 00000000) + eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000) + eqv 00000000, ffffffff => 00000000 (00000000 00000000) + eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + eqv 000f423f, 000f423f => ffffffff (00000000 00000000) + eqv 000f423f, ffffffff => 000f423f (00000000 00000000) + eqv ffffffff, 00000000 => 00000000 (00000000 00000000) + eqv ffffffff, 000f423f => 000f423f (00000000 00000000) + eqv ffffffff, ffffffff => ffffffff (00000000 00000000) + + nand 00000000, 00000000 => ffffffff (00000000 00000000) + nand 00000000, 000f423f => ffffffff (00000000 00000000) + nand 00000000, ffffffff => ffffffff (00000000 00000000) + nand 000f423f, 00000000 => ffffffff (00000000 00000000) + nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000) + nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + nand ffffffff, 00000000 => ffffffff (00000000 00000000) + nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + nand ffffffff, ffffffff => 00000000 (00000000 00000000) + + nor 00000000, 00000000 => ffffffff (00000000 00000000) + nor 00000000, 000f423f => fff0bdc0 (00000000 00000000) + nor 00000000, ffffffff => 00000000 (00000000 00000000) + nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000) + nor 000f423f, ffffffff => 00000000 (00000000 00000000) + nor ffffffff, 00000000 => 00000000 (00000000 00000000) + nor ffffffff, 000f423f => 00000000 (00000000 00000000) + nor ffffffff, ffffffff => 00000000 (00000000 00000000) + + or 00000000, 00000000 => 00000000 (00000000 00000000) + or 00000000, 000f423f => 000f423f (00000000 00000000) + or 00000000, ffffffff => ffffffff (00000000 00000000) + or 000f423f, 00000000 => 000f423f (00000000 00000000) + or 000f423f, 000f423f => 000f423f (00000000 00000000) + or 000f423f, ffffffff => ffffffff (00000000 00000000) + or ffffffff, 00000000 => ffffffff (00000000 00000000) + or ffffffff, 000f423f => ffffffff (00000000 00000000) + or ffffffff, ffffffff => ffffffff (00000000 00000000) + + orc 00000000, 00000000 => ffffffff (00000000 00000000) + orc 00000000, 000f423f => fff0bdc0 (00000000 00000000) + orc 00000000, ffffffff => 00000000 (00000000 00000000) + orc 000f423f, 00000000 => ffffffff (00000000 00000000) + orc 000f423f, 000f423f => ffffffff (00000000 00000000) + orc 000f423f, ffffffff => 000f423f (00000000 00000000) + orc ffffffff, 00000000 => ffffffff (00000000 00000000) + orc ffffffff, 000f423f => ffffffff (00000000 00000000) + orc ffffffff, ffffffff => ffffffff (00000000 00000000) + + xor 00000000, 00000000 => 00000000 (00000000 00000000) + xor 00000000, 000f423f => 000f423f (00000000 00000000) + xor 00000000, ffffffff => ffffffff (00000000 00000000) + xor 000f423f, 00000000 => 000f423f (00000000 00000000) + xor 000f423f, 000f423f => 00000000 (00000000 00000000) + xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + xor ffffffff, 00000000 => ffffffff (00000000 00000000) + xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + xor ffffffff, ffffffff => 00000000 (00000000 00000000) + + slw 00000000, 00000000 => 00000000 (00000000 00000000) + slw 00000000, 000f423f => 00000000 (00000000 00000000) + slw 00000000, ffffffff => 00000000 (00000000 00000000) + slw 000f423f, 00000000 => 000f423f (00000000 00000000) + slw 000f423f, 000f423f => 00000000 (00000000 00000000) + slw 000f423f, ffffffff => 00000000 (00000000 00000000) + slw ffffffff, 00000000 => ffffffff (00000000 00000000) + slw ffffffff, 000f423f => 00000000 (00000000 00000000) + slw ffffffff, ffffffff => 00000000 (00000000 00000000) + + sraw 00000000, 00000000 => 00000000 (00000000 00000000) + sraw 00000000, 000f423f => 00000000 (00000000 00000000) + sraw 00000000, ffffffff => 00000000 (00000000 00000000) + sraw 000f423f, 00000000 => 000f423f (00000000 00000000) + sraw 000f423f, 000f423f => 00000000 (00000000 00000000) + sraw 000f423f, ffffffff => 00000000 (00000000 00000000) + sraw ffffffff, 00000000 => ffffffff (00000000 00000000) + sraw ffffffff, 000f423f => ffffffff (00000000 20000000) + sraw ffffffff, ffffffff => ffffffff (00000000 20000000) + + srw 00000000, 00000000 => 00000000 (00000000 00000000) + srw 00000000, 000f423f => 00000000 (00000000 00000000) + srw 00000000, ffffffff => 00000000 (00000000 00000000) + srw 000f423f, 00000000 => 000f423f (00000000 00000000) + srw 000f423f, 000f423f => 00000000 (00000000 00000000) + srw 000f423f, ffffffff => 00000000 (00000000 00000000) + srw ffffffff, 00000000 => ffffffff (00000000 00000000) + srw ffffffff, 000f423f => 00000000 (00000000 00000000) + srw ffffffff, ffffffff => 00000000 (00000000 00000000) + +PPC integer logical insns with two args with flags update: + and. 00000000, 00000000 => 00000000 (20000000 00000000) + and. 00000000, 000f423f => 00000000 (20000000 00000000) + and. 00000000, ffffffff => 00000000 (20000000 00000000) + and. 000f423f, 00000000 => 00000000 (20000000 00000000) + and. 000f423f, 000f423f => 000f423f (40000000 00000000) + and. 000f423f, ffffffff => 000f423f (40000000 00000000) + and. ffffffff, 00000000 => 00000000 (20000000 00000000) + and. ffffffff, 000f423f => 000f423f (40000000 00000000) + and. ffffffff, ffffffff => ffffffff (80000000 00000000) + + andc. 00000000, 00000000 => 00000000 (20000000 00000000) + andc. 00000000, 000f423f => 00000000 (20000000 00000000) + andc. 00000000, ffffffff => 00000000 (20000000 00000000) + andc. 000f423f, 00000000 => 000f423f (40000000 00000000) + andc. 000f423f, 000f423f => 00000000 (20000000 00000000) + andc. 000f423f, ffffffff => 00000000 (20000000 00000000) + andc. ffffffff, 00000000 => ffffffff (80000000 00000000) + andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + andc. ffffffff, ffffffff => 00000000 (20000000 00000000) + + eqv. 00000000, 00000000 => ffffffff (80000000 00000000) + eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + eqv. 00000000, ffffffff => 00000000 (20000000 00000000) + eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + eqv. 000f423f, 000f423f => ffffffff (80000000 00000000) + eqv. 000f423f, ffffffff => 000f423f (40000000 00000000) + eqv. ffffffff, 00000000 => 00000000 (20000000 00000000) + eqv. ffffffff, 000f423f => 000f423f (40000000 00000000) + eqv. ffffffff, ffffffff => ffffffff (80000000 00000000) + + nand. 00000000, 00000000 => ffffffff (80000000 00000000) + nand. 00000000, 000f423f => ffffffff (80000000 00000000) + nand. 00000000, ffffffff => ffffffff (80000000 00000000) + nand. 000f423f, 00000000 => ffffffff (80000000 00000000) + nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000) + nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + nand. ffffffff, 00000000 => ffffffff (80000000 00000000) + nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + nand. ffffffff, ffffffff => 00000000 (20000000 00000000) + + nor. 00000000, 00000000 => ffffffff (80000000 00000000) + nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + nor. 00000000, ffffffff => 00000000 (20000000 00000000) + nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000) + nor. 000f423f, ffffffff => 00000000 (20000000 00000000) + nor. ffffffff, 00000000 => 00000000 (20000000 00000000) + nor. ffffffff, 000f423f => 00000000 (20000000 00000000) + nor. ffffffff, ffffffff => 00000000 (20000000 00000000) + + or. 00000000, 00000000 => 00000000 (20000000 00000000) + or. 00000000, 000f423f => 000f423f (40000000 00000000) + or. 00000000, ffffffff => ffffffff (80000000 00000000) + or. 000f423f, 00000000 => 000f423f (40000000 00000000) + or. 000f423f, 000f423f => 000f423f (40000000 00000000) + or. 000f423f, ffffffff => ffffffff (80000000 00000000) + or. ffffffff, 00000000 => ffffffff (80000000 00000000) + or. ffffffff, 000f423f => ffffffff (80000000 00000000) + or. ffffffff, ffffffff => ffffffff (80000000 00000000) + + orc. 00000000, 00000000 => ffffffff (80000000 00000000) + orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + orc. 00000000, ffffffff => 00000000 (20000000 00000000) + orc. 000f423f, 00000000 => ffffffff (80000000 00000000) + orc. 000f423f, 000f423f => ffffffff (80000000 00000000) + orc. 000f423f, ffffffff => 000f423f (40000000 00000000) + orc. ffffffff, 00000000 => ffffffff (80000000 00000000) + orc. ffffffff, 000f423f => ffffffff (80000000 00000000) + orc. ffffffff, ffffffff => ffffffff (80000000 00000000) + + xor. 00000000, 00000000 => 00000000 (20000000 00000000) + xor. 00000000, 000f423f => 000f423f (40000000 00000000) + xor. 00000000, ffffffff => ffffffff (80000000 00000000) + xor. 000f423f, 00000000 => 000f423f (40000000 00000000) + xor. 000f423f, 000f423f => 00000000 (20000000 00000000) + xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + xor. ffffffff, 00000000 => ffffffff (80000000 00000000) + xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + xor. ffffffff, ffffffff => 00000000 (20000000 00000000) + + slw. 00000000, 00000000 => 00000000 (20000000 00000000) + slw. 00000000, 000f423f => 00000000 (20000000 00000000) + slw. 00000000, ffffffff => 00000000 (20000000 00000000) + slw. 000f423f, 00000000 => 000f423f (40000000 00000000) + slw. 000f423f, 000f423f => 00000000 (20000000 00000000) + slw. 000f423f, ffffffff => 00000000 (20000000 00000000) + slw. ffffffff, 00000000 => ffffffff (80000000 00000000) + slw. ffffffff, 000f423f => 00000000 (20000000 00000000) + slw. ffffffff, ffffffff => 00000000 (20000000 00000000) + + sraw. 00000000, 00000000 => 00000000 (20000000 00000000) + sraw. 00000000, 000f423f => 00000000 (20000000 00000000) + sraw. 00000000, ffffffff => 00000000 (20000000 00000000) + sraw. 000f423f, 00000000 => 000f423f (40000000 00000000) + sraw. 000f423f, 000f423f => 00000000 (20000000 00000000) + sraw. 000f423f, ffffffff => 00000000 (20000000 00000000) + sraw. ffffffff, 00000000 => ffffffff (80000000 00000000) + sraw. ffffffff, 000f423f => ffffffff (80000000 20000000) + sraw. ffffffff, ffffffff => ffffffff (80000000 20000000) + + srw. 00000000, 00000000 => 00000000 (20000000 00000000) + srw. 00000000, 000f423f => 00000000 (20000000 00000000) + srw. 00000000, ffffffff => 00000000 (20000000 00000000) + srw. 000f423f, 00000000 => 000f423f (40000000 00000000) + srw. 000f423f, 000f423f => 00000000 (20000000 00000000) + srw. 000f423f, ffffffff => 00000000 (20000000 00000000) + srw. ffffffff, 00000000 => ffffffff (80000000 00000000) + srw. ffffffff, 000f423f => 00000000 (20000000 00000000) + srw. ffffffff, ffffffff => 00000000 (20000000 00000000) + +PPC integer compare insns (two args): + cmp 00000000, 00000000 => 00000000 (00200000 00000000) + cmp 00000000, 000f423f => 00000000 (00800000 00000000) + cmp 00000000, ffffffff => 00000000 (00400000 00000000) + cmp 000f423f, 00000000 => 00000000 (00400000 00000000) + cmp 000f423f, 000f423f => 00000000 (00200000 00000000) + cmp 000f423f, ffffffff => 00000000 (00400000 00000000) + cmp ffffffff, 00000000 => 00000000 (00800000 00000000) + cmp ffffffff, 000f423f => 00000000 (00800000 00000000) + cmp ffffffff, ffffffff => 00000000 (00200000 00000000) + + cmpl 00000000, 00000000 => 00000000 (00200000 00000000) + cmpl 00000000, 000f423f => 00000000 (00800000 00000000) + cmpl 00000000, ffffffff => 00000000 (00800000 00000000) + cmpl 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpl 000f423f, 000f423f => 00000000 (00200000 00000000) + cmpl 000f423f, ffffffff => 00000000 (00800000 00000000) + cmpl ffffffff, 00000000 => 00000000 (00400000 00000000) + cmpl ffffffff, 000f423f => 00000000 (00400000 00000000) + cmpl ffffffff, ffffffff => 00000000 (00200000 00000000) + +PPC integer compare with immediate insns (two args): + cmpi 00000000, 00000000 => 00000000 (00200000 00000000) + cmpi 00000000, 000003e7 => 00000000 (00800000 00000000) + cmpi 00000000, 0000ffff => 00000000 (00400000 00000000) + cmpi 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpi 000f423f, 000003e7 => 00000000 (00400000 00000000) + cmpi 000f423f, 0000ffff => 00000000 (00400000 00000000) + cmpi ffffffff, 00000000 => 00000000 (00800000 00000000) + cmpi ffffffff, 000003e7 => 00000000 (00800000 00000000) + cmpi ffffffff, 0000ffff => 00000000 (00200000 00000000) + + cmpli 00000000, 00000000 => 00000000 (00200000 00000000) + cmpli 00000000, 000003e7 => 00000000 (00800000 00000000) + cmpli 00000000, 0000ffff => 00000000 (00800000 00000000) + cmpli 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpli 000f423f, 000003e7 => 00000000 (00400000 00000000) + cmpli 000f423f, 0000ffff => 00000000 (00400000 00000000) + cmpli ffffffff, 00000000 => 00000000 (00400000 00000000) + cmpli ffffffff, 000003e7 => 00000000 (00400000 00000000) + cmpli ffffffff, 0000ffff => 00000000 (00400000 00000000) + +PPC integer arith insns + with one register + one 16 bits immediate args: + addi 00000000, 00000000 => 00000000 (00000000 00000000) + addi 00000000, 000003e7 => 000003e7 (00000000 00000000) + addi 00000000, 0000ffff => ffffffff (00000000 00000000) + addi 000f423f, 00000000 => 000f423f (00000000 00000000) + addi 000f423f, 000003e7 => 000f4626 (00000000 00000000) + addi 000f423f, 0000ffff => 000f423e (00000000 00000000) + addi ffffffff, 00000000 => ffffffff (00000000 00000000) + addi ffffffff, 000003e7 => 000003e6 (00000000 00000000) + addi ffffffff, 0000ffff => fffffffe (00000000 00000000) + + addic 00000000, 00000000 => 00000000 (00000000 00000000) + addic 00000000, 000003e7 => 000003e7 (00000000 00000000) + addic 00000000, 0000ffff => ffffffff (00000000 00000000) + addic 000f423f, 00000000 => 000f423f (00000000 00000000) + addic 000f423f, 000003e7 => 000f4626 (00000000 00000000) + addic 000f423f, 0000ffff => 000f423e (00000000 20000000) + addic ffffffff, 00000000 => ffffffff (00000000 00000000) + addic ffffffff, 000003e7 => 000003e6 (00000000 20000000) + addic ffffffff, 0000ffff => fffffffe (00000000 20000000) + + addis 00000000, 00000000 => 00000000 (00000000 00000000) + addis 00000000, 000003e7 => 03e70000 (00000000 00000000) + addis 00000000, 0000ffff => ffff0000 (00000000 00000000) + addis 000f423f, 00000000 => 000f423f (00000000 00000000) + addis 000f423f, 000003e7 => 03f6423f (00000000 00000000) + addis 000f423f, 0000ffff => 000e423f (00000000 00000000) + addis ffffffff, 00000000 => ffffffff (00000000 00000000) + addis ffffffff, 000003e7 => 03e6ffff (00000000 00000000) + addis ffffffff, 0000ffff => fffeffff (00000000 00000000) + + mulli 00000000, 00000000 => 00000000 (00000000 00000000) + mulli 00000000, 000003e7 => 00000000 (00000000 00000000) + mulli 00000000, 0000ffff => 00000000 (00000000 00000000) + mulli 000f423f, 00000000 => 00000000 (00000000 00000000) + mulli 000f423f, 000003e7 => 3b8b83d9 (00000000 00000000) + mulli 000f423f, 0000ffff => fff0bdc1 (00000000 00000000) + mulli ffffffff, 00000000 => 00000000 (00000000 00000000) + mulli ffffffff, 000003e7 => fffffc19 (00000000 00000000) + mulli ffffffff, 0000ffff => 00000001 (00000000 00000000) + + subfic 00000000, 00000000 => 00000000 (00000000 20000000) + subfic 00000000, 000003e7 => 000003e7 (00000000 20000000) + subfic 00000000, 0000ffff => ffffffff (00000000 20000000) + subfic 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfic 000f423f, 000003e7 => fff0c1a8 (00000000 00000000) + subfic 000f423f, 0000ffff => fff0bdc0 (00000000 20000000) + subfic ffffffff, 00000000 => 00000001 (00000000 00000000) + subfic ffffffff, 000003e7 => 000003e8 (00000000 00000000) + subfic ffffffff, 0000ffff => 00000000 (00000000 20000000) + +PPC integer arith insns + with one register + one 16 bits immediate args with flags update: + addic. 00000000, 00000000 => 00000000 (20000000 00000000) + addic. 00000000, 000003e7 => 000003e7 (40000000 00000000) + addic. 00000000, 0000ffff => ffffffff (80000000 00000000) + addic. 000f423f, 00000000 => 000f423f (40000000 00000000) + addic. 000f423f, 000003e7 => 000f4626 (40000000 00000000) + addic. 000f423f, 0000ffff => 000f423e (40000000 20000000) + addic. ffffffff, 00000000 => ffffffff (80000000 00000000) + addic. ffffffff, 000003e7 => 000003e6 (40000000 20000000) + addic. ffffffff, 0000ffff => fffffffe (80000000 20000000) + +PPC integer logical insns + with one register + one 16 bits immediate args: + ori 00000000, 00000000 => 00000000 (00000000 00000000) + ori 00000000, 000003e7 => 000003e7 (00000000 00000000) + ori 00000000, 0000ffff => 0000ffff (00000000 00000000) + ori 000f423f, 00000000 => 000f423f (00000000 00000000) + ori 000f423f, 000003e7 => 000f43ff (00000000 00000000) + ori 000f423f, 0000ffff => 000fffff (00000000 00000000) + ori ffffffff, 00000000 => ffffffff (00000000 00000000) + ori ffffffff, 000003e7 => ffffffff (00000000 00000000) + ori ffffffff, 0000ffff => ffffffff (00000000 00000000) + + oris 00000000, 00000000 => 00000000 (00000000 00000000) + oris 00000000, 000003e7 => 03e70000 (00000000 00000000) + oris 00000000, 0000ffff => ffff0000 (00000000 00000000) + oris 000f423f, 00000000 => 000f423f (00000000 00000000) + oris 000f423f, 000003e7 => 03ef423f (00000000 00000000) + oris 000f423f, 0000ffff => ffff423f (00000000 00000000) + oris ffffffff, 00000000 => ffffffff (00000000 00000000) + oris ffffffff, 000003e7 => ffffffff (00000000 00000000) + oris ffffffff, 0000ffff => ffffffff (00000000 00000000) + + xori 00000000, 00000000 => 00000000 (00000000 00000000) + xori 00000000, 000003e7 => 000003e7 (00000000 00000000) + xori 00000000, 0000ffff => 0000ffff (00000000 00000000) + xori 000f423f, 00000000 => 000f423f (00000000 00000000) + xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000) + xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000) + xori ffffffff, 00000000 => ffffffff (00000000 00000000) + xori ffffffff, 000003e7 => fffffc18 (00000000 00000000) + xori ffffffff, 0000ffff => ffff0000 (00000000 00000000) + + xoris 00000000, 00000000 => 00000000 (00000000 00000000) + xoris 00000000, 000003e7 => 03e70000 (00000000 00000000) + xoris 00000000, 0000ffff => ffff0000 (00000000 00000000) + xoris 000f423f, 00000000 => 000f423f (00000000 00000000) + xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000) + xoris 000f423f, 0000ffff => fff0423f (00000000 00000000) + xoris ffffffff, 00000000 => ffffffff (00000000 00000000) + xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000) + xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000) + +PPC integer logical insns + with one register + one 16 bits immediate args with flags update: + andi. 00000000, 00000000 => 00000000 (20000000 00000000) + andi. 00000000, 000003e7 => 00000000 (20000000 00000000) + andi. 00000000, 0000ffff => 00000000 (20000000 00000000) + andi. 000f423f, 00000000 => 00000000 (20000000 00000000) + andi. 000f423f, 000003e7 => 00000227 (40000000 00000000) + andi. 000f423f, 0000ffff => 0000423f (40000000 00000000) + andi. ffffffff, 00000000 => 00000000 (20000000 00000000) + andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000) + andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000) + + andis. 00000000, 00000000 => 00000000 (20000000 00000000) + andis. 00000000, 000003e7 => 00000000 (20000000 00000000) + andis. 00000000, 0000ffff => 00000000 (20000000 00000000) + andis. 000f423f, 00000000 => 00000000 (20000000 00000000) + andis. 000f423f, 000003e7 => 00070000 (40000000 00000000) + andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000) + andis. ffffffff, 00000000 => 00000000 (20000000 00000000) + andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000) + andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000) + +PPC condition register logical insns - two operands: + crand 00000000, 00000000 => ffff0000 (00000000 00000000) + crand 00000000, 000f423f => ffff0000 (00000000 00000000) + crand 00000000, ffffffff => ffff0000 (00000000 00000000) + crand 000f423f, 00000000 => ffff0000 (00000000 00000000) + crand 000f423f, 000f423f => ffff0000 (00000000 00000000) + crand 000f423f, ffffffff => ffff0000 (00000000 00000000) + crand ffffffff, 00000000 => ffff0000 (00000000 00000000) + crand ffffffff, 000f423f => ffff0000 (00000000 00000000) + crand ffffffff, ffffffff => ffff0000 (00000000 00000000) + + crandc 00000000, 00000000 => ffff0000 (00000000 00000000) + crandc 00000000, 000f423f => ffff0000 (00000000 00000000) + crandc 00000000, ffffffff => ffff0000 (00000000 00000000) + crandc 000f423f, 00000000 => ffff0000 (00000000 00000000) + crandc 000f423f, 000f423f => ffff0000 (00000000 00000000) + crandc 000f423f, ffffffff => ffff0000 (00000000 00000000) + crandc ffffffff, 00000000 => ffff0000 (00000000 00000000) + crandc ffffffff, 000f423f => ffff0000 (00000000 00000000) + crandc ffffffff, ffffffff => ffff0000 (00000000 00000000) + + creqv 00000000, 00000000 => ffff0000 (00004000 00000000) + creqv 00000000, 000f423f => ffff0000 (00004000 00000000) + creqv 00000000, ffffffff => ffff0000 (00004000 00000000) + creqv 000f423f, 00000000 => ffff0000 (00004000 00000000) + creqv 000f423f, 000f423f => ffff0000 (00004000 00000000) + creqv 000f423f, ffffffff => ffff0000 (00004000 00000000) + creqv ffffffff, 00000000 => ffff0000 (00004000 00000000) + creqv ffffffff, 000f423f => ffff0000 (00004000 00000000) + creqv ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crnand 00000000, 00000000 => ffff0000 (00004000 00000000) + crnand 00000000, 000f423f => ffff0000 (00004000 00000000) + crnand 00000000, ffffffff => ffff0000 (00004000 00000000) + crnand 000f423f, 00000000 => ffff0000 (00004000 00000000) + crnand 000f423f, 000f423f => ffff0000 (00004000 00000000) + crnand 000f423f, ffffffff => ffff0000 (00004000 00000000) + crnand ffffffff, 00000000 => ffff0000 (00004000 00000000) + crnand ffffffff, 000f423f => ffff0000 (00004000 00000000) + crnand ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crnor 00000000, 00000000 => ffff0000 (00004000 00000000) + crnor 00000000, 000f423f => ffff0000 (00004000 00000000) + crnor 00000000, ffffffff => ffff0000 (00004000 00000000) + crnor 000f423f, 00000000 => ffff0000 (00004000 00000000) + crnor 000f423f, 000f423f => ffff0000 (00004000 00000000) + crnor 000f423f, ffffffff => ffff0000 (00004000 00000000) + crnor ffffffff, 00000000 => ffff0000 (00004000 00000000) + crnor ffffffff, 000f423f => ffff0000 (00004000 00000000) + crnor ffffffff, ffffffff => ffff0000 (00004000 00000000) + + cror 00000000, 00000000 => ffff0000 (00000000 00000000) + cror 00000000, 000f423f => ffff0000 (00000000 00000000) + cror 00000000, ffffffff => ffff0000 (00000000 00000000) + cror 000f423f, 00000000 => ffff0000 (00000000 00000000) + cror 000f423f, 000f423f => ffff0000 (00000000 00000000) + cror 000f423f, ffffffff => ffff0000 (00000000 00000000) + cror ffffffff, 00000000 => ffff0000 (00000000 00000000) + cror ffffffff, 000f423f => ffff0000 (00000000 00000000) + cror ffffffff, ffffffff => ffff0000 (00000000 00000000) + + crorc 00000000, 00000000 => ffff0000 (00004000 00000000) + crorc 00000000, 000f423f => ffff0000 (00004000 00000000) + crorc 00000000, ffffffff => ffff0000 (00004000 00000000) + crorc 000f423f, 00000000 => ffff0000 (00004000 00000000) + crorc 000f423f, 000f423f => ffff0000 (00004000 00000000) + crorc 000f423f, ffffffff => ffff0000 (00004000 00000000) + crorc ffffffff, 00000000 => ffff0000 (00004000 00000000) + crorc ffffffff, 000f423f => ffff0000 (00004000 00000000) + crorc ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crxor 00000000, 00000000 => ffff0000 (00000000 00000000) + crxor 00000000, 000f423f => ffff0000 (00000000 00000000) + crxor 00000000, ffffffff => ffff0000 (00000000 00000000) + crxor 000f423f, 00000000 => ffff0000 (00000000 00000000) + crxor 000f423f, 000f423f => ffff0000 (00000000 00000000) + crxor 000f423f, ffffffff => ffff0000 (00000000 00000000) + crxor ffffffff, 00000000 => ffff0000 (00000000 00000000) + crxor ffffffff, 000f423f => ffff0000 (00000000 00000000) + crxor ffffffff, ffffffff => ffff0000 (00000000 00000000) + +PPC integer arith insns with one arg and carry: + addme 00000000 => ffffffff (00000000 00000000) + addme 000f423f => 000f423e (00000000 20000000) + addme ffffffff => fffffffe (00000000 20000000) + addme 00000000 => 00000000 (00000000 20000000) + addme 000f423f => 000f423f (00000000 20000000) + addme ffffffff => ffffffff (00000000 20000000) + + addmeo 00000000 => ffffffff (00000000 00000000) + addmeo 000f423f => 000f423e (00000000 20000000) + addmeo ffffffff => fffffffe (00000000 20000000) + addmeo 00000000 => 00000000 (00000000 20000000) + addmeo 000f423f => 000f423f (00000000 20000000) + addmeo ffffffff => ffffffff (00000000 20000000) + + addze 00000000 => 00000000 (00000000 00000000) + addze 000f423f => 000f423f (00000000 00000000) + addze ffffffff => ffffffff (00000000 00000000) + addze 00000000 => 00000001 (00000000 00000000) + addze 000f423f => 000f4240 (00000000 00000000) + addze ffffffff => 00000000 (00000000 20000000) + + addzeo 00000000 => 00000000 (00000000 00000000) + addzeo 000f423f => 000f423f (00000000 00000000) + addzeo ffffffff => ffffffff (00000000 00000000) + addzeo 00000000 => 00000001 (00000000 00000000) + addzeo 000f423f => 000f4240 (00000000 00000000) + addzeo ffffffff => 00000000 (00000000 20000000) + + subfme 00000000 => fffffffe (00000000 20000000) + subfme 000f423f => fff0bdbf (00000000 20000000) + subfme ffffffff => ffffffff (00000000 00000000) + subfme 00000000 => ffffffff (00000000 20000000) + subfme 000f423f => fff0bdc0 (00000000 20000000) + subfme ffffffff => 00000000 (00000000 20000000) + + subfmeo 00000000 => fffffffe (00000000 20000000) + subfmeo 000f423f => fff0bdbf (00000000 20000000) + subfmeo ffffffff => ffffffff (00000000 00000000) + subfmeo 00000000 => ffffffff (00000000 20000000) + subfmeo 000f423f => fff0bdc0 (00000000 20000000) + subfmeo ffffffff => 00000000 (00000000 20000000) + + subfze 00000000 => ffffffff (00000000 00000000) + subfze 000f423f => fff0bdc0 (00000000 00000000) + subfze ffffffff => 00000000 (00000000 00000000) + subfze 00000000 => 00000000 (00000000 20000000) + subfze 000f423f => fff0bdc1 (00000000 00000000) + subfze ffffffff => 00000001 (00000000 00000000) + + subfzeo 00000000 => ffffffff (00000000 00000000) + subfzeo 000f423f => fff0bdc0 (00000000 00000000) + subfzeo ffffffff => 00000000 (00000000 00000000) + subfzeo 00000000 => 00000000 (00000000 20000000) + subfzeo 000f423f => fff0bdc1 (00000000 00000000) + subfzeo ffffffff => 00000001 (00000000 00000000) + +PPC integer arith insns with one arg and carry with flags update: + addme. 00000000 => ffffffff (80000000 00000000) + addme. 000f423f => 000f423e (40000000 20000000) + addme. ffffffff => fffffffe (80000000 20000000) + addme. 00000000 => 00000000 (20000000 20000000) + addme. 000f423f => 000f423f (40000000 20000000) + addme. ffffffff => ffffffff (80000000 20000000) + + addmeo. 00000000 => ffffffff (80000000 00000000) + addmeo. 000f423f => 000f423e (40000000 20000000) + addmeo. ffffffff => fffffffe (80000000 20000000) + addmeo. 00000000 => 00000000 (20000000 20000000) + addmeo. 000f423f => 000f423f (40000000 20000000) + addmeo. ffffffff => ffffffff (80000000 20000000) + + addze. 00000000 => 00000000 (20000000 00000000) + addze. 000f423f => 000f423f (40000000 00000000) + addze. ffffffff => ffffffff (80000000 00000000) + addze. 00000000 => 00000001 (40000000 00000000) + addze. 000f423f => 000f4240 (40000000 00000000) + addze. ffffffff => 00000000 (20000000 20000000) + + addzeo. 00000000 => 00000000 (20000000 00000000) + addzeo. 000f423f => 000f423f (40000000 00000000) + addzeo. ffffffff => ffffffff (80000000 00000000) + addzeo. 00000000 => 00000001 (40000000 00000000) + addzeo. 000f423f => 000f4240 (40000000 00000000) + addzeo. ffffffff => 00000000 (20000000 20000000) + + subfme. 00000000 => fffffffe (80000000 20000000) + subfme. 000f423f => fff0bdbf (80000000 20000000) + subfme. ffffffff => ffffffff (80000000 00000000) + subfme. 00000000 => ffffffff (80000000 20000000) + subfme. 000f423f => fff0bdc0 (80000000 20000000) + subfme. ffffffff => 00000000 (20000000 20000000) + + subfmeo. 00000000 => fffffffe (80000000 20000000) + subfmeo. 000f423f => fff0bdbf (80000000 20000000) + subfmeo. ffffffff => ffffffff (80000000 00000000) + subfmeo. 00000000 => ffffffff (80000000 20000000) + subfmeo. 000f423f => fff0bdc0 (80000000 20000000) + subfmeo. ffffffff => 00000000 (20000000 20000000) + + subfze. 00000000 => ffffffff (80000000 00000000) + subfze. 000f423f => fff0bdc0 (80000000 00000000) + subfze. ffffffff => 00000000 (20000000 00000000) + subfze. 00000000 => 00000000 (20000000 20000000) + subfze. 000f423f => fff0bdc1 (80000000 00000000) + subfze. ffffffff => 00000001 (40000000 00000000) + + subfzeo. 00000000 => ffffffff (80000000 00000000) + subfzeo. 000f423f => fff0bdc0 (80000000 00000000) + subfzeo. ffffffff => 00000000 (20000000 00000000) + subfzeo. 00000000 => 00000000 (20000000 20000000) + subfzeo. 000f423f => fff0bdc1 (80000000 00000000) + subfzeo. ffffffff => 00000001 (40000000 00000000) + +PPC integer logical insns with one arg: + cntlzw 00000000 => 00000020 (00000000 00000000) + cntlzw 000f423f => 0000000c (00000000 00000000) + cntlzw ffffffff => 00000000 (00000000 00000000) + + extsb 00000000 => 00000000 (00000000 00000000) + extsb 000f423f => 0000003f (00000000 00000000) + extsb ffffffff => ffffffff (00000000 00000000) + + extsh 00000000 => 00000000 (00000000 00000000) + extsh 000f423f => 0000423f (00000000 00000000) + extsh ffffffff => ffffffff (00000000 00000000) + + neg 00000000 => 00000000 (00000000 00000000) + neg 000f423f => fff0bdc1 (00000000 00000000) + neg ffffffff => 00000001 (00000000 00000000) + + nego 00000000 => 00000000 (00000000 00000000) + nego 000f423f => fff0bdc1 (00000000 00000000) + nego ffffffff => 00000001 (00000000 00000000) + +PPC integer logical insns with one arg with flags update: + cntlzw. 00000000 => 00000020 (40000000 00000000) + cntlzw. 000f423f => 0000000c (40000000 00000000) + cntlzw. ffffffff => 00000000 (20000000 00000000) + + extsb. 00000000 => 00000000 (20000000 00000000) + extsb. 000f423f => 0000003f (40000000 00000000) + extsb. ffffffff => ffffffff (80000000 00000000) + + extsh. 00000000 => 00000000 (20000000 00000000) + extsh. 000f423f => 0000423f (40000000 00000000) + extsh. ffffffff => ffffffff (80000000 00000000) + + neg. 00000000 => 00000000 (20000000 00000000) + neg. 000f423f => fff0bdc1 (80000000 00000000) + neg. ffffffff => 00000001 (40000000 00000000) + + nego. 00000000 => 00000000 (20000000 00000000) + nego. 000f423f => fff0bdc1 (80000000 00000000) + nego. ffffffff => 00000001 (40000000 00000000) + +PPC logical insns with special forms: + rlwimi 00000000, 0, 0, 0 => 00000001 (00000000 00000000) + rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000) + rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000) + rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000) + rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000) + rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000) + rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000) + rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000) + rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000) + rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000) + rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000) + rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000) + + rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000) + rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000) + rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000) + rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000) + rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000) + rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000) + rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000) + rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000) + rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000) + rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000) + rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000) + rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000) + rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000) + rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000) + rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000) + rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000) + rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000) + + rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000) + rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000) + rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000) + rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000) + rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000) + rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000) + rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000) + rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000) + rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000) + rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000) + rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000) + rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000) + rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000) + + srawi 00000000, 0 => 00000000 (00000000 00000000) + srawi 00000000, 31 => 00000000 (00000000 00000000) + srawi 000f423f, 0 => 000f423f (00000000 00000000) + srawi 000f423f, 31 => 00000000 (00000000 00000000) + srawi ffffffff, 0 => ffffffff (00000000 00000000) + srawi ffffffff, 31 => ffffffff (00000000 20000000) + + mfcr (00000000) => 00000000 (00000000 00000000) + mfcr (000f423f) => 000f423f (000f423f 00000000) + mfcr (ffffffff) => ffffffff (ffffffff 00000000) + + mfspr 1 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 1 (000f423f) => 0000003f (00000000 0000003f, 00000000, 00000000) + mfspr 1 (ffffffff) => e000007f (00000000 e000007f, 00000000, 00000000) + mfspr 8 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 8 (000f423f) => 000f423f (00000000 00000000, 000f423f, 00000000) + mfspr 8 (ffffffff) => ffffffff (00000000 00000000, ffffffff, 00000000) + mfspr 9 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 9 (000f423f) => 000f423f (00000000 00000000, 00000000, 000f423f) + mfspr 9 (ffffffff) => ffffffff (00000000 00000000, 00000000, ffffffff) + + mtspr 1, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 1, 000f423f => (00000000 0000003f, 00000000, 00000000) + mtspr 1, ffffffff => (00000000 e000007f, 00000000, 00000000) + mtspr 8, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 8, 000f423f => (00000000 00000000, 000f423f, 00000000) + mtspr 8, ffffffff => (00000000 00000000, ffffffff, 00000000) + mtspr 9, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 9, 000f423f => (00000000 00000000, 00000000, 000f423f) + mtspr 9, ffffffff => (00000000 00000000, 00000000, ffffffff) + +PPC logical insns with special forms with flags update: + rlwimi. 00000000, 0, 0, 0 => 7fffffff (40000000 00000000) + rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000) + rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000) + rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000) + rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000) + rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000) + rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000) + rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000) + rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000) + + rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000) + rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000) + rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000) + rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000) + rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000) + rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000) + rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000) + rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000) + rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000) + rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000) + rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000) + rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000) + rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000) + rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000) + rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000) + rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000) + + rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000) + rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000) + rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000) + rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000) + rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000) + rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000) + rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000) + rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000) + rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000) + rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000) + rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000) + + srawi. 00000000, 0 => 00000000 (20000000 00000000) + srawi. 00000000, 31 => 00000000 (20000000 00000000) + srawi. 000f423f, 0 => 000f423f (40000000 00000000) + srawi. 000f423f, 31 => 00000000 (20000000 00000000) + srawi. ffffffff, 0 => ffffffff (80000000 00000000) + srawi. ffffffff, 31 => ffffffff (80000000 20000000) + + mcrf 0, 0 (00000000) => (00000000 00000000) + mcrf 0, 7 (00000000) => (00000000 00000000) + mcrf 7, 0 (00000000) => (00000000 00000000) + mcrf 7, 7 (00000000) => (00000000 00000000) + mcrf 0, 0 (000f423f) => (000f423f 00000000) + mcrf 0, 7 (000f423f) => (f00f423f 00000000) + mcrf 7, 0 (000f423f) => (000f4230 00000000) + mcrf 7, 7 (000f423f) => (000f423f 00000000) + mcrf 0, 0 (ffffffff) => (ffffffff 00000000) + mcrf 0, 7 (ffffffff) => (ffffffff 00000000) + mcrf 7, 0 (ffffffff) => (ffffffff 00000000) + mcrf 7, 7 (ffffffff) => (ffffffff 00000000) + + mcrxr 0 (00000000) => (00000000 00000000) + mcrxr 1 (00000000) => (00000000 00000000) + mcrxr 2 (00000000) => (00000000 00000000) + mcrxr 3 (00000000) => (00000000 00000000) + mcrxr 4 (00000000) => (00000000 00000000) + mcrxr 5 (00000000) => (00000000 00000000) + mcrxr 6 (00000000) => (00000000 00000000) + mcrxr 7 (00000000) => (00000000 00000000) + mcrxr 0 (10000000) => (00000000 00000000) + mcrxr 1 (10000000) => (00000000 00000000) + mcrxr 2 (10000000) => (00000000 00000000) + mcrxr 3 (10000000) => (00000000 00000000) + mcrxr 4 (10000000) => (00000000 00000000) + mcrxr 5 (10000000) => (00000000 00000000) + mcrxr 6 (10000000) => (00000000 00000000) + mcrxr 7 (10000000) => (00000000 00000000) + mcrxr 0 (20000000) => (20000000 00000000) + mcrxr 1 (20000000) => (02000000 00000000) + mcrxr 2 (20000000) => (00200000 00000000) + mcrxr 3 (20000000) => (00020000 00000000) + mcrxr 4 (20000000) => (00002000 00000000) + mcrxr 5 (20000000) => (00000200 00000000) + mcrxr 6 (20000000) => (00000020 00000000) + mcrxr 7 (20000000) => (00000002 00000000) + mcrxr 0 (30000000) => (20000000 00000000) + mcrxr 1 (30000000) => (02000000 00000000) + mcrxr 2 (30000000) => (00200000 00000000) + mcrxr 3 (30000000) => (00020000 00000000) + mcrxr 4 (30000000) => (00002000 00000000) + mcrxr 5 (30000000) => (00000200 00000000) + mcrxr 6 (30000000) => (00000020 00000000) + mcrxr 7 (30000000) => (00000002 00000000) + mcrxr 0 (40000000) => (40000000 00000000) + mcrxr 1 (40000000) => (04000000 00000000) + mcrxr 2 (40000000) => (00400000 00000000) + mcrxr 3 (40000000) => (00040000 00000000) + mcrxr 4 (40000000) => (00004000 00000000) + mcrxr 5 (40000000) => (00000400 00000000) + mcrxr 6 (40000000) => (00000040 00000000) + mcrxr 7 (40000000) => (00000004 00000000) + mcrxr 0 (50000000) => (40000000 00000000) + mcrxr 1 (50000000) => (04000000 00000000) + mcrxr 2 (50000000) => (00400000 00000000) + mcrxr 3 (50000000) => (00040000 00000000) + mcrxr 4 (50000000) => (00004000 00000000) + mcrxr 5 (50000000) => (00000400 00000000) + mcrxr 6 (50000000) => (00000040 00000000) + mcrxr 7 (50000000) => (00000004 00000000) + mcrxr 0 (60000000) => (60000000 00000000) + mcrxr 1 (60000000) => (06000000 00000000) + mcrxr 2 (60000000) => (00600000 00000000) + mcrxr 3 (60000000) => (00060000 00000000) + mcrxr 4 (60000000) => (00006000 00000000) + mcrxr 5 (60000000) => (00000600 00000000) + mcrxr 6 (60000000) => (00000060 00000000) + mcrxr 7 (60000000) => (00000006 00000000) + mcrxr 0 (70000000) => (60000000 00000000) + mcrxr 1 (70000000) => (06000000 00000000) + mcrxr 2 (70000000) => (00600000 00000000) + mcrxr 3 (70000000) => (00060000 00000000) + mcrxr 4 (70000000) => (00006000 00000000) + mcrxr 5 (70000000) => (00000600 00000000) + mcrxr 6 (70000000) => (00000060 00000000) + mcrxr 7 (70000000) => (00000006 00000000) + mcrxr 0 (80000000) => (80000000 00000000) + mcrxr 1 (80000000) => (08000000 00000000) + mcrxr 2 (80000000) => (00800000 00000000) + mcrxr 3 (80000000) => (00080000 00000000) + mcrxr 4 (80000000) => (00008000 00000000) + mcrxr 5 (80000000) => (00000800 00000000) + mcrxr 6 (80000000) => (00000080 00000000) + mcrxr 7 (80000000) => (00000008 00000000) + mcrxr 0 (90000000) => (80000000 00000000) + mcrxr 1 (90000000) => (08000000 00000000) + mcrxr 2 (90000000) => (00800000 00000000) + mcrxr 3 (90000000) => (00080000 00000000) + mcrxr 4 (90000000) => (00008000 00000000) + mcrxr 5 (90000000) => (00000800 00000000) + mcrxr 6 (90000000) => (00000080 00000000) + mcrxr 7 (90000000) => (00000008 00000000) + mcrxr 0 (a0000000) => (a0000000 00000000) + mcrxr 1 (a0000000) => (0a000000 00000000) + mcrxr 2 (a0000000) => (00a00000 00000000) + mcrxr 3 (a0000000) => (000a0000 00000000) + mcrxr 4 (a0000000) => (0000a000 00000000) + mcrxr 5 (a0000000) => (00000a00 00000000) + mcrxr 6 (a0000000) => (000000a0 00000000) + mcrxr 7 (a0000000) => (0000000a 00000000) + mcrxr 0 (b0000000) => (a0000000 00000000) + mcrxr 1 (b0000000) => (0a000000 00000000) + mcrxr 2 (b0000000) => (00a00000 00000000) + mcrxr 3 (b0000000) => (000a0000 00000000) + mcrxr 4 (b0000000) => (0000a000 00000000) + mcrxr 5 (b0000000) => (00000a00 00000000) + mcrxr 6 (b0000000) => (000000a0 00000000) + mcrxr 7 (b0000000) => (0000000a 00000000) + mcrxr 0 (c0000000) => (c0000000 00000000) + mcrxr 1 (c0000000) => (0c000000 00000000) + mcrxr 2 (c0000000) => (00c00000 00000000) + mcrxr 3 (c0000000) => (000c0000 00000000) + mcrxr 4 (c0000000) => (0000c000 00000000) + mcrxr 5 (c0000000) => (00000c00 00000000) + mcrxr 6 (c0000000) => (000000c0 00000000) + mcrxr 7 (c0000000) => (0000000c 00000000) + mcrxr 0 (d0000000) => (c0000000 00000000) + mcrxr 1 (d0000000) => (0c000000 00000000) + mcrxr 2 (d0000000) => (00c00000 00000000) + mcrxr 3 (d0000000) => (000c0000 00000000) + mcrxr 4 (d0000000) => (0000c000 00000000) + mcrxr 5 (d0000000) => (00000c00 00000000) + mcrxr 6 (d0000000) => (000000c0 00000000) + mcrxr 7 (d0000000) => (0000000c 00000000) + mcrxr 0 (e0000000) => (e0000000 00000000) + mcrxr 1 (e0000000) => (0e000000 00000000) + mcrxr 2 (e0000000) => (00e00000 00000000) + mcrxr 3 (e0000000) => (000e0000 00000000) + mcrxr 4 (e0000000) => (0000e000 00000000) + mcrxr 5 (e0000000) => (00000e00 00000000) + mcrxr 6 (e0000000) => (000000e0 00000000) + mcrxr 7 (e0000000) => (0000000e 00000000) + mcrxr 0 (f0000000) => (e0000000 00000000) + mcrxr 1 (f0000000) => (0e000000 00000000) + mcrxr 2 (f0000000) => (00e00000 00000000) + mcrxr 3 (f0000000) => (000e0000 00000000) + mcrxr 4 (f0000000) => (0000e000 00000000) + mcrxr 5 (f0000000) => (00000e00 00000000) + mcrxr 6 (f0000000) => (000000e0 00000000) + mcrxr 7 (f0000000) => (0000000e 00000000) + + mtcrf 0, 00000000 => (00000000 00000000) + mtcrf 99, 00000000 => (00000000 00000000) + mtcrf 198, 00000000 => (00000000 00000000) + mtcrf 0, 000f423f => (00000000 00000000) + mtcrf 99, 000f423f => (0000003f 00000000) + mtcrf 198, 000f423f => (00000230 00000000) + mtcrf 0, ffffffff => (00000000 00000000) + mtcrf 99, ffffffff => (0ff000ff 00000000) + mtcrf 198, ffffffff => (ff000ff0 00000000) + +PPC integer load insns + with one register + one 16 bits immediate args with flags update: + lbz 0, (00000000) => 00000000, (00000000 00000000) + lbz 4, (000f423f) => 00000000, (00000000 00000000) + lbz 8, (ffffffff) => 000000ff, (00000000 00000000) + lbz -8, (00000000) => 00000000 (00000000 00000000) + lbz -4, (000f423f) => 00000000 (00000000 00000000) + lbz 0, (ffffffff) => 000000ff (00000000 00000000) + + lbzu 0, (00000000) => 00000000, (00000000 00000000) + lbzu 4, (000f423f) => 00000000, (00000000 00000000) + lbzu 8, (ffffffff) => 000000ff, (00000000 00000000) + lbzu -8, (00000000) => 00000000 (00000000 00000000) + lbzu -4, (000f423f) => 00000000 (00000000 00000000) + lbzu 0, (ffffffff) => 000000ff (00000000 00000000) + + lha 0, (00000000) => 00000000, (00000000 00000000) + lha 4, (000f423f) => 0000000f, (00000000 00000000) + lha 8, (ffffffff) => ffffffff, (00000000 00000000) + lha -8, (00000000) => 00000000 (00000000 00000000) + lha -4, (000f423f) => 0000000f (00000000 00000000) + lha 0, (ffffffff) => ffffffff (00000000 00000000) + + lhau 0, (00000000) => 00000000, (00000000 00000000) + lhau 4, (000f423f) => 0000000f, (00000000 00000000) + lhau 8, (ffffffff) => ffffffff, (00000000 00000000) + lhau -8, (00000000) => 00000000 (00000000 00000000) + lhau -4, (000f423f) => 0000000f (00000000 00000000) + lhau 0, (ffffffff) => ffffffff (00000000 00000000) + + lhz 0, (00000000) => 00000000, (00000000 00000000) + lhz 4, (000f423f) => 0000000f, (00000000 00000000) + lhz 8, (ffffffff) => 0000ffff, (00000000 00000000) + lhz -8, (00000000) => 00000000 (00000000 00000000) + lhz -4, (000f423f) => 0000000f (00000000 00000000) + lhz 0, (ffffffff) => 0000ffff (00000000 00000000) + + lhzu 0, (00000000) => 00000000, (00000000 00000000) + lhzu 4, (000f423f) => 0000000f, (00000000 00000000) + lhzu 8, (ffffffff) => 0000ffff, (00000000 00000000) + lhzu -8, (00000000) => 00000000 (00000000 00000000) + lhzu -4, (000f423f) => 0000000f (00000000 00000000) + lhzu 0, (ffffffff) => 0000ffff (00000000 00000000) + + lwz 0, (00000000) => 00000000, (00000000 00000000) + lwz 4, (000f423f) => 000f423f, (00000000 00000000) + lwz 8, (ffffffff) => ffffffff, (00000000 00000000) + lwz -8, (00000000) => 00000000 (00000000 00000000) + lwz -4, (000f423f) => 000f423f (00000000 00000000) + lwz 0, (ffffffff) => ffffffff (00000000 00000000) + + lwzu 0, (00000000) => 00000000, (00000000 00000000) + lwzu 4, (000f423f) => 000f423f, (00000000 00000000) + lwzu 8, (ffffffff) => ffffffff, (00000000 00000000) + lwzu -8, (00000000) => 00000000 (00000000 00000000) + lwzu -4, (000f423f) => 000f423f (00000000 00000000) + lwzu 0, (ffffffff) => ffffffff (00000000 00000000) + +PPC integer load insns with two register args: + lbzx 0 (00000000) => 00000000 (00000000 00000000) + lbzx 4 (000f423f) => 00000000 (00000000 00000000) + lbzx 8 (ffffffff) => 000000ff (00000000 00000000) + + lbzux 0 (00000000) => 00000000 (00000000 00000000) + lbzux 4 (000f423f) => 00000000 (00000000 00000000) + lbzux 8 (ffffffff) => 000000ff (00000000 00000000) + + lhax 0 (00000000) => 00000000 (00000000 00000000) + lhax 4 (000f423f) => 0000000f (00000000 00000000) + lhax 8 (ffffffff) => ffffffff (00000000 00000000) + + lhaux 0 (00000000) => 00000000 (00000000 00000000) + lhaux 4 (000f423f) => 0000000f (00000000 00000000) + lhaux 8 (ffffffff) => ffffffff (00000000 00000000) + + lhzx 0 (00000000) => 00000000 (00000000 00000000) + lhzx 4 (000f423f) => 0000000f (00000000 00000000) + lhzx 8 (ffffffff) => 0000ffff (00000000 00000000) + + lhzux 0 (00000000) => 00000000 (00000000 00000000) + lhzux 4 (000f423f) => 0000000f (00000000 00000000) + lhzux 8 (ffffffff) => 0000ffff (00000000 00000000) + + lwzx 0 (00000000) => 00000000 (00000000 00000000) + lwzx 4 (000f423f) => 000f423f (00000000 00000000) + lwzx 8 (ffffffff) => ffffffff (00000000 00000000) + + lwzux 0 (00000000) => 00000000 (00000000 00000000) + lwzux 4 (000f423f) => 000f423f (00000000 00000000) + lwzux 8 (ffffffff) => ffffffff (00000000 00000000) + +PPC integer store insns + with one register + one 16 bits immediate args with flags update: + stb 00000000, 0 => 00000000, (00000000 00000000) + stb 000f423f, 4 => 3f000000, (00000000 00000000) + stb ffffffff, 8 => ff000000, (00000000 00000000) + stb 00000000, -8 => 00000000, (00000000 00000000) + stb 000f423f, -4 => 3f000000, (00000000 00000000) + stb ffffffff, 0 => ff000000, (00000000 00000000) + + stbu 00000000, 0 => 00000000, (00000000 00000000) + stbu 000f423f, 4 => 3f000000, (00000000 00000000) + stbu ffffffff, 8 => ff000000, (00000000 00000000) + stbu 00000000, -8 => 00000000, (00000000 00000000) + stbu 000f423f, -4 => 3f000000, (00000000 00000000) + stbu ffffffff, 0 => ff000000, (00000000 00000000) + + sth 00000000, 0 => 00000000, (00000000 00000000) + sth 000f423f, 4 => 423f0000, (00000000 00000000) + sth ffffffff, 8 => ffff0000, (00000000 00000000) + sth 00000000, -8 => 00000000, (00000000 00000000) + sth 000f423f, -4 => 423f0000, (00000000 00000000) + sth ffffffff, 0 => ffff0000, (00000000 00000000) + + sthu 00000000, 0 => 00000000, (00000000 00000000) + sthu 000f423f, 4 => 423f0000, (00000000 00000000) + sthu ffffffff, 8 => ffff0000, (00000000 00000000) + sthu 00000000, -8 => 00000000, (00000000 00000000) + sthu 000f423f, -4 => 423f0000, (00000000 00000000) + sthu ffffffff, 0 => ffff0000, (00000000 00000000) + + stw 00000000, 0 => 00000000, (00000000 00000000) + stw 000f423f, 4 => 000f423f, (00000000 00000000) + stw ffffffff, 8 => ffffffff, (00000000 00000000) + stw 00000000, -8 => 00000000, (00000000 00000000) + stw 000f423f, -4 => 000f423f, (00000000 00000000) + stw ffffffff, 0 => ffffffff, (00000000 00000000) + + stwu 00000000, 0 => 00000000, (00000000 00000000) + stwu 000f423f, 4 => 000f423f, (00000000 00000000) + stwu ffffffff, 8 => ffffffff, (00000000 00000000) + stwu 00000000, -8 => 00000000, (00000000 00000000) + stwu 000f423f, -4 => 000f423f, (00000000 00000000) + stwu ffffffff, 0 => ffffffff, (00000000 00000000) + +PPC integer store insns with three register args: + stbx 00000000, 0 => 00000000, (00000000 00000000) + stbx 000f423f, 4 => 3f000000, (00000000 00000000) + stbx ffffffff, 8 => ff000000, (00000000 00000000) + + stbux 00000000, 0 => 00000000, (00000000 00000000) + stbux 000f423f, 4 => 3f000000, (00000000 00000000) + stbux ffffffff, 8 => ff000000, (00000000 00000000) + + sthx 00000000, 0 => 00000000, (00000000 00000000) + sthx 000f423f, 4 => 423f0000, (00000000 00000000) + sthx ffffffff, 8 => ffff0000, (00000000 00000000) + + sthux 00000000, 0 => 00000000, (00000000 00000000) + sthux 000f423f, 4 => 423f0000, (00000000 00000000) + sthux ffffffff, 8 => ffff0000, (00000000 00000000) + + stwx 00000000, 0 => 00000000, (00000000 00000000) + stwx 000f423f, 4 => 000f423f, (00000000 00000000) + stwx ffffffff, 8 => ffffffff, (00000000 00000000) + + stwux 00000000, 0 => 00000000, (00000000 00000000) + stwux 000f423f, 4 => 000f423f, (00000000 00000000) + stwux ffffffff, 8 => ffffffff, (00000000 00000000) + +All done. Tested 154 different instructions diff --git a/none/tests/ppc32/jm-insns.vgtest b/none/tests/ppc32/jm-insns.vgtest new file mode 100644 index 0000000000..0a5c57a759 --- /dev/null +++ b/none/tests/ppc32/jm-insns.vgtest @@ -0,0 +1 @@ +prog: jm-insns diff --git a/none/tests/ppc32/jm-vmx.stderr.exp b/none/tests/ppc32/jm-vmx.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc32/jm-vmx.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/jm-vmx.stdout.exp b/none/tests/ppc32/jm-vmx.stdout.exp new file mode 100644 index 0000000000..b152b4818b --- /dev/null +++ b/none/tests/ppc32/jm-vmx.stdout.exp @@ -0,0 +1,3041 @@ +PPC integer arith insns with two args: + add 00000000, 00000000 => 00000000 (00000000 00000000) + add 00000000, 000f423f => 000f423f (00000000 00000000) + add 00000000, ffffffff => ffffffff (00000000 00000000) + add 000f423f, 00000000 => 000f423f (00000000 00000000) + add 000f423f, 000f423f => 001e847e (00000000 00000000) + add 000f423f, ffffffff => 000f423e (00000000 00000000) + add ffffffff, 00000000 => ffffffff (00000000 00000000) + add ffffffff, 000f423f => 000f423e (00000000 00000000) + add ffffffff, ffffffff => fffffffe (00000000 00000000) + + addo 00000000, 00000000 => 00000000 (00000000 00000000) + addo 00000000, 000f423f => 000f423f (00000000 00000000) + addo 00000000, ffffffff => ffffffff (00000000 00000000) + addo 000f423f, 00000000 => 000f423f (00000000 00000000) + addo 000f423f, 000f423f => 001e847e (00000000 00000000) + addo 000f423f, ffffffff => 000f423e (00000000 00000000) + addo ffffffff, 00000000 => ffffffff (00000000 00000000) + addo ffffffff, 000f423f => 000f423e (00000000 00000000) + addo ffffffff, ffffffff => fffffffe (00000000 00000000) + + addc 00000000, 00000000 => 00000000 (00000000 00000000) + addc 00000000, 000f423f => 000f423f (00000000 00000000) + addc 00000000, ffffffff => ffffffff (00000000 00000000) + addc 000f423f, 00000000 => 000f423f (00000000 00000000) + addc 000f423f, 000f423f => 001e847e (00000000 00000000) + addc 000f423f, ffffffff => 000f423e (00000000 20000000) + addc ffffffff, 00000000 => ffffffff (00000000 00000000) + addc ffffffff, 000f423f => 000f423e (00000000 20000000) + addc ffffffff, ffffffff => fffffffe (00000000 20000000) + + addco 00000000, 00000000 => 00000000 (00000000 00000000) + addco 00000000, 000f423f => 000f423f (00000000 00000000) + addco 00000000, ffffffff => ffffffff (00000000 00000000) + addco 000f423f, 00000000 => 000f423f (00000000 00000000) + addco 000f423f, 000f423f => 001e847e (00000000 00000000) + addco 000f423f, ffffffff => 000f423e (00000000 20000000) + addco ffffffff, 00000000 => ffffffff (00000000 00000000) + addco ffffffff, 000f423f => 000f423e (00000000 20000000) + addco ffffffff, ffffffff => fffffffe (00000000 20000000) + + divw 00000000, 00000000 => 00000000 (00000000 00000000) + divw 00000000, 000f423f => 00000000 (00000000 00000000) + divw 00000000, ffffffff => 00000000 (00000000 00000000) + divw 000f423f, 00000000 => 00000000 (00000000 00000000) + divw 000f423f, 000f423f => 00000001 (00000000 00000000) + divw 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + divw ffffffff, 00000000 => 00000000 (00000000 00000000) + divw ffffffff, 000f423f => 00000000 (00000000 00000000) + divw ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwo 00000000, 00000000 => 00000000 (00000000 c0000000) + divwo 00000000, 000f423f => 00000000 (00000000 00000000) + divwo 00000000, ffffffff => 00000000 (00000000 00000000) + divwo 000f423f, 00000000 => 00000000 (00000000 c0000000) + divwo 000f423f, 000f423f => 00000001 (00000000 00000000) + divwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + divwo ffffffff, 00000000 => 00000000 (00000000 c0000000) + divwo ffffffff, 000f423f => 00000000 (00000000 00000000) + divwo ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwu 00000000, 00000000 => 00000000 (00000000 00000000) + divwu 00000000, 000f423f => 00000000 (00000000 00000000) + divwu 00000000, ffffffff => 00000000 (00000000 00000000) + divwu 000f423f, 00000000 => 00000000 (00000000 00000000) + divwu 000f423f, 000f423f => 00000001 (00000000 00000000) + divwu 000f423f, ffffffff => 00000000 (00000000 00000000) + divwu ffffffff, 00000000 => 00000000 (00000000 00000000) + divwu ffffffff, 000f423f => 000010c6 (00000000 00000000) + divwu ffffffff, ffffffff => 00000001 (00000000 00000000) + + divwuo 00000000, 00000000 => 00000000 (00000000 c0000000) + divwuo 00000000, 000f423f => 00000000 (00000000 00000000) + divwuo 00000000, ffffffff => 00000000 (00000000 00000000) + divwuo 000f423f, 00000000 => 00000000 (00000000 c0000000) + divwuo 000f423f, 000f423f => 00000001 (00000000 00000000) + divwuo 000f423f, ffffffff => 00000000 (00000000 00000000) + divwuo ffffffff, 00000000 => 00000000 (00000000 c0000000) + divwuo ffffffff, 000f423f => 000010c6 (00000000 00000000) + divwuo ffffffff, ffffffff => 00000001 (00000000 00000000) + + mulhw 00000000, 00000000 => 00000000 (00000000 00000000) + mulhw 00000000, 000f423f => 00000000 (00000000 00000000) + mulhw 00000000, ffffffff => 00000000 (00000000 00000000) + mulhw 000f423f, 00000000 => 00000000 (00000000 00000000) + mulhw 000f423f, 000f423f => 000000e8 (00000000 00000000) + mulhw 000f423f, ffffffff => ffffffff (00000000 00000000) + mulhw ffffffff, 00000000 => 00000000 (00000000 00000000) + mulhw ffffffff, 000f423f => ffffffff (00000000 00000000) + mulhw ffffffff, ffffffff => 00000000 (00000000 00000000) + + mulhwu 00000000, 00000000 => 00000000 (00000000 00000000) + mulhwu 00000000, 000f423f => 00000000 (00000000 00000000) + mulhwu 00000000, ffffffff => 00000000 (00000000 00000000) + mulhwu 000f423f, 00000000 => 00000000 (00000000 00000000) + mulhwu 000f423f, 000f423f => 000000e8 (00000000 00000000) + mulhwu 000f423f, ffffffff => 000f423e (00000000 00000000) + mulhwu ffffffff, 00000000 => 00000000 (00000000 00000000) + mulhwu ffffffff, 000f423f => 000f423e (00000000 00000000) + mulhwu ffffffff, ffffffff => fffffffe (00000000 00000000) + + mullw 00000000, 00000000 => 00000000 (00000000 00000000) + mullw 00000000, 000f423f => 00000000 (00000000 00000000) + mullw 00000000, ffffffff => 00000000 (00000000 00000000) + mullw 000f423f, 00000000 => 00000000 (00000000 00000000) + mullw 000f423f, 000f423f => d4868b81 (00000000 00000000) + mullw 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + mullw ffffffff, 00000000 => 00000000 (00000000 00000000) + mullw ffffffff, 000f423f => fff0bdc1 (00000000 00000000) + mullw ffffffff, ffffffff => 00000001 (00000000 00000000) + + mullwo 00000000, 00000000 => 00000000 (00000000 00000000) + mullwo 00000000, 000f423f => 00000000 (00000000 00000000) + mullwo 00000000, ffffffff => 00000000 (00000000 00000000) + mullwo 000f423f, 00000000 => 00000000 (00000000 00000000) + mullwo 000f423f, 000f423f => d4868b81 (00000000 c0000000) + mullwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000) + mullwo ffffffff, 00000000 => 00000000 (00000000 00000000) + mullwo ffffffff, 000f423f => fff0bdc1 (00000000 00000000) + mullwo ffffffff, ffffffff => 00000001 (00000000 00000000) + + subf 00000000, 00000000 => 00000000 (00000000 00000000) + subf 00000000, 000f423f => 000f423f (00000000 00000000) + subf 00000000, ffffffff => ffffffff (00000000 00000000) + subf 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subf 000f423f, 000f423f => 00000000 (00000000 00000000) + subf 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + subf ffffffff, 00000000 => 00000001 (00000000 00000000) + subf ffffffff, 000f423f => 000f4240 (00000000 00000000) + subf ffffffff, ffffffff => 00000000 (00000000 00000000) + + subfo 00000000, 00000000 => 00000000 (00000000 00000000) + subfo 00000000, 000f423f => 000f423f (00000000 00000000) + subfo 00000000, ffffffff => ffffffff (00000000 00000000) + subfo 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfo 000f423f, 000f423f => 00000000 (00000000 00000000) + subfo 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + subfo ffffffff, 00000000 => 00000001 (00000000 00000000) + subfo ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfo ffffffff, ffffffff => 00000000 (00000000 00000000) + + subfc 00000000, 00000000 => 00000000 (00000000 20000000) + subfc 00000000, 000f423f => 000f423f (00000000 20000000) + subfc 00000000, ffffffff => ffffffff (00000000 20000000) + subfc 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfc 000f423f, 000f423f => 00000000 (00000000 20000000) + subfc 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfc ffffffff, 00000000 => 00000001 (00000000 00000000) + subfc ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfc ffffffff, ffffffff => 00000000 (00000000 20000000) + + subfco 00000000, 00000000 => 00000000 (00000000 20000000) + subfco 00000000, 000f423f => 000f423f (00000000 20000000) + subfco 00000000, ffffffff => ffffffff (00000000 20000000) + subfco 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfco 000f423f, 000f423f => 00000000 (00000000 20000000) + subfco 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfco ffffffff, 00000000 => 00000001 (00000000 00000000) + subfco ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfco ffffffff, ffffffff => 00000000 (00000000 20000000) + +PPC integer arith insns with two args with flags update: + add. 00000000, 00000000 => 00000000 (20000000 00000000) + add. 00000000, 000f423f => 000f423f (40000000 00000000) + add. 00000000, ffffffff => ffffffff (80000000 00000000) + add. 000f423f, 00000000 => 000f423f (40000000 00000000) + add. 000f423f, 000f423f => 001e847e (40000000 00000000) + add. 000f423f, ffffffff => 000f423e (40000000 00000000) + add. ffffffff, 00000000 => ffffffff (80000000 00000000) + add. ffffffff, 000f423f => 000f423e (40000000 00000000) + add. ffffffff, ffffffff => fffffffe (80000000 00000000) + + addo. 00000000, 00000000 => 00000000 (20000000 00000000) + addo. 00000000, 000f423f => 000f423f (40000000 00000000) + addo. 00000000, ffffffff => ffffffff (80000000 00000000) + addo. 000f423f, 00000000 => 000f423f (40000000 00000000) + addo. 000f423f, 000f423f => 001e847e (40000000 00000000) + addo. 000f423f, ffffffff => 000f423e (40000000 00000000) + addo. ffffffff, 00000000 => ffffffff (80000000 00000000) + addo. ffffffff, 000f423f => 000f423e (40000000 00000000) + addo. ffffffff, ffffffff => fffffffe (80000000 00000000) + + addc. 00000000, 00000000 => 00000000 (20000000 00000000) + addc. 00000000, 000f423f => 000f423f (40000000 00000000) + addc. 00000000, ffffffff => ffffffff (80000000 00000000) + addc. 000f423f, 00000000 => 000f423f (40000000 00000000) + addc. 000f423f, 000f423f => 001e847e (40000000 00000000) + addc. 000f423f, ffffffff => 000f423e (40000000 20000000) + addc. ffffffff, 00000000 => ffffffff (80000000 00000000) + addc. ffffffff, 000f423f => 000f423e (40000000 20000000) + addc. ffffffff, ffffffff => fffffffe (80000000 20000000) + + addco. 00000000, 00000000 => 00000000 (20000000 00000000) + addco. 00000000, 000f423f => 000f423f (40000000 00000000) + addco. 00000000, ffffffff => ffffffff (80000000 00000000) + addco. 000f423f, 00000000 => 000f423f (40000000 00000000) + addco. 000f423f, 000f423f => 001e847e (40000000 00000000) + addco. 000f423f, ffffffff => 000f423e (40000000 20000000) + addco. ffffffff, 00000000 => ffffffff (80000000 00000000) + addco. ffffffff, 000f423f => 000f423e (40000000 20000000) + addco. ffffffff, ffffffff => fffffffe (80000000 20000000) + + divw. 00000000, 00000000 => 00000000 (20000000 00000000) + divw. 00000000, 000f423f => 00000000 (20000000 00000000) + divw. 00000000, ffffffff => 00000000 (20000000 00000000) + divw. 000f423f, 00000000 => 00000000 (20000000 00000000) + divw. 000f423f, 000f423f => 00000001 (40000000 00000000) + divw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + divw. ffffffff, 00000000 => 00000000 (20000000 00000000) + divw. ffffffff, 000f423f => 00000000 (20000000 00000000) + divw. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwo. 00000000, 00000000 => 00000000 (30000000 c0000000) + divwo. 00000000, 000f423f => 00000000 (20000000 00000000) + divwo. 00000000, ffffffff => 00000000 (20000000 00000000) + divwo. 000f423f, 00000000 => 00000000 (30000000 c0000000) + divwo. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + divwo. ffffffff, 00000000 => 00000000 (30000000 c0000000) + divwo. ffffffff, 000f423f => 00000000 (20000000 00000000) + divwo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwu. 00000000, 00000000 => 00000000 (20000000 00000000) + divwu. 00000000, 000f423f => 00000000 (20000000 00000000) + divwu. 00000000, ffffffff => 00000000 (20000000 00000000) + divwu. 000f423f, 00000000 => 00000000 (20000000 00000000) + divwu. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwu. 000f423f, ffffffff => 00000000 (20000000 00000000) + divwu. ffffffff, 00000000 => 00000000 (20000000 00000000) + divwu. ffffffff, 000f423f => 000010c6 (40000000 00000000) + divwu. ffffffff, ffffffff => 00000001 (40000000 00000000) + + divwuo. 00000000, 00000000 => 00000000 (30000000 c0000000) + divwuo. 00000000, 000f423f => 00000000 (20000000 00000000) + divwuo. 00000000, ffffffff => 00000000 (20000000 00000000) + divwuo. 000f423f, 00000000 => 00000000 (30000000 c0000000) + divwuo. 000f423f, 000f423f => 00000001 (40000000 00000000) + divwuo. 000f423f, ffffffff => 00000000 (20000000 00000000) + divwuo. ffffffff, 00000000 => 00000000 (30000000 c0000000) + divwuo. ffffffff, 000f423f => 000010c6 (40000000 00000000) + divwuo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + mulhw. 00000000, 00000000 => 00000000 (20000000 00000000) + mulhw. 00000000, 000f423f => 00000000 (20000000 00000000) + mulhw. 00000000, ffffffff => 00000000 (20000000 00000000) + mulhw. 000f423f, 00000000 => 00000000 (20000000 00000000) + mulhw. 000f423f, 000f423f => 000000e8 (40000000 00000000) + mulhw. 000f423f, ffffffff => ffffffff (80000000 00000000) + mulhw. ffffffff, 00000000 => 00000000 (20000000 00000000) + mulhw. ffffffff, 000f423f => ffffffff (80000000 00000000) + mulhw. ffffffff, ffffffff => 00000000 (20000000 00000000) + + mulhwu. 00000000, 00000000 => 00000000 (20000000 00000000) + mulhwu. 00000000, 000f423f => 00000000 (20000000 00000000) + mulhwu. 00000000, ffffffff => 00000000 (20000000 00000000) + mulhwu. 000f423f, 00000000 => 00000000 (20000000 00000000) + mulhwu. 000f423f, 000f423f => 000000e8 (40000000 00000000) + mulhwu. 000f423f, ffffffff => 000f423e (40000000 00000000) + mulhwu. ffffffff, 00000000 => 00000000 (20000000 00000000) + mulhwu. ffffffff, 000f423f => 000f423e (40000000 00000000) + mulhwu. ffffffff, ffffffff => fffffffe (80000000 00000000) + + mullw. 00000000, 00000000 => 00000000 (20000000 00000000) + mullw. 00000000, 000f423f => 00000000 (20000000 00000000) + mullw. 00000000, ffffffff => 00000000 (20000000 00000000) + mullw. 000f423f, 00000000 => 00000000 (20000000 00000000) + mullw. 000f423f, 000f423f => d4868b81 (80000000 00000000) + mullw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + mullw. ffffffff, 00000000 => 00000000 (20000000 00000000) + mullw. ffffffff, 000f423f => fff0bdc1 (80000000 00000000) + mullw. ffffffff, ffffffff => 00000001 (40000000 00000000) + + mullwo. 00000000, 00000000 => 00000000 (20000000 00000000) + mullwo. 00000000, 000f423f => 00000000 (20000000 00000000) + mullwo. 00000000, ffffffff => 00000000 (20000000 00000000) + mullwo. 000f423f, 00000000 => 00000000 (20000000 00000000) + mullwo. 000f423f, 000f423f => d4868b81 (90000000 c0000000) + mullwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000) + mullwo. ffffffff, 00000000 => 00000000 (20000000 00000000) + mullwo. ffffffff, 000f423f => fff0bdc1 (80000000 00000000) + mullwo. ffffffff, ffffffff => 00000001 (40000000 00000000) + + subf. 00000000, 00000000 => 00000000 (20000000 00000000) + subf. 00000000, 000f423f => 000f423f (40000000 00000000) + subf. 00000000, ffffffff => ffffffff (80000000 00000000) + subf. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subf. 000f423f, 000f423f => 00000000 (20000000 00000000) + subf. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + subf. ffffffff, 00000000 => 00000001 (40000000 00000000) + subf. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subf. ffffffff, ffffffff => 00000000 (20000000 00000000) + + subfo. 00000000, 00000000 => 00000000 (20000000 00000000) + subfo. 00000000, 000f423f => 000f423f (40000000 00000000) + subfo. 00000000, ffffffff => ffffffff (80000000 00000000) + subfo. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfo. 000f423f, 000f423f => 00000000 (20000000 00000000) + subfo. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + subfo. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfo. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfo. ffffffff, ffffffff => 00000000 (20000000 00000000) + + subfc. 00000000, 00000000 => 00000000 (20000000 20000000) + subfc. 00000000, 000f423f => 000f423f (40000000 20000000) + subfc. 00000000, ffffffff => ffffffff (80000000 20000000) + subfc. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfc. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfc. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfc. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfc. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfc. ffffffff, ffffffff => 00000000 (20000000 20000000) + + subfco. 00000000, 00000000 => 00000000 (20000000 20000000) + subfco. 00000000, 000f423f => 000f423f (40000000 20000000) + subfco. 00000000, ffffffff => ffffffff (80000000 20000000) + subfco. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfco. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfco. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfco. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfco. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfco. ffffffff, ffffffff => 00000000 (20000000 20000000) + +PPC integer arith insns with two args and carry: + adde 00000000, 00000000 => 00000000 (00000000 00000000) + adde 00000000, 000f423f => 000f423f (00000000 00000000) + adde 00000000, ffffffff => ffffffff (00000000 00000000) + adde 000f423f, 00000000 => 000f423f (00000000 00000000) + adde 000f423f, 000f423f => 001e847e (00000000 00000000) + adde 000f423f, ffffffff => 000f423e (00000000 20000000) + adde ffffffff, 00000000 => ffffffff (00000000 00000000) + adde ffffffff, 000f423f => 000f423e (00000000 20000000) + adde ffffffff, ffffffff => fffffffe (00000000 20000000) + adde 00000000, 00000000 => 00000001 (00000000 00000000) + adde 00000000, 000f423f => 000f4240 (00000000 00000000) + adde 00000000, ffffffff => 00000000 (00000000 20000000) + adde 000f423f, 00000000 => 000f4240 (00000000 00000000) + adde 000f423f, 000f423f => 001e847f (00000000 00000000) + adde 000f423f, ffffffff => 000f423f (00000000 20000000) + adde ffffffff, 00000000 => 00000000 (00000000 20000000) + adde ffffffff, 000f423f => 000f423f (00000000 20000000) + adde ffffffff, ffffffff => ffffffff (00000000 20000000) + + addeo 00000000, 00000000 => 00000000 (00000000 00000000) + addeo 00000000, 000f423f => 000f423f (00000000 00000000) + addeo 00000000, ffffffff => ffffffff (00000000 00000000) + addeo 000f423f, 00000000 => 000f423f (00000000 00000000) + addeo 000f423f, 000f423f => 001e847e (00000000 00000000) + addeo 000f423f, ffffffff => 000f423e (00000000 20000000) + addeo ffffffff, 00000000 => ffffffff (00000000 00000000) + addeo ffffffff, 000f423f => 000f423e (00000000 20000000) + addeo ffffffff, ffffffff => fffffffe (00000000 20000000) + addeo 00000000, 00000000 => 00000001 (00000000 00000000) + addeo 00000000, 000f423f => 000f4240 (00000000 00000000) + addeo 00000000, ffffffff => 00000000 (00000000 20000000) + addeo 000f423f, 00000000 => 000f4240 (00000000 00000000) + addeo 000f423f, 000f423f => 001e847f (00000000 00000000) + addeo 000f423f, ffffffff => 000f423f (00000000 20000000) + addeo ffffffff, 00000000 => 00000000 (00000000 20000000) + addeo ffffffff, 000f423f => 000f423f (00000000 20000000) + addeo ffffffff, ffffffff => ffffffff (00000000 20000000) + + subfe 00000000, 00000000 => ffffffff (00000000 00000000) + subfe 00000000, 000f423f => 000f423e (00000000 20000000) + subfe 00000000, ffffffff => fffffffe (00000000 20000000) + subfe 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + subfe 000f423f, 000f423f => ffffffff (00000000 00000000) + subfe 000f423f, ffffffff => fff0bdbf (00000000 20000000) + subfe ffffffff, 00000000 => 00000000 (00000000 00000000) + subfe ffffffff, 000f423f => 000f423f (00000000 00000000) + subfe ffffffff, ffffffff => ffffffff (00000000 00000000) + subfe 00000000, 00000000 => 00000000 (00000000 20000000) + subfe 00000000, 000f423f => 000f423f (00000000 20000000) + subfe 00000000, ffffffff => ffffffff (00000000 20000000) + subfe 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfe 000f423f, 000f423f => 00000000 (00000000 20000000) + subfe 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfe ffffffff, 00000000 => 00000001 (00000000 00000000) + subfe ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfe ffffffff, ffffffff => 00000000 (00000000 20000000) + + subfeo 00000000, 00000000 => ffffffff (00000000 00000000) + subfeo 00000000, 000f423f => 000f423e (00000000 20000000) + subfeo 00000000, ffffffff => fffffffe (00000000 20000000) + subfeo 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + subfeo 000f423f, 000f423f => ffffffff (00000000 00000000) + subfeo 000f423f, ffffffff => fff0bdbf (00000000 20000000) + subfeo ffffffff, 00000000 => 00000000 (00000000 00000000) + subfeo ffffffff, 000f423f => 000f423f (00000000 00000000) + subfeo ffffffff, ffffffff => ffffffff (00000000 00000000) + subfeo 00000000, 00000000 => 00000000 (00000000 20000000) + subfeo 00000000, 000f423f => 000f423f (00000000 20000000) + subfeo 00000000, ffffffff => ffffffff (00000000 20000000) + subfeo 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfeo 000f423f, 000f423f => 00000000 (00000000 20000000) + subfeo 000f423f, ffffffff => fff0bdc0 (00000000 20000000) + subfeo ffffffff, 00000000 => 00000001 (00000000 00000000) + subfeo ffffffff, 000f423f => 000f4240 (00000000 00000000) + subfeo ffffffff, ffffffff => 00000000 (00000000 20000000) + +PPC integer arith insns with two args and carry with flags update: + adde. 00000000, 00000000 => 00000000 (20000000 00000000) + adde. 00000000, 000f423f => 000f423f (40000000 00000000) + adde. 00000000, ffffffff => ffffffff (80000000 00000000) + adde. 000f423f, 00000000 => 000f423f (40000000 00000000) + adde. 000f423f, 000f423f => 001e847e (40000000 00000000) + adde. 000f423f, ffffffff => 000f423e (40000000 20000000) + adde. ffffffff, 00000000 => ffffffff (80000000 00000000) + adde. ffffffff, 000f423f => 000f423e (40000000 20000000) + adde. ffffffff, ffffffff => fffffffe (80000000 20000000) + adde. 00000000, 00000000 => 00000001 (40000000 00000000) + adde. 00000000, 000f423f => 000f4240 (40000000 00000000) + adde. 00000000, ffffffff => 00000000 (20000000 20000000) + adde. 000f423f, 00000000 => 000f4240 (40000000 00000000) + adde. 000f423f, 000f423f => 001e847f (40000000 00000000) + adde. 000f423f, ffffffff => 000f423f (40000000 20000000) + adde. ffffffff, 00000000 => 00000000 (20000000 20000000) + adde. ffffffff, 000f423f => 000f423f (40000000 20000000) + adde. ffffffff, ffffffff => ffffffff (80000000 20000000) + + addeo. 00000000, 00000000 => 00000000 (20000000 00000000) + addeo. 00000000, 000f423f => 000f423f (40000000 00000000) + addeo. 00000000, ffffffff => ffffffff (80000000 00000000) + addeo. 000f423f, 00000000 => 000f423f (40000000 00000000) + addeo. 000f423f, 000f423f => 001e847e (40000000 00000000) + addeo. 000f423f, ffffffff => 000f423e (40000000 20000000) + addeo. ffffffff, 00000000 => ffffffff (80000000 00000000) + addeo. ffffffff, 000f423f => 000f423e (40000000 20000000) + addeo. ffffffff, ffffffff => fffffffe (80000000 20000000) + addeo. 00000000, 00000000 => 00000001 (40000000 00000000) + addeo. 00000000, 000f423f => 000f4240 (40000000 00000000) + addeo. 00000000, ffffffff => 00000000 (20000000 20000000) + addeo. 000f423f, 00000000 => 000f4240 (40000000 00000000) + addeo. 000f423f, 000f423f => 001e847f (40000000 00000000) + addeo. 000f423f, ffffffff => 000f423f (40000000 20000000) + addeo. ffffffff, 00000000 => 00000000 (20000000 20000000) + addeo. ffffffff, 000f423f => 000f423f (40000000 20000000) + addeo. ffffffff, ffffffff => ffffffff (80000000 20000000) + + subfe. 00000000, 00000000 => ffffffff (80000000 00000000) + subfe. 00000000, 000f423f => 000f423e (40000000 20000000) + subfe. 00000000, ffffffff => fffffffe (80000000 20000000) + subfe. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + subfe. 000f423f, 000f423f => ffffffff (80000000 00000000) + subfe. 000f423f, ffffffff => fff0bdbf (80000000 20000000) + subfe. ffffffff, 00000000 => 00000000 (20000000 00000000) + subfe. ffffffff, 000f423f => 000f423f (40000000 00000000) + subfe. ffffffff, ffffffff => ffffffff (80000000 00000000) + subfe. 00000000, 00000000 => 00000000 (20000000 20000000) + subfe. 00000000, 000f423f => 000f423f (40000000 20000000) + subfe. 00000000, ffffffff => ffffffff (80000000 20000000) + subfe. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfe. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfe. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfe. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfe. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfe. ffffffff, ffffffff => 00000000 (20000000 20000000) + + subfeo. 00000000, 00000000 => ffffffff (80000000 00000000) + subfeo. 00000000, 000f423f => 000f423e (40000000 20000000) + subfeo. 00000000, ffffffff => fffffffe (80000000 20000000) + subfeo. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + subfeo. 000f423f, 000f423f => ffffffff (80000000 00000000) + subfeo. 000f423f, ffffffff => fff0bdbf (80000000 20000000) + subfeo. ffffffff, 00000000 => 00000000 (20000000 00000000) + subfeo. ffffffff, 000f423f => 000f423f (40000000 00000000) + subfeo. ffffffff, ffffffff => ffffffff (80000000 00000000) + subfeo. 00000000, 00000000 => 00000000 (20000000 20000000) + subfeo. 00000000, 000f423f => 000f423f (40000000 20000000) + subfeo. 00000000, ffffffff => ffffffff (80000000 20000000) + subfeo. 000f423f, 00000000 => fff0bdc1 (80000000 00000000) + subfeo. 000f423f, 000f423f => 00000000 (20000000 20000000) + subfeo. 000f423f, ffffffff => fff0bdc0 (80000000 20000000) + subfeo. ffffffff, 00000000 => 00000001 (40000000 00000000) + subfeo. ffffffff, 000f423f => 000f4240 (40000000 00000000) + subfeo. ffffffff, ffffffff => 00000000 (20000000 20000000) + +PPC integer logical insns with two args: + and 00000000, 00000000 => 00000000 (00000000 00000000) + and 00000000, 000f423f => 00000000 (00000000 00000000) + and 00000000, ffffffff => 00000000 (00000000 00000000) + and 000f423f, 00000000 => 00000000 (00000000 00000000) + and 000f423f, 000f423f => 000f423f (00000000 00000000) + and 000f423f, ffffffff => 000f423f (00000000 00000000) + and ffffffff, 00000000 => 00000000 (00000000 00000000) + and ffffffff, 000f423f => 000f423f (00000000 00000000) + and ffffffff, ffffffff => ffffffff (00000000 00000000) + + andc 00000000, 00000000 => 00000000 (00000000 00000000) + andc 00000000, 000f423f => 00000000 (00000000 00000000) + andc 00000000, ffffffff => 00000000 (00000000 00000000) + andc 000f423f, 00000000 => 000f423f (00000000 00000000) + andc 000f423f, 000f423f => 00000000 (00000000 00000000) + andc 000f423f, ffffffff => 00000000 (00000000 00000000) + andc ffffffff, 00000000 => ffffffff (00000000 00000000) + andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + andc ffffffff, ffffffff => 00000000 (00000000 00000000) + + eqv 00000000, 00000000 => ffffffff (00000000 00000000) + eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000) + eqv 00000000, ffffffff => 00000000 (00000000 00000000) + eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + eqv 000f423f, 000f423f => ffffffff (00000000 00000000) + eqv 000f423f, ffffffff => 000f423f (00000000 00000000) + eqv ffffffff, 00000000 => 00000000 (00000000 00000000) + eqv ffffffff, 000f423f => 000f423f (00000000 00000000) + eqv ffffffff, ffffffff => ffffffff (00000000 00000000) + + nand 00000000, 00000000 => ffffffff (00000000 00000000) + nand 00000000, 000f423f => ffffffff (00000000 00000000) + nand 00000000, ffffffff => ffffffff (00000000 00000000) + nand 000f423f, 00000000 => ffffffff (00000000 00000000) + nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000) + nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + nand ffffffff, 00000000 => ffffffff (00000000 00000000) + nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + nand ffffffff, ffffffff => 00000000 (00000000 00000000) + + nor 00000000, 00000000 => ffffffff (00000000 00000000) + nor 00000000, 000f423f => fff0bdc0 (00000000 00000000) + nor 00000000, ffffffff => 00000000 (00000000 00000000) + nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000) + nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000) + nor 000f423f, ffffffff => 00000000 (00000000 00000000) + nor ffffffff, 00000000 => 00000000 (00000000 00000000) + nor ffffffff, 000f423f => 00000000 (00000000 00000000) + nor ffffffff, ffffffff => 00000000 (00000000 00000000) + + or 00000000, 00000000 => 00000000 (00000000 00000000) + or 00000000, 000f423f => 000f423f (00000000 00000000) + or 00000000, ffffffff => ffffffff (00000000 00000000) + or 000f423f, 00000000 => 000f423f (00000000 00000000) + or 000f423f, 000f423f => 000f423f (00000000 00000000) + or 000f423f, ffffffff => ffffffff (00000000 00000000) + or ffffffff, 00000000 => ffffffff (00000000 00000000) + or ffffffff, 000f423f => ffffffff (00000000 00000000) + or ffffffff, ffffffff => ffffffff (00000000 00000000) + + orc 00000000, 00000000 => ffffffff (00000000 00000000) + orc 00000000, 000f423f => fff0bdc0 (00000000 00000000) + orc 00000000, ffffffff => 00000000 (00000000 00000000) + orc 000f423f, 00000000 => ffffffff (00000000 00000000) + orc 000f423f, 000f423f => ffffffff (00000000 00000000) + orc 000f423f, ffffffff => 000f423f (00000000 00000000) + orc ffffffff, 00000000 => ffffffff (00000000 00000000) + orc ffffffff, 000f423f => ffffffff (00000000 00000000) + orc ffffffff, ffffffff => ffffffff (00000000 00000000) + + xor 00000000, 00000000 => 00000000 (00000000 00000000) + xor 00000000, 000f423f => 000f423f (00000000 00000000) + xor 00000000, ffffffff => ffffffff (00000000 00000000) + xor 000f423f, 00000000 => 000f423f (00000000 00000000) + xor 000f423f, 000f423f => 00000000 (00000000 00000000) + xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000) + xor ffffffff, 00000000 => ffffffff (00000000 00000000) + xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000) + xor ffffffff, ffffffff => 00000000 (00000000 00000000) + + slw 00000000, 00000000 => 00000000 (00000000 00000000) + slw 00000000, 000f423f => 00000000 (00000000 00000000) + slw 00000000, ffffffff => 00000000 (00000000 00000000) + slw 000f423f, 00000000 => 000f423f (00000000 00000000) + slw 000f423f, 000f423f => 00000000 (00000000 00000000) + slw 000f423f, ffffffff => 00000000 (00000000 00000000) + slw ffffffff, 00000000 => ffffffff (00000000 00000000) + slw ffffffff, 000f423f => 00000000 (00000000 00000000) + slw ffffffff, ffffffff => 00000000 (00000000 00000000) + + sraw 00000000, 00000000 => 00000000 (00000000 00000000) + sraw 00000000, 000f423f => 00000000 (00000000 00000000) + sraw 00000000, ffffffff => 00000000 (00000000 00000000) + sraw 000f423f, 00000000 => 000f423f (00000000 00000000) + sraw 000f423f, 000f423f => 00000000 (00000000 00000000) + sraw 000f423f, ffffffff => 00000000 (00000000 00000000) + sraw ffffffff, 00000000 => ffffffff (00000000 00000000) + sraw ffffffff, 000f423f => ffffffff (00000000 20000000) + sraw ffffffff, ffffffff => ffffffff (00000000 20000000) + + srw 00000000, 00000000 => 00000000 (00000000 00000000) + srw 00000000, 000f423f => 00000000 (00000000 00000000) + srw 00000000, ffffffff => 00000000 (00000000 00000000) + srw 000f423f, 00000000 => 000f423f (00000000 00000000) + srw 000f423f, 000f423f => 00000000 (00000000 00000000) + srw 000f423f, ffffffff => 00000000 (00000000 00000000) + srw ffffffff, 00000000 => ffffffff (00000000 00000000) + srw ffffffff, 000f423f => 00000000 (00000000 00000000) + srw ffffffff, ffffffff => 00000000 (00000000 00000000) + +PPC integer logical insns with two args with flags update: + and. 00000000, 00000000 => 00000000 (20000000 00000000) + and. 00000000, 000f423f => 00000000 (20000000 00000000) + and. 00000000, ffffffff => 00000000 (20000000 00000000) + and. 000f423f, 00000000 => 00000000 (20000000 00000000) + and. 000f423f, 000f423f => 000f423f (40000000 00000000) + and. 000f423f, ffffffff => 000f423f (40000000 00000000) + and. ffffffff, 00000000 => 00000000 (20000000 00000000) + and. ffffffff, 000f423f => 000f423f (40000000 00000000) + and. ffffffff, ffffffff => ffffffff (80000000 00000000) + + andc. 00000000, 00000000 => 00000000 (20000000 00000000) + andc. 00000000, 000f423f => 00000000 (20000000 00000000) + andc. 00000000, ffffffff => 00000000 (20000000 00000000) + andc. 000f423f, 00000000 => 000f423f (40000000 00000000) + andc. 000f423f, 000f423f => 00000000 (20000000 00000000) + andc. 000f423f, ffffffff => 00000000 (20000000 00000000) + andc. ffffffff, 00000000 => ffffffff (80000000 00000000) + andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + andc. ffffffff, ffffffff => 00000000 (20000000 00000000) + + eqv. 00000000, 00000000 => ffffffff (80000000 00000000) + eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + eqv. 00000000, ffffffff => 00000000 (20000000 00000000) + eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + eqv. 000f423f, 000f423f => ffffffff (80000000 00000000) + eqv. 000f423f, ffffffff => 000f423f (40000000 00000000) + eqv. ffffffff, 00000000 => 00000000 (20000000 00000000) + eqv. ffffffff, 000f423f => 000f423f (40000000 00000000) + eqv. ffffffff, ffffffff => ffffffff (80000000 00000000) + + nand. 00000000, 00000000 => ffffffff (80000000 00000000) + nand. 00000000, 000f423f => ffffffff (80000000 00000000) + nand. 00000000, ffffffff => ffffffff (80000000 00000000) + nand. 000f423f, 00000000 => ffffffff (80000000 00000000) + nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000) + nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + nand. ffffffff, 00000000 => ffffffff (80000000 00000000) + nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + nand. ffffffff, ffffffff => 00000000 (20000000 00000000) + + nor. 00000000, 00000000 => ffffffff (80000000 00000000) + nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + nor. 00000000, ffffffff => 00000000 (20000000 00000000) + nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000) + nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000) + nor. 000f423f, ffffffff => 00000000 (20000000 00000000) + nor. ffffffff, 00000000 => 00000000 (20000000 00000000) + nor. ffffffff, 000f423f => 00000000 (20000000 00000000) + nor. ffffffff, ffffffff => 00000000 (20000000 00000000) + + or. 00000000, 00000000 => 00000000 (20000000 00000000) + or. 00000000, 000f423f => 000f423f (40000000 00000000) + or. 00000000, ffffffff => ffffffff (80000000 00000000) + or. 000f423f, 00000000 => 000f423f (40000000 00000000) + or. 000f423f, 000f423f => 000f423f (40000000 00000000) + or. 000f423f, ffffffff => ffffffff (80000000 00000000) + or. ffffffff, 00000000 => ffffffff (80000000 00000000) + or. ffffffff, 000f423f => ffffffff (80000000 00000000) + or. ffffffff, ffffffff => ffffffff (80000000 00000000) + + orc. 00000000, 00000000 => ffffffff (80000000 00000000) + orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000) + orc. 00000000, ffffffff => 00000000 (20000000 00000000) + orc. 000f423f, 00000000 => ffffffff (80000000 00000000) + orc. 000f423f, 000f423f => ffffffff (80000000 00000000) + orc. 000f423f, ffffffff => 000f423f (40000000 00000000) + orc. ffffffff, 00000000 => ffffffff (80000000 00000000) + orc. ffffffff, 000f423f => ffffffff (80000000 00000000) + orc. ffffffff, ffffffff => ffffffff (80000000 00000000) + + xor. 00000000, 00000000 => 00000000 (20000000 00000000) + xor. 00000000, 000f423f => 000f423f (40000000 00000000) + xor. 00000000, ffffffff => ffffffff (80000000 00000000) + xor. 000f423f, 00000000 => 000f423f (40000000 00000000) + xor. 000f423f, 000f423f => 00000000 (20000000 00000000) + xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000) + xor. ffffffff, 00000000 => ffffffff (80000000 00000000) + xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000) + xor. ffffffff, ffffffff => 00000000 (20000000 00000000) + + slw. 00000000, 00000000 => 00000000 (20000000 00000000) + slw. 00000000, 000f423f => 00000000 (20000000 00000000) + slw. 00000000, ffffffff => 00000000 (20000000 00000000) + slw. 000f423f, 00000000 => 000f423f (40000000 00000000) + slw. 000f423f, 000f423f => 00000000 (20000000 00000000) + slw. 000f423f, ffffffff => 00000000 (20000000 00000000) + slw. ffffffff, 00000000 => ffffffff (80000000 00000000) + slw. ffffffff, 000f423f => 00000000 (20000000 00000000) + slw. ffffffff, ffffffff => 00000000 (20000000 00000000) + + sraw. 00000000, 00000000 => 00000000 (20000000 00000000) + sraw. 00000000, 000f423f => 00000000 (20000000 00000000) + sraw. 00000000, ffffffff => 00000000 (20000000 00000000) + sraw. 000f423f, 00000000 => 000f423f (40000000 00000000) + sraw. 000f423f, 000f423f => 00000000 (20000000 00000000) + sraw. 000f423f, ffffffff => 00000000 (20000000 00000000) + sraw. ffffffff, 00000000 => ffffffff (80000000 00000000) + sraw. ffffffff, 000f423f => ffffffff (80000000 20000000) + sraw. ffffffff, ffffffff => ffffffff (80000000 20000000) + + srw. 00000000, 00000000 => 00000000 (20000000 00000000) + srw. 00000000, 000f423f => 00000000 (20000000 00000000) + srw. 00000000, ffffffff => 00000000 (20000000 00000000) + srw. 000f423f, 00000000 => 000f423f (40000000 00000000) + srw. 000f423f, 000f423f => 00000000 (20000000 00000000) + srw. 000f423f, ffffffff => 00000000 (20000000 00000000) + srw. ffffffff, 00000000 => ffffffff (80000000 00000000) + srw. ffffffff, 000f423f => 00000000 (20000000 00000000) + srw. ffffffff, ffffffff => 00000000 (20000000 00000000) + +PPC integer compare insns (two args): + cmp 00000000, 00000000 => 00000000 (00200000 00000000) + cmp 00000000, 000f423f => 00000000 (00800000 00000000) + cmp 00000000, ffffffff => 00000000 (00400000 00000000) + cmp 000f423f, 00000000 => 00000000 (00400000 00000000) + cmp 000f423f, 000f423f => 00000000 (00200000 00000000) + cmp 000f423f, ffffffff => 00000000 (00400000 00000000) + cmp ffffffff, 00000000 => 00000000 (00800000 00000000) + cmp ffffffff, 000f423f => 00000000 (00800000 00000000) + cmp ffffffff, ffffffff => 00000000 (00200000 00000000) + + cmpl 00000000, 00000000 => 00000000 (00200000 00000000) + cmpl 00000000, 000f423f => 00000000 (00800000 00000000) + cmpl 00000000, ffffffff => 00000000 (00800000 00000000) + cmpl 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpl 000f423f, 000f423f => 00000000 (00200000 00000000) + cmpl 000f423f, ffffffff => 00000000 (00800000 00000000) + cmpl ffffffff, 00000000 => 00000000 (00400000 00000000) + cmpl ffffffff, 000f423f => 00000000 (00400000 00000000) + cmpl ffffffff, ffffffff => 00000000 (00200000 00000000) + +PPC integer compare with immediate insns (two args): + cmpi 00000000, 00000000 => 00000000 (00200000 00000000) + cmpi 00000000, 000003e7 => 00000000 (00800000 00000000) + cmpi 00000000, 0000ffff => 00000000 (00400000 00000000) + cmpi 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpi 000f423f, 000003e7 => 00000000 (00400000 00000000) + cmpi 000f423f, 0000ffff => 00000000 (00400000 00000000) + cmpi ffffffff, 00000000 => 00000000 (00800000 00000000) + cmpi ffffffff, 000003e7 => 00000000 (00800000 00000000) + cmpi ffffffff, 0000ffff => 00000000 (00200000 00000000) + + cmpli 00000000, 00000000 => 00000000 (00200000 00000000) + cmpli 00000000, 000003e7 => 00000000 (00800000 00000000) + cmpli 00000000, 0000ffff => 00000000 (00800000 00000000) + cmpli 000f423f, 00000000 => 00000000 (00400000 00000000) + cmpli 000f423f, 000003e7 => 00000000 (00400000 00000000) + cmpli 000f423f, 0000ffff => 00000000 (00400000 00000000) + cmpli ffffffff, 00000000 => 00000000 (00400000 00000000) + cmpli ffffffff, 000003e7 => 00000000 (00400000 00000000) + cmpli ffffffff, 0000ffff => 00000000 (00400000 00000000) + +PPC integer arith insns + with one register + one 16 bits immediate args: + addi 00000000, 00000000 => 00000000 (00000000 00000000) + addi 00000000, 000003e7 => 000003e7 (00000000 00000000) + addi 00000000, 0000ffff => ffffffff (00000000 00000000) + addi 000f423f, 00000000 => 000f423f (00000000 00000000) + addi 000f423f, 000003e7 => 000f4626 (00000000 00000000) + addi 000f423f, 0000ffff => 000f423e (00000000 00000000) + addi ffffffff, 00000000 => ffffffff (00000000 00000000) + addi ffffffff, 000003e7 => 000003e6 (00000000 00000000) + addi ffffffff, 0000ffff => fffffffe (00000000 00000000) + + addic 00000000, 00000000 => 00000000 (00000000 00000000) + addic 00000000, 000003e7 => 000003e7 (00000000 00000000) + addic 00000000, 0000ffff => ffffffff (00000000 00000000) + addic 000f423f, 00000000 => 000f423f (00000000 00000000) + addic 000f423f, 000003e7 => 000f4626 (00000000 00000000) + addic 000f423f, 0000ffff => 000f423e (00000000 20000000) + addic ffffffff, 00000000 => ffffffff (00000000 00000000) + addic ffffffff, 000003e7 => 000003e6 (00000000 20000000) + addic ffffffff, 0000ffff => fffffffe (00000000 20000000) + + addis 00000000, 00000000 => 00000000 (00000000 00000000) + addis 00000000, 000003e7 => 03e70000 (00000000 00000000) + addis 00000000, 0000ffff => ffff0000 (00000000 00000000) + addis 000f423f, 00000000 => 000f423f (00000000 00000000) + addis 000f423f, 000003e7 => 03f6423f (00000000 00000000) + addis 000f423f, 0000ffff => 000e423f (00000000 00000000) + addis ffffffff, 00000000 => ffffffff (00000000 00000000) + addis ffffffff, 000003e7 => 03e6ffff (00000000 00000000) + addis ffffffff, 0000ffff => fffeffff (00000000 00000000) + + mulli 00000000, 00000000 => 00000000 (00000000 00000000) + mulli 00000000, 000003e7 => 00000000 (00000000 00000000) + mulli 00000000, 0000ffff => 00000000 (00000000 00000000) + mulli 000f423f, 00000000 => 00000000 (00000000 00000000) + mulli 000f423f, 000003e7 => 3b8b83d9 (00000000 00000000) + mulli 000f423f, 0000ffff => fff0bdc1 (00000000 00000000) + mulli ffffffff, 00000000 => 00000000 (00000000 00000000) + mulli ffffffff, 000003e7 => fffffc19 (00000000 00000000) + mulli ffffffff, 0000ffff => 00000001 (00000000 00000000) + + subfic 00000000, 00000000 => 00000000 (00000000 20000000) + subfic 00000000, 000003e7 => 000003e7 (00000000 20000000) + subfic 00000000, 0000ffff => ffffffff (00000000 20000000) + subfic 000f423f, 00000000 => fff0bdc1 (00000000 00000000) + subfic 000f423f, 000003e7 => fff0c1a8 (00000000 00000000) + subfic 000f423f, 0000ffff => fff0bdc0 (00000000 20000000) + subfic ffffffff, 00000000 => 00000001 (00000000 00000000) + subfic ffffffff, 000003e7 => 000003e8 (00000000 00000000) + subfic ffffffff, 0000ffff => 00000000 (00000000 20000000) + +PPC integer arith insns + with one register + one 16 bits immediate args with flags update: + addic. 00000000, 00000000 => 00000000 (20000000 00000000) + addic. 00000000, 000003e7 => 000003e7 (40000000 00000000) + addic. 00000000, 0000ffff => ffffffff (80000000 00000000) + addic. 000f423f, 00000000 => 000f423f (40000000 00000000) + addic. 000f423f, 000003e7 => 000f4626 (40000000 00000000) + addic. 000f423f, 0000ffff => 000f423e (40000000 20000000) + addic. ffffffff, 00000000 => ffffffff (80000000 00000000) + addic. ffffffff, 000003e7 => 000003e6 (40000000 20000000) + addic. ffffffff, 0000ffff => fffffffe (80000000 20000000) + +PPC integer logical insns + with one register + one 16 bits immediate args: + ori 00000000, 00000000 => 00000000 (00000000 00000000) + ori 00000000, 000003e7 => 000003e7 (00000000 00000000) + ori 00000000, 0000ffff => 0000ffff (00000000 00000000) + ori 000f423f, 00000000 => 000f423f (00000000 00000000) + ori 000f423f, 000003e7 => 000f43ff (00000000 00000000) + ori 000f423f, 0000ffff => 000fffff (00000000 00000000) + ori ffffffff, 00000000 => ffffffff (00000000 00000000) + ori ffffffff, 000003e7 => ffffffff (00000000 00000000) + ori ffffffff, 0000ffff => ffffffff (00000000 00000000) + + oris 00000000, 00000000 => 00000000 (00000000 00000000) + oris 00000000, 000003e7 => 03e70000 (00000000 00000000) + oris 00000000, 0000ffff => ffff0000 (00000000 00000000) + oris 000f423f, 00000000 => 000f423f (00000000 00000000) + oris 000f423f, 000003e7 => 03ef423f (00000000 00000000) + oris 000f423f, 0000ffff => ffff423f (00000000 00000000) + oris ffffffff, 00000000 => ffffffff (00000000 00000000) + oris ffffffff, 000003e7 => ffffffff (00000000 00000000) + oris ffffffff, 0000ffff => ffffffff (00000000 00000000) + + xori 00000000, 00000000 => 00000000 (00000000 00000000) + xori 00000000, 000003e7 => 000003e7 (00000000 00000000) + xori 00000000, 0000ffff => 0000ffff (00000000 00000000) + xori 000f423f, 00000000 => 000f423f (00000000 00000000) + xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000) + xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000) + xori ffffffff, 00000000 => ffffffff (00000000 00000000) + xori ffffffff, 000003e7 => fffffc18 (00000000 00000000) + xori ffffffff, 0000ffff => ffff0000 (00000000 00000000) + + xoris 00000000, 00000000 => 00000000 (00000000 00000000) + xoris 00000000, 000003e7 => 03e70000 (00000000 00000000) + xoris 00000000, 0000ffff => ffff0000 (00000000 00000000) + xoris 000f423f, 00000000 => 000f423f (00000000 00000000) + xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000) + xoris 000f423f, 0000ffff => fff0423f (00000000 00000000) + xoris ffffffff, 00000000 => ffffffff (00000000 00000000) + xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000) + xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000) + +PPC integer logical insns + with one register + one 16 bits immediate args with flags update: + andi. 00000000, 00000000 => 00000000 (20000000 00000000) + andi. 00000000, 000003e7 => 00000000 (20000000 00000000) + andi. 00000000, 0000ffff => 00000000 (20000000 00000000) + andi. 000f423f, 00000000 => 00000000 (20000000 00000000) + andi. 000f423f, 000003e7 => 00000227 (40000000 00000000) + andi. 000f423f, 0000ffff => 0000423f (40000000 00000000) + andi. ffffffff, 00000000 => 00000000 (20000000 00000000) + andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000) + andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000) + + andis. 00000000, 00000000 => 00000000 (20000000 00000000) + andis. 00000000, 000003e7 => 00000000 (20000000 00000000) + andis. 00000000, 0000ffff => 00000000 (20000000 00000000) + andis. 000f423f, 00000000 => 00000000 (20000000 00000000) + andis. 000f423f, 000003e7 => 00070000 (40000000 00000000) + andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000) + andis. ffffffff, 00000000 => 00000000 (20000000 00000000) + andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000) + andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000) + +PPC condition register logical insns - two operands: + crand 00000000, 00000000 => ffff0000 (00000000 00000000) + crand 00000000, 000f423f => ffff0000 (00000000 00000000) + crand 00000000, ffffffff => ffff0000 (00000000 00000000) + crand 000f423f, 00000000 => ffff0000 (00000000 00000000) + crand 000f423f, 000f423f => ffff0000 (00000000 00000000) + crand 000f423f, ffffffff => ffff0000 (00000000 00000000) + crand ffffffff, 00000000 => ffff0000 (00000000 00000000) + crand ffffffff, 000f423f => ffff0000 (00000000 00000000) + crand ffffffff, ffffffff => ffff0000 (00000000 00000000) + + crandc 00000000, 00000000 => ffff0000 (00000000 00000000) + crandc 00000000, 000f423f => ffff0000 (00000000 00000000) + crandc 00000000, ffffffff => ffff0000 (00000000 00000000) + crandc 000f423f, 00000000 => ffff0000 (00000000 00000000) + crandc 000f423f, 000f423f => ffff0000 (00000000 00000000) + crandc 000f423f, ffffffff => ffff0000 (00000000 00000000) + crandc ffffffff, 00000000 => ffff0000 (00000000 00000000) + crandc ffffffff, 000f423f => ffff0000 (00000000 00000000) + crandc ffffffff, ffffffff => ffff0000 (00000000 00000000) + + creqv 00000000, 00000000 => ffff0000 (00004000 00000000) + creqv 00000000, 000f423f => ffff0000 (00004000 00000000) + creqv 00000000, ffffffff => ffff0000 (00004000 00000000) + creqv 000f423f, 00000000 => ffff0000 (00004000 00000000) + creqv 000f423f, 000f423f => ffff0000 (00004000 00000000) + creqv 000f423f, ffffffff => ffff0000 (00004000 00000000) + creqv ffffffff, 00000000 => ffff0000 (00004000 00000000) + creqv ffffffff, 000f423f => ffff0000 (00004000 00000000) + creqv ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crnand 00000000, 00000000 => ffff0000 (00004000 00000000) + crnand 00000000, 000f423f => ffff0000 (00004000 00000000) + crnand 00000000, ffffffff => ffff0000 (00004000 00000000) + crnand 000f423f, 00000000 => ffff0000 (00004000 00000000) + crnand 000f423f, 000f423f => ffff0000 (00004000 00000000) + crnand 000f423f, ffffffff => ffff0000 (00004000 00000000) + crnand ffffffff, 00000000 => ffff0000 (00004000 00000000) + crnand ffffffff, 000f423f => ffff0000 (00004000 00000000) + crnand ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crnor 00000000, 00000000 => ffff0000 (00004000 00000000) + crnor 00000000, 000f423f => ffff0000 (00004000 00000000) + crnor 00000000, ffffffff => ffff0000 (00004000 00000000) + crnor 000f423f, 00000000 => ffff0000 (00004000 00000000) + crnor 000f423f, 000f423f => ffff0000 (00004000 00000000) + crnor 000f423f, ffffffff => ffff0000 (00004000 00000000) + crnor ffffffff, 00000000 => ffff0000 (00004000 00000000) + crnor ffffffff, 000f423f => ffff0000 (00004000 00000000) + crnor ffffffff, ffffffff => ffff0000 (00004000 00000000) + + cror 00000000, 00000000 => ffff0000 (00000000 00000000) + cror 00000000, 000f423f => ffff0000 (00000000 00000000) + cror 00000000, ffffffff => ffff0000 (00000000 00000000) + cror 000f423f, 00000000 => ffff0000 (00000000 00000000) + cror 000f423f, 000f423f => ffff0000 (00000000 00000000) + cror 000f423f, ffffffff => ffff0000 (00000000 00000000) + cror ffffffff, 00000000 => ffff0000 (00000000 00000000) + cror ffffffff, 000f423f => ffff0000 (00000000 00000000) + cror ffffffff, ffffffff => ffff0000 (00000000 00000000) + + crorc 00000000, 00000000 => ffff0000 (00004000 00000000) + crorc 00000000, 000f423f => ffff0000 (00004000 00000000) + crorc 00000000, ffffffff => ffff0000 (00004000 00000000) + crorc 000f423f, 00000000 => ffff0000 (00004000 00000000) + crorc 000f423f, 000f423f => ffff0000 (00004000 00000000) + crorc 000f423f, ffffffff => ffff0000 (00004000 00000000) + crorc ffffffff, 00000000 => ffff0000 (00004000 00000000) + crorc ffffffff, 000f423f => ffff0000 (00004000 00000000) + crorc ffffffff, ffffffff => ffff0000 (00004000 00000000) + + crxor 00000000, 00000000 => ffff0000 (00000000 00000000) + crxor 00000000, 000f423f => ffff0000 (00000000 00000000) + crxor 00000000, ffffffff => ffff0000 (00000000 00000000) + crxor 000f423f, 00000000 => ffff0000 (00000000 00000000) + crxor 000f423f, 000f423f => ffff0000 (00000000 00000000) + crxor 000f423f, ffffffff => ffff0000 (00000000 00000000) + crxor ffffffff, 00000000 => ffff0000 (00000000 00000000) + crxor ffffffff, 000f423f => ffff0000 (00000000 00000000) + crxor ffffffff, ffffffff => ffff0000 (00000000 00000000) + +PPC integer arith insns with one arg and carry: + addme 00000000 => ffffffff (00000000 00000000) + addme 000f423f => 000f423e (00000000 20000000) + addme ffffffff => fffffffe (00000000 20000000) + addme 00000000 => 00000000 (00000000 20000000) + addme 000f423f => 000f423f (00000000 20000000) + addme ffffffff => ffffffff (00000000 20000000) + + addmeo 00000000 => ffffffff (00000000 00000000) + addmeo 000f423f => 000f423e (00000000 20000000) + addmeo ffffffff => fffffffe (00000000 20000000) + addmeo 00000000 => 00000000 (00000000 20000000) + addmeo 000f423f => 000f423f (00000000 20000000) + addmeo ffffffff => ffffffff (00000000 20000000) + + addze 00000000 => 00000000 (00000000 00000000) + addze 000f423f => 000f423f (00000000 00000000) + addze ffffffff => ffffffff (00000000 00000000) + addze 00000000 => 00000001 (00000000 00000000) + addze 000f423f => 000f4240 (00000000 00000000) + addze ffffffff => 00000000 (00000000 20000000) + + addzeo 00000000 => 00000000 (00000000 00000000) + addzeo 000f423f => 000f423f (00000000 00000000) + addzeo ffffffff => ffffffff (00000000 00000000) + addzeo 00000000 => 00000001 (00000000 00000000) + addzeo 000f423f => 000f4240 (00000000 00000000) + addzeo ffffffff => 00000000 (00000000 20000000) + + subfme 00000000 => fffffffe (00000000 20000000) + subfme 000f423f => fff0bdbf (00000000 20000000) + subfme ffffffff => ffffffff (00000000 00000000) + subfme 00000000 => ffffffff (00000000 20000000) + subfme 000f423f => fff0bdc0 (00000000 20000000) + subfme ffffffff => 00000000 (00000000 20000000) + + subfmeo 00000000 => fffffffe (00000000 20000000) + subfmeo 000f423f => fff0bdbf (00000000 20000000) + subfmeo ffffffff => ffffffff (00000000 00000000) + subfmeo 00000000 => ffffffff (00000000 20000000) + subfmeo 000f423f => fff0bdc0 (00000000 20000000) + subfmeo ffffffff => 00000000 (00000000 20000000) + + subfze 00000000 => ffffffff (00000000 00000000) + subfze 000f423f => fff0bdc0 (00000000 00000000) + subfze ffffffff => 00000000 (00000000 00000000) + subfze 00000000 => 00000000 (00000000 20000000) + subfze 000f423f => fff0bdc1 (00000000 00000000) + subfze ffffffff => 00000001 (00000000 00000000) + + subfzeo 00000000 => ffffffff (00000000 00000000) + subfzeo 000f423f => fff0bdc0 (00000000 00000000) + subfzeo ffffffff => 00000000 (00000000 00000000) + subfzeo 00000000 => 00000000 (00000000 20000000) + subfzeo 000f423f => fff0bdc1 (00000000 00000000) + subfzeo ffffffff => 00000001 (00000000 00000000) + +PPC integer arith insns with one arg and carry with flags update: + addme. 00000000 => ffffffff (80000000 00000000) + addme. 000f423f => 000f423e (40000000 20000000) + addme. ffffffff => fffffffe (80000000 20000000) + addme. 00000000 => 00000000 (20000000 20000000) + addme. 000f423f => 000f423f (40000000 20000000) + addme. ffffffff => ffffffff (80000000 20000000) + + addmeo. 00000000 => ffffffff (80000000 00000000) + addmeo. 000f423f => 000f423e (40000000 20000000) + addmeo. ffffffff => fffffffe (80000000 20000000) + addmeo. 00000000 => 00000000 (20000000 20000000) + addmeo. 000f423f => 000f423f (40000000 20000000) + addmeo. ffffffff => ffffffff (80000000 20000000) + + addze. 00000000 => 00000000 (20000000 00000000) + addze. 000f423f => 000f423f (40000000 00000000) + addze. ffffffff => ffffffff (80000000 00000000) + addze. 00000000 => 00000001 (40000000 00000000) + addze. 000f423f => 000f4240 (40000000 00000000) + addze. ffffffff => 00000000 (20000000 20000000) + + addzeo. 00000000 => 00000000 (20000000 00000000) + addzeo. 000f423f => 000f423f (40000000 00000000) + addzeo. ffffffff => ffffffff (80000000 00000000) + addzeo. 00000000 => 00000001 (40000000 00000000) + addzeo. 000f423f => 000f4240 (40000000 00000000) + addzeo. ffffffff => 00000000 (20000000 20000000) + + subfme. 00000000 => fffffffe (80000000 20000000) + subfme. 000f423f => fff0bdbf (80000000 20000000) + subfme. ffffffff => ffffffff (80000000 00000000) + subfme. 00000000 => ffffffff (80000000 20000000) + subfme. 000f423f => fff0bdc0 (80000000 20000000) + subfme. ffffffff => 00000000 (20000000 20000000) + + subfmeo. 00000000 => fffffffe (80000000 20000000) + subfmeo. 000f423f => fff0bdbf (80000000 20000000) + subfmeo. ffffffff => ffffffff (80000000 00000000) + subfmeo. 00000000 => ffffffff (80000000 20000000) + subfmeo. 000f423f => fff0bdc0 (80000000 20000000) + subfmeo. ffffffff => 00000000 (20000000 20000000) + + subfze. 00000000 => ffffffff (80000000 00000000) + subfze. 000f423f => fff0bdc0 (80000000 00000000) + subfze. ffffffff => 00000000 (20000000 00000000) + subfze. 00000000 => 00000000 (20000000 20000000) + subfze. 000f423f => fff0bdc1 (80000000 00000000) + subfze. ffffffff => 00000001 (40000000 00000000) + + subfzeo. 00000000 => ffffffff (80000000 00000000) + subfzeo. 000f423f => fff0bdc0 (80000000 00000000) + subfzeo. ffffffff => 00000000 (20000000 00000000) + subfzeo. 00000000 => 00000000 (20000000 20000000) + subfzeo. 000f423f => fff0bdc1 (80000000 00000000) + subfzeo. ffffffff => 00000001 (40000000 00000000) + +PPC integer logical insns with one arg: + cntlzw 00000000 => 00000020 (00000000 00000000) + cntlzw 000f423f => 0000000c (00000000 00000000) + cntlzw ffffffff => 00000000 (00000000 00000000) + + extsb 00000000 => 00000000 (00000000 00000000) + extsb 000f423f => 0000003f (00000000 00000000) + extsb ffffffff => ffffffff (00000000 00000000) + + extsh 00000000 => 00000000 (00000000 00000000) + extsh 000f423f => 0000423f (00000000 00000000) + extsh ffffffff => ffffffff (00000000 00000000) + + neg 00000000 => 00000000 (00000000 00000000) + neg 000f423f => fff0bdc1 (00000000 00000000) + neg ffffffff => 00000001 (00000000 00000000) + + nego 00000000 => 00000000 (00000000 00000000) + nego 000f423f => fff0bdc1 (00000000 00000000) + nego ffffffff => 00000001 (00000000 00000000) + +PPC integer logical insns with one arg with flags update: + cntlzw. 00000000 => 00000020 (40000000 00000000) + cntlzw. 000f423f => 0000000c (40000000 00000000) + cntlzw. ffffffff => 00000000 (20000000 00000000) + + extsb. 00000000 => 00000000 (20000000 00000000) + extsb. 000f423f => 0000003f (40000000 00000000) + extsb. ffffffff => ffffffff (80000000 00000000) + + extsh. 00000000 => 00000000 (20000000 00000000) + extsh. 000f423f => 0000423f (40000000 00000000) + extsh. ffffffff => ffffffff (80000000 00000000) + + neg. 00000000 => 00000000 (20000000 00000000) + neg. 000f423f => fff0bdc1 (80000000 00000000) + neg. ffffffff => 00000001 (40000000 00000000) + + nego. 00000000 => 00000000 (20000000 00000000) + nego. 000f423f => fff0bdc1 (80000000 00000000) + nego. ffffffff => 00000001 (40000000 00000000) + +PPC logical insns with special forms: + rlwimi 00000000, 0, 0, 0 => 00000001 (00000000 00000000) + rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000) + rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000) + rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000) + rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000) + rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000) + rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000) + rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000) + rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000) + rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000) + rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000) + rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000) + rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000) + rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000) + + rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000) + rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000) + rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000) + rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000) + rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000) + rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000) + rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000) + rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000) + rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000) + rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000) + rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000) + rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000) + rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000) + rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000) + rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000) + rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000) + rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000) + rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000) + + rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000) + rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000) + rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000) + rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000) + rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000) + rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000) + rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000) + rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000) + rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000) + rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000) + rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000) + rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000) + rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000) + rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000) + rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000) + rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000) + rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000) + rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000) + + srawi 00000000, 0 => 00000000 (00000000 00000000) + srawi 00000000, 31 => 00000000 (00000000 00000000) + srawi 000f423f, 0 => 000f423f (00000000 00000000) + srawi 000f423f, 31 => 00000000 (00000000 00000000) + srawi ffffffff, 0 => ffffffff (00000000 00000000) + srawi ffffffff, 31 => ffffffff (00000000 20000000) + + mfcr (00000000) => 00000000 (00000000 00000000) + mfcr (000f423f) => 000f423f (000f423f 00000000) + mfcr (ffffffff) => ffffffff (ffffffff 00000000) + + mfspr 1 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 1 (000f423f) => 0000003f (00000000 0000003f, 00000000, 00000000) + mfspr 1 (ffffffff) => e000007f (00000000 e000007f, 00000000, 00000000) + mfspr 8 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 8 (000f423f) => 000f423f (00000000 00000000, 000f423f, 00000000) + mfspr 8 (ffffffff) => ffffffff (00000000 00000000, ffffffff, 00000000) + mfspr 9 (00000000) => 00000000 (00000000 00000000, 00000000, 00000000) + mfspr 9 (000f423f) => 000f423f (00000000 00000000, 00000000, 000f423f) + mfspr 9 (ffffffff) => ffffffff (00000000 00000000, 00000000, ffffffff) + + mtspr 1, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 1, 000f423f => (00000000 0000003f, 00000000, 00000000) + mtspr 1, ffffffff => (00000000 e000007f, 00000000, 00000000) + mtspr 8, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 8, 000f423f => (00000000 00000000, 000f423f, 00000000) + mtspr 8, ffffffff => (00000000 00000000, ffffffff, 00000000) + mtspr 9, 00000000 => (00000000 00000000, 00000000, 00000000) + mtspr 9, 000f423f => (00000000 00000000, 00000000, 000f423f) + mtspr 9, ffffffff => (00000000 00000000, 00000000, ffffffff) + +PPC logical insns with special forms with flags update: + rlwimi. 00000000, 0, 0, 0 => 7fffffff (40000000 00000000) + rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000) + rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000) + rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000) + rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000) + rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000) + rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000) + rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000) + rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000) + rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000) + rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000) + rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000) + + rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000) + rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000) + rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000) + rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000) + rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000) + rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000) + rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000) + rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000) + rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000) + rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000) + rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000) + rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000) + rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000) + rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000) + rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000) + rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000) + rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000) + rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000) + + rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000) + rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000) + rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000) + rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000) + rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000) + rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000) + rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000) + rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000) + rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000) + rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000) + rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000) + rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000) + rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000) + rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000) + rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000) + rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000) + rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000) + rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000) + + srawi. 00000000, 0 => 00000000 (20000000 00000000) + srawi. 00000000, 31 => 00000000 (20000000 00000000) + srawi. 000f423f, 0 => 000f423f (40000000 00000000) + srawi. 000f423f, 31 => 00000000 (20000000 00000000) + srawi. ffffffff, 0 => ffffffff (80000000 00000000) + srawi. ffffffff, 31 => ffffffff (80000000 20000000) + + mcrf 0, 0 (00000000) => (00000000 00000000) + mcrf 0, 7 (00000000) => (00000000 00000000) + mcrf 7, 0 (00000000) => (00000000 00000000) + mcrf 7, 7 (00000000) => (00000000 00000000) + mcrf 0, 0 (000f423f) => (000f423f 00000000) + mcrf 0, 7 (000f423f) => (f00f423f 00000000) + mcrf 7, 0 (000f423f) => (000f4230 00000000) + mcrf 7, 7 (000f423f) => (000f423f 00000000) + mcrf 0, 0 (ffffffff) => (ffffffff 00000000) + mcrf 0, 7 (ffffffff) => (ffffffff 00000000) + mcrf 7, 0 (ffffffff) => (ffffffff 00000000) + mcrf 7, 7 (ffffffff) => (ffffffff 00000000) + + mcrxr 0 (00000000) => (00000000 00000000) + mcrxr 1 (00000000) => (00000000 00000000) + mcrxr 2 (00000000) => (00000000 00000000) + mcrxr 3 (00000000) => (00000000 00000000) + mcrxr 4 (00000000) => (00000000 00000000) + mcrxr 5 (00000000) => (00000000 00000000) + mcrxr 6 (00000000) => (00000000 00000000) + mcrxr 7 (00000000) => (00000000 00000000) + mcrxr 0 (10000000) => (00000000 00000000) + mcrxr 1 (10000000) => (00000000 00000000) + mcrxr 2 (10000000) => (00000000 00000000) + mcrxr 3 (10000000) => (00000000 00000000) + mcrxr 4 (10000000) => (00000000 00000000) + mcrxr 5 (10000000) => (00000000 00000000) + mcrxr 6 (10000000) => (00000000 00000000) + mcrxr 7 (10000000) => (00000000 00000000) + mcrxr 0 (20000000) => (20000000 00000000) + mcrxr 1 (20000000) => (02000000 00000000) + mcrxr 2 (20000000) => (00200000 00000000) + mcrxr 3 (20000000) => (00020000 00000000) + mcrxr 4 (20000000) => (00002000 00000000) + mcrxr 5 (20000000) => (00000200 00000000) + mcrxr 6 (20000000) => (00000020 00000000) + mcrxr 7 (20000000) => (00000002 00000000) + mcrxr 0 (30000000) => (20000000 00000000) + mcrxr 1 (30000000) => (02000000 00000000) + mcrxr 2 (30000000) => (00200000 00000000) + mcrxr 3 (30000000) => (00020000 00000000) + mcrxr 4 (30000000) => (00002000 00000000) + mcrxr 5 (30000000) => (00000200 00000000) + mcrxr 6 (30000000) => (00000020 00000000) + mcrxr 7 (30000000) => (00000002 00000000) + mcrxr 0 (40000000) => (40000000 00000000) + mcrxr 1 (40000000) => (04000000 00000000) + mcrxr 2 (40000000) => (00400000 00000000) + mcrxr 3 (40000000) => (00040000 00000000) + mcrxr 4 (40000000) => (00004000 00000000) + mcrxr 5 (40000000) => (00000400 00000000) + mcrxr 6 (40000000) => (00000040 00000000) + mcrxr 7 (40000000) => (00000004 00000000) + mcrxr 0 (50000000) => (40000000 00000000) + mcrxr 1 (50000000) => (04000000 00000000) + mcrxr 2 (50000000) => (00400000 00000000) + mcrxr 3 (50000000) => (00040000 00000000) + mcrxr 4 (50000000) => (00004000 00000000) + mcrxr 5 (50000000) => (00000400 00000000) + mcrxr 6 (50000000) => (00000040 00000000) + mcrxr 7 (50000000) => (00000004 00000000) + mcrxr 0 (60000000) => (60000000 00000000) + mcrxr 1 (60000000) => (06000000 00000000) + mcrxr 2 (60000000) => (00600000 00000000) + mcrxr 3 (60000000) => (00060000 00000000) + mcrxr 4 (60000000) => (00006000 00000000) + mcrxr 5 (60000000) => (00000600 00000000) + mcrxr 6 (60000000) => (00000060 00000000) + mcrxr 7 (60000000) => (00000006 00000000) + mcrxr 0 (70000000) => (60000000 00000000) + mcrxr 1 (70000000) => (06000000 00000000) + mcrxr 2 (70000000) => (00600000 00000000) + mcrxr 3 (70000000) => (00060000 00000000) + mcrxr 4 (70000000) => (00006000 00000000) + mcrxr 5 (70000000) => (00000600 00000000) + mcrxr 6 (70000000) => (00000060 00000000) + mcrxr 7 (70000000) => (00000006 00000000) + mcrxr 0 (80000000) => (80000000 00000000) + mcrxr 1 (80000000) => (08000000 00000000) + mcrxr 2 (80000000) => (00800000 00000000) + mcrxr 3 (80000000) => (00080000 00000000) + mcrxr 4 (80000000) => (00008000 00000000) + mcrxr 5 (80000000) => (00000800 00000000) + mcrxr 6 (80000000) => (00000080 00000000) + mcrxr 7 (80000000) => (00000008 00000000) + mcrxr 0 (90000000) => (80000000 00000000) + mcrxr 1 (90000000) => (08000000 00000000) + mcrxr 2 (90000000) => (00800000 00000000) + mcrxr 3 (90000000) => (00080000 00000000) + mcrxr 4 (90000000) => (00008000 00000000) + mcrxr 5 (90000000) => (00000800 00000000) + mcrxr 6 (90000000) => (00000080 00000000) + mcrxr 7 (90000000) => (00000008 00000000) + mcrxr 0 (a0000000) => (a0000000 00000000) + mcrxr 1 (a0000000) => (0a000000 00000000) + mcrxr 2 (a0000000) => (00a00000 00000000) + mcrxr 3 (a0000000) => (000a0000 00000000) + mcrxr 4 (a0000000) => (0000a000 00000000) + mcrxr 5 (a0000000) => (00000a00 00000000) + mcrxr 6 (a0000000) => (000000a0 00000000) + mcrxr 7 (a0000000) => (0000000a 00000000) + mcrxr 0 (b0000000) => (a0000000 00000000) + mcrxr 1 (b0000000) => (0a000000 00000000) + mcrxr 2 (b0000000) => (00a00000 00000000) + mcrxr 3 (b0000000) => (000a0000 00000000) + mcrxr 4 (b0000000) => (0000a000 00000000) + mcrxr 5 (b0000000) => (00000a00 00000000) + mcrxr 6 (b0000000) => (000000a0 00000000) + mcrxr 7 (b0000000) => (0000000a 00000000) + mcrxr 0 (c0000000) => (c0000000 00000000) + mcrxr 1 (c0000000) => (0c000000 00000000) + mcrxr 2 (c0000000) => (00c00000 00000000) + mcrxr 3 (c0000000) => (000c0000 00000000) + mcrxr 4 (c0000000) => (0000c000 00000000) + mcrxr 5 (c0000000) => (00000c00 00000000) + mcrxr 6 (c0000000) => (000000c0 00000000) + mcrxr 7 (c0000000) => (0000000c 00000000) + mcrxr 0 (d0000000) => (c0000000 00000000) + mcrxr 1 (d0000000) => (0c000000 00000000) + mcrxr 2 (d0000000) => (00c00000 00000000) + mcrxr 3 (d0000000) => (000c0000 00000000) + mcrxr 4 (d0000000) => (0000c000 00000000) + mcrxr 5 (d0000000) => (00000c00 00000000) + mcrxr 6 (d0000000) => (000000c0 00000000) + mcrxr 7 (d0000000) => (0000000c 00000000) + mcrxr 0 (e0000000) => (e0000000 00000000) + mcrxr 1 (e0000000) => (0e000000 00000000) + mcrxr 2 (e0000000) => (00e00000 00000000) + mcrxr 3 (e0000000) => (000e0000 00000000) + mcrxr 4 (e0000000) => (0000e000 00000000) + mcrxr 5 (e0000000) => (00000e00 00000000) + mcrxr 6 (e0000000) => (000000e0 00000000) + mcrxr 7 (e0000000) => (0000000e 00000000) + mcrxr 0 (f0000000) => (e0000000 00000000) + mcrxr 1 (f0000000) => (0e000000 00000000) + mcrxr 2 (f0000000) => (00e00000 00000000) + mcrxr 3 (f0000000) => (000e0000 00000000) + mcrxr 4 (f0000000) => (0000e000 00000000) + mcrxr 5 (f0000000) => (00000e00 00000000) + mcrxr 6 (f0000000) => (000000e0 00000000) + mcrxr 7 (f0000000) => (0000000e 00000000) + + mtcrf 0, 00000000 => (00000000 00000000) + mtcrf 99, 00000000 => (00000000 00000000) + mtcrf 198, 00000000 => (00000000 00000000) + mtcrf 0, 000f423f => (00000000 00000000) + mtcrf 99, 000f423f => (0000003f 00000000) + mtcrf 198, 000f423f => (00000230 00000000) + mtcrf 0, ffffffff => (00000000 00000000) + mtcrf 99, ffffffff => (0ff000ff 00000000) + mtcrf 198, ffffffff => (ff000ff0 00000000) + +PPC integer load insns + with one register + one 16 bits immediate args with flags update: + lbz 0, (00000000) => 00000000, (00000000 00000000) + lbz 4, (000f423f) => 00000000, (00000000 00000000) + lbz 8, (ffffffff) => 000000ff, (00000000 00000000) + lbz -8, (00000000) => 00000000 (00000000 00000000) + lbz -4, (000f423f) => 00000000 (00000000 00000000) + lbz 0, (ffffffff) => 000000ff (00000000 00000000) + + lbzu 0, (00000000) => 00000000, (00000000 00000000) + lbzu 4, (000f423f) => 00000000, (00000000 00000000) + lbzu 8, (ffffffff) => 000000ff, (00000000 00000000) + lbzu -8, (00000000) => 00000000 (00000000 00000000) + lbzu -4, (000f423f) => 00000000 (00000000 00000000) + lbzu 0, (ffffffff) => 000000ff (00000000 00000000) + + lha 0, (00000000) => 00000000, (00000000 00000000) + lha 4, (000f423f) => 0000000f, (00000000 00000000) + lha 8, (ffffffff) => ffffffff, (00000000 00000000) + lha -8, (00000000) => 00000000 (00000000 00000000) + lha -4, (000f423f) => 0000000f (00000000 00000000) + lha 0, (ffffffff) => ffffffff (00000000 00000000) + + lhau 0, (00000000) => 00000000, (00000000 00000000) + lhau 4, (000f423f) => 0000000f, (00000000 00000000) + lhau 8, (ffffffff) => ffffffff, (00000000 00000000) + lhau -8, (00000000) => 00000000 (00000000 00000000) + lhau -4, (000f423f) => 0000000f (00000000 00000000) + lhau 0, (ffffffff) => ffffffff (00000000 00000000) + + lhz 0, (00000000) => 00000000, (00000000 00000000) + lhz 4, (000f423f) => 0000000f, (00000000 00000000) + lhz 8, (ffffffff) => 0000ffff, (00000000 00000000) + lhz -8, (00000000) => 00000000 (00000000 00000000) + lhz -4, (000f423f) => 0000000f (00000000 00000000) + lhz 0, (ffffffff) => 0000ffff (00000000 00000000) + + lhzu 0, (00000000) => 00000000, (00000000 00000000) + lhzu 4, (000f423f) => 0000000f, (00000000 00000000) + lhzu 8, (ffffffff) => 0000ffff, (00000000 00000000) + lhzu -8, (00000000) => 00000000 (00000000 00000000) + lhzu -4, (000f423f) => 0000000f (00000000 00000000) + lhzu 0, (ffffffff) => 0000ffff (00000000 00000000) + + lwz 0, (00000000) => 00000000, (00000000 00000000) + lwz 4, (000f423f) => 000f423f, (00000000 00000000) + lwz 8, (ffffffff) => ffffffff, (00000000 00000000) + lwz -8, (00000000) => 00000000 (00000000 00000000) + lwz -4, (000f423f) => 000f423f (00000000 00000000) + lwz 0, (ffffffff) => ffffffff (00000000 00000000) + + lwzu 0, (00000000) => 00000000, (00000000 00000000) + lwzu 4, (000f423f) => 000f423f, (00000000 00000000) + lwzu 8, (ffffffff) => ffffffff, (00000000 00000000) + lwzu -8, (00000000) => 00000000 (00000000 00000000) + lwzu -4, (000f423f) => 000f423f (00000000 00000000) + lwzu 0, (ffffffff) => ffffffff (00000000 00000000) + +PPC integer load insns with two register args: + lbzx 0 (00000000) => 00000000 (00000000 00000000) + lbzx 4 (000f423f) => 00000000 (00000000 00000000) + lbzx 8 (ffffffff) => 000000ff (00000000 00000000) + + lbzux 0 (00000000) => 00000000 (00000000 00000000) + lbzux 4 (000f423f) => 00000000 (00000000 00000000) + lbzux 8 (ffffffff) => 000000ff (00000000 00000000) + + lhax 0 (00000000) => 00000000 (00000000 00000000) + lhax 4 (000f423f) => 0000000f (00000000 00000000) + lhax 8 (ffffffff) => ffffffff (00000000 00000000) + + lhaux 0 (00000000) => 00000000 (00000000 00000000) + lhaux 4 (000f423f) => 0000000f (00000000 00000000) + lhaux 8 (ffffffff) => ffffffff (00000000 00000000) + + lhzx 0 (00000000) => 00000000 (00000000 00000000) + lhzx 4 (000f423f) => 0000000f (00000000 00000000) + lhzx 8 (ffffffff) => 0000ffff (00000000 00000000) + + lhzux 0 (00000000) => 00000000 (00000000 00000000) + lhzux 4 (000f423f) => 0000000f (00000000 00000000) + lhzux 8 (ffffffff) => 0000ffff (00000000 00000000) + + lwzx 0 (00000000) => 00000000 (00000000 00000000) + lwzx 4 (000f423f) => 000f423f (00000000 00000000) + lwzx 8 (ffffffff) => ffffffff (00000000 00000000) + + lwzux 0 (00000000) => 00000000 (00000000 00000000) + lwzux 4 (000f423f) => 000f423f (00000000 00000000) + lwzux 8 (ffffffff) => ffffffff (00000000 00000000) + +PPC integer store insns + with one register + one 16 bits immediate args with flags update: + stb 00000000, 0 => 00000000, (00000000 00000000) + stb 000f423f, 4 => 3f000000, (00000000 00000000) + stb ffffffff, 8 => ff000000, (00000000 00000000) + stb 00000000, -8 => 00000000, (00000000 00000000) + stb 000f423f, -4 => 3f000000, (00000000 00000000) + stb ffffffff, 0 => ff000000, (00000000 00000000) + + stbu 00000000, 0 => 00000000, (00000000 00000000) + stbu 000f423f, 4 => 3f000000, (00000000 00000000) + stbu ffffffff, 8 => ff000000, (00000000 00000000) + stbu 00000000, -8 => 00000000, (00000000 00000000) + stbu 000f423f, -4 => 3f000000, (00000000 00000000) + stbu ffffffff, 0 => ff000000, (00000000 00000000) + + sth 00000000, 0 => 00000000, (00000000 00000000) + sth 000f423f, 4 => 423f0000, (00000000 00000000) + sth ffffffff, 8 => ffff0000, (00000000 00000000) + sth 00000000, -8 => 00000000, (00000000 00000000) + sth 000f423f, -4 => 423f0000, (00000000 00000000) + sth ffffffff, 0 => ffff0000, (00000000 00000000) + + sthu 00000000, 0 => 00000000, (00000000 00000000) + sthu 000f423f, 4 => 423f0000, (00000000 00000000) + sthu ffffffff, 8 => ffff0000, (00000000 00000000) + sthu 00000000, -8 => 00000000, (00000000 00000000) + sthu 000f423f, -4 => 423f0000, (00000000 00000000) + sthu ffffffff, 0 => ffff0000, (00000000 00000000) + + stw 00000000, 0 => 00000000, (00000000 00000000) + stw 000f423f, 4 => 000f423f, (00000000 00000000) + stw ffffffff, 8 => ffffffff, (00000000 00000000) + stw 00000000, -8 => 00000000, (00000000 00000000) + stw 000f423f, -4 => 000f423f, (00000000 00000000) + stw ffffffff, 0 => ffffffff, (00000000 00000000) + + stwu 00000000, 0 => 00000000, (00000000 00000000) + stwu 000f423f, 4 => 000f423f, (00000000 00000000) + stwu ffffffff, 8 => ffffffff, (00000000 00000000) + stwu 00000000, -8 => 00000000, (00000000 00000000) + stwu 000f423f, -4 => 000f423f, (00000000 00000000) + stwu ffffffff, 0 => ffffffff, (00000000 00000000) + +PPC integer store insns with three register args: + stbx 00000000, 0 => 00000000, (00000000 00000000) + stbx 000f423f, 4 => 3f000000, (00000000 00000000) + stbx ffffffff, 8 => ff000000, (00000000 00000000) + + stbux 00000000, 0 => 00000000, (00000000 00000000) + stbux 000f423f, 4 => 3f000000, (00000000 00000000) + stbux ffffffff, 8 => ff000000, (00000000 00000000) + + sthx 00000000, 0 => 00000000, (00000000 00000000) + sthx 000f423f, 4 => 423f0000, (00000000 00000000) + sthx ffffffff, 8 => ffff0000, (00000000 00000000) + + sthux 00000000, 0 => 00000000, (00000000 00000000) + sthux 000f423f, 4 => 423f0000, (00000000 00000000) + sthux ffffffff, 8 => ffff0000, (00000000 00000000) + + stwx 00000000, 0 => 00000000, (00000000 00000000) + stwx 000f423f, 4 => 000f423f, (00000000 00000000) + stwx ffffffff, 8 => ffffffff, (00000000 00000000) + + stwux 00000000, 0 => 00000000, (00000000 00000000) + stwux 000f423f, 4 => 000f423f, (00000000 00000000) + stwux ffffffff, 8 => ffffffff, (00000000 00000000) + +PPC altivec integer arith insns with three args: + vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000) + vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000) + vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000) + vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000) + vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000) + vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000) + vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000) + vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000) + + vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000) + vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000) + vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000) + vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000) + vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000) + vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000) + vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000) + vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000) + + vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000) + vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000) + vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000) + vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000) + vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000) + vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000) + vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000) + vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000) + + vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000) + vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000) + vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000) + vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) + vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000) + vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) + vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000) + vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000) + + vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000) + vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000) + vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) + vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000) + vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) + vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000) + vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000) + vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000) + + vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000) + vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000) + vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) + vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) + vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) + vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) + vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000) + vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000) + + vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000) + vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000) + vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) + vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000) + vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) + vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000) + vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000) + vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000) + + vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000) + vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000) + vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000) + vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) + vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000) + vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000) + vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000) + vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000) + + vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000) + vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000) + vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) + vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) + vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) + vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) + vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000) + vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000) + +PPC altivec integer logical insns with three args: + vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000) + vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000) + vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000) + vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000) + vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000) + vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000) + vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000) + vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000) + + vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) + vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) + vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) + vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) + vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) + vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) + vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) + vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) + +PPC altivec integer arith insns with two args: + vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) + vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) + vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000) + + vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) + vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) + vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000) + + vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) + vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) + vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000) + + vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000) + vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000) + vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) + vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) + vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) + vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) + vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) + vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) + vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000) + + vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) + vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) + vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000) + + vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) + vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) + vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000) + + vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vaddcuw: => 00000000 00000000 00000000 00000000 (00000000) + vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddcuw: => 00000000 00000000 00000001 00000001 (00000000) + vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vaddcuw: => 00000000 00000000 00000001 00000001 (00000000) + vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vaddcuw: => 00000001 00000001 00000001 00000001 (00000000) + + vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsububm: => 00000000 00000000 00000000 00000000 (00000000) + vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsububm: => 10101010 10101010 10101010 10101010 (00000000) + vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsububm: => 00000000 00000000 00000000 00000000 (00000000) + + vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubuhm: => 00000000 00000000 00000000 00000000 (00000000) + vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000) + vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuhm: => 00000000 00000000 00000000 00000000 (00000000) + + vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubuwm: => 00000000 00000000 00000000 00000000 (00000000) + vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000) + vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuwm: => 00000000 00000000 00000000 00000000 (00000000) + + vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsububs: => 00000000 00000000 00000000 00000000 (00000000) + vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsububs: => 00000000 00000000 00000000 00000000 (00000000) + vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsububs: => 00000000 00000000 00000000 00000000 (00000000) + + vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) + vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) + vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) + + vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubuws: => 00000000 00000000 00000000 00000000 (00000000) + vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuws: => 00000000 00000000 00000000 00000000 (00000000) + vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubuws: => 00000000 00000000 00000000 00000000 (00000000) + + vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubsbs: => 00000000 00000000 00000000 00000000 (00000000) + vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubsbs: => 10101010 10101010 10101010 10101010 (00000000) + vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubsbs: => 00000000 00000000 00000000 00000000 (00000000) + + vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubshs: => 00000000 00000000 00000000 00000000 (00000000) + vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000) + vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubshs: => 00000000 00000000 00000000 00000000 (00000000) + + vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubsws: => 00000000 00000000 00000000 00000000 (00000000) + vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000) + vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubsws: => 00000000 00000000 00000000 00000000 (00000000) + + vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) + vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubcuw: => 00000000 00000000 00000000 00000000 (00000000) + vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) + vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) + + vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000) + vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000) + vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000) + vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000) + + vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000) + vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000) + vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000) + vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000) + + vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000) + vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000) + vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000) + vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulosb: => 00c40090 00640040 00240010 00090001 (00000000) + + vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000) + vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000) + vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000) + vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulosh: => 00912090 00408040 00102010 00010201 (00000000) + + vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000) + vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000) + vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000) + vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000) + + vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000) + vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000) + vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000) + vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000) + + vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000) + vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000) + vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000) + vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000) + + vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000) + vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000) + vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000) + vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000) + + vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsumsws: => 00000000 00000000 00000000 2b2c3136 (00000000) + vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsumsws: => 00000000 00000000 00000000 1c1d2226 (00000000) + vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsumsws: => 00000000 00000000 00000000 eeeff4f6 (00000000) + vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsumsws: => 00000000 00000000 00000000 dfe0e5e6 (00000000) + + vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsum2sws: => 00000000 0b0e1114 00000000 2524272a (00000000) + vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum2sws: => 00000000 fbff0204 00000000 1615181a (00000000) + vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsum2sws: => 00000000 eceff2f4 00000000 0706090a (00000000) + vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum2sws: => 00000000 dde0e3e4 00000000 f7f6f9fa (00000000) + + vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000) + vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000) + vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000) + vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000) + + vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000) + vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000) + vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000) + vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000) + + vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000) + vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000) + vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000) + vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000) + + vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) + vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000) + vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000) + vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000) + vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000) + vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000) + vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000) + vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + +PPC altivec integer logical insns with two args: + vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + + vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vxor: => 00000000 00000000 00000000 00000000 (00000000) + vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vxor: => 00000000 00000000 00000000 00000000 (00000000) + + vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vandc: => 00000000 00000000 00000000 00000000 (00000000) + vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vandc: => 00000000 00000000 00000000 00000000 (00000000) + vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vandc: => 00000000 00000000 00000000 00000000 (00000000) + + vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000) + vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) + vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) + vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) + + vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000) + vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000) + vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000) + vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000) + + vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000) + vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000) + vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000) + vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000) + + vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000) + vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000) + vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000) + vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000) + + vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vslb: => 02081840 a0808008 122858c0 80a08080 (00000000) + vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslb: => 02081840 a0808008 122858c0 80a08080 (00000000) + vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000) + vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000) + + vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vslh: => 04083040 41800800 2800c000 a0008000 (00000000) + vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslh: => 04083040 41800800 2800c000 a0008000 (00000000) + vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000) + vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000) + + vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vslw: => 10203040 06070800 a0b0c000 87078000 (00000000) + vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslw: => 30400000 08000000 c0000000 80000000 (00000000) + vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000) + vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslw: => 3f400000 f8000000 c0000000 80000000 (00000000) + + vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsrb: => 00000000 00000008 04020100 00000000 (00000000) + vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrb: => 00000000 00000008 04020100 00000000 (00000000) + vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000) + vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000) + + vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsrh: => 00400030 00140007 00020000 00000000 (00000000) + vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrh: => 00400030 00140007 00020000 00000000 (00000000) + vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000) + vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000) + + vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsrw: => 00102030 00050607 000090a0 00001c1a (00000000) + vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrw: => 00000010 00000005 00000000 00000000 (00000000) + vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000) + vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000) + + vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsrab: => 00000000 00000008 04020100 00000000 (00000000) + vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrab: => 00000000 00000008 04020100 00000000 (00000000) + vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000) + vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000) + + vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsrah: => 00400030 00140007 00020000 00000000 (00000000) + vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrah: => 00400030 00140007 00020000 00000000 (00000000) + vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000) + vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000) + + vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsraw: => 00102030 00050607 000090a0 00001c1a (00000000) + vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsraw: => 00000010 00000005 00000000 00000000 (00000000) + vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000) + vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000) + + vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkuhum: => 02040608 0a0c0d0f 02040608 0a0c0d0f (00000000) + vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuhum: => 02040608 0a0c0d0f f2f4f6f8 fafcfdff (00000000) + vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkuhum: => f2f4f6f8 fafcfdff 02040608 0a0c0d0f (00000000) + vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuhum: => f2f4f6f8 fafcfdff f2f4f6f8 fafcfdff (00000000) + + vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkuwum: => 03040708 0b0c0e0f 03040708 0b0c0e0f (00000000) + vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuwum: => 03040708 0b0c0e0f f3f4f7f8 fbfcfeff (00000000) + vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkuwum: => f3f4f7f8 fbfcfeff 03040708 0b0c0e0f (00000000) + vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuwum: => f3f4f7f8 fbfcfeff f3f4f7f8 fbfcfeff (00000000) + + vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000) + vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000) + vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkshus: => 00000000 00000000 00000000 00000000 (00000000) + + vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000) + vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000) + vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000) + vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkswus: => 00000000 00000000 00000000 00000000 (00000000) + + vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000) + vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000) + vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000) + vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkshss: => 80808080 80808080 80808080 80808080 (00000000) + + vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000) + vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000) + vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000) + vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkswss: => 80008000 80008000 80008000 80008000 (00000000) + + vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vpkpx: => 80008001 84210421 80008001 84210421 (00000000) + vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkpx: => 80008001 84210421 fbdefbdf ffff7fff (00000000) + vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vpkpx: => fbdefbdf ffff7fff 80008001 84210421 (00000000) + vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vpkpx: => fbdefbdf ffff7fff fbdefbdf ffff7fff (00000000) + + vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrghb: => 01010202 03030404 05050606 07070808 (00000000) + vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghb: => 01f102f2 03f304f4 05f506f6 07f708f8 (00000000) + vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrghb: => f101f202 f303f404 f505f606 f707f808 (00000000) + vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghb: => f1f1f2f2 f3f3f4f4 f5f5f6f6 f7f7f8f8 (00000000) + + vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrghh: => 01020102 03040304 05060506 07080708 (00000000) + vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghh: => 0102f1f2 0304f3f4 0506f5f6 0708f7f8 (00000000) + vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrghh: => f1f20102 f3f40304 f5f60506 f7f80708 (00000000) + vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghh: => f1f2f1f2 f3f4f3f4 f5f6f5f6 f7f8f7f8 (00000000) + + vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrghw: => 01020304 01020304 05060708 05060708 (00000000) + vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000) + vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrghw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000) + vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrghw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000) + + vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrglb: => 09090a0a 0b0b0c0c 0e0e0d0d 0e0e0f0f (00000000) + vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglb: => 09f90afa 0bfb0cfc 0efe0dfd 0efe0fff (00000000) + vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrglb: => f909fa0a fb0bfc0c fe0efd0d fe0eff0f (00000000) + vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglb: => f9f9fafa fbfbfcfc fefefdfd fefeffff (00000000) + + vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrglh: => 090a090a 0b0c0b0c 0e0d0e0d 0e0f0e0f (00000000) + vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglh: => 090af9fa 0b0cfbfc 0e0dfefd 0e0ffeff (00000000) + vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrglh: => f9fa090a fbfc0b0c fefd0e0d feff0e0f (00000000) + vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglh: => f9faf9fa fbfcfbfc fefdfefd fefffeff (00000000) + + vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vmrglw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000) + vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000) + vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vmrglw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000) + vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vmrglw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000) + + vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vslo: => 02030405 06070809 0a0b0c0e 0d0e0f00 (00000000) + vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslo: => 0f000000 00000000 00000000 00000000 (00000000) + vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vslo: => f2f3f4f5 f6f7f8f9 fafbfcfe fdfeff00 (00000000) + vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vslo: => ff000000 00000000 00000000 00000000 (00000000) + + vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vsro: => 00010203 04050607 08090a0b 0c0e0d0e (00000000) + vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsro: => 00000000 00000000 00000000 00000001 (00000000) + vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vsro: => 00f1f2f3 f4f5f6f7 f8f9fafb fcfefdfe (00000000) + vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vsro: => 00000000 00000000 00000000 000000f1 (00000000) + +PPC altivec integer logical insns with one arg: + vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f + vupkhsb: => 00010002 00030004 00050006 00070008 (00000000) + vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupkhsb: => fff1fff2 fff3fff4 fff5fff6 fff7fff8 (00000000) + + vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f + vupkhsh: => 00000102 00000304 00000506 00000708 (00000000) + vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupkhsh: => fffff1f2 fffff3f4 fffff5f6 fffff7f8 (00000000) + + vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f + vupkhpx: => 00000802 00001804 00010806 00011808 (00000000) + vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupkhpx: => ff1c0f12 ff1c1f14 ff1d0f16 ff1d1f18 (00000000) + + vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f + vupklsb: => 0009000a 000b000c 000e000d 000e000f (00000000) + vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupklsb: => fff9fffa fffbfffc fffefffd fffeffff (00000000) + + vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f + vupklsh: => 0000090a 00000b0c 00000e0d 00000e0f (00000000) + vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupklsh: => fffff9fa fffffbfc fffffefd fffffeff (00000000) + + vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f + vupklpx: => 0002080a 0002180c 0003100d 0003100f (00000000) + vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff + vupklpx: => ff1e0f1a ff1e1f1c ff1f171d ff1f171f (00000000) + +Altivec integer compare insns: + vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) + + vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequb: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequb: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequh: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000) + vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequw: => 00000000 00000000 00000000 00000000 (00000000) + vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000) + +Altivec integer compare insns with flags update: + vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) + + vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080) + + vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080) + + vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f + vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080) + vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f + vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020) + vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff + vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080) + +Altivec integer special insns: + vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000 + vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101 + vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202 + vsl: => 04080c10 14181c20 24282c30 3834383c (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303 + vsl: => 08101820 28303840 48505860 70687078 (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404 + vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505 + vsl: => 20406080 a0c0e101 21416181 c1a1c1e0 (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606 + vsl: => 4080c101 4181c202 4282c303 834383c0 (00000000) + vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707 + vsl: => 81018202 83038404 85058607 06870780 (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000 + vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101 + vsl: => e3e5e7e9 ebedeff1 f3f5f7f9 fdfbfdfe (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202 + vsl: => c7cbcfd3 d7dbdfe3 e7ebeff3 fbf7fbfc (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303 + vsl: => 8f979fa7 afb7bfc7 cfd7dfe7 f7eff7f8 (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404 + vsl: => 1f2f3f4f 5f6f7f8f 9fafbfcf efdfeff0 (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505 + vsl: => 3e5e7e9e bedeff1f 3f5f7f9f dfbfdfe0 (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606 + vsl: => 7cbcfd3d 7dbdfe3e 7ebeff3f bf7fbfc0 (00000000) + vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707 + vsl: => f979fa7a fb7bfc7c fd7dfe7f 7eff7f80 (00000000) + + vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000 + vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101 + vsr: => 00810182 02830384 04850586 07068707 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202 + vsr: => 004080c1 014181c2 024282c3 03834383 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303 + vsr: => 00204060 80a0c0e1 01214161 81c1a1c1 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404 + vsr: => 00102030 40506070 8090a0b0 c0e0d0e0 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505 + vsr: => 00081018 20283038 40485058 60706870 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606 + vsr: => 0004080c 1014181c 2024282c 30383438 (00000000) + vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707 + vsr: => 00020406 080a0c0e 10121416 181c1a1c (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000 + vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101 + vsr: => 78f979fa 7afb7bfc 7cfd7dfe 7f7eff7f (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202 + vsr: => 3c7cbcfd 3d7dbdfe 3e7ebeff 3fbf7fbf (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303 + vsr: => 1e3e5e7e 9ebedeff 1f3f5f7f 9fdfbfdf (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404 + vsr: => 0f1f2f3f 4f5f6f7f 8f9fafbf cfefdfef (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505 + vsr: => 078f979f a7afb7bf c7cfd7df e7f7eff7 (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606 + vsr: => 03c7cbcf d3d7dbdf e3e7ebef f3fbf7fb (00000000) + vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707 + vsr: => 01e3e5e7 e9ebedef f1f3f5f7 f9fdfbfd (00000000) + + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0 + vspltb: => 01010101 01010101 01010101 01010101 (00000000) + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3 + vspltb: => 04040404 04040404 04040404 04040404 (00000000) + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6 + vspltb: => 07070707 07070707 07070707 07070707 (00000000) + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9 + vspltb: => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000) + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12 + vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000) + vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15 + vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 + vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 + vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 + vspltb: => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 + vspltb: => fafafafa fafafafa fafafafa fafafafa (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 + vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000) + vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 + vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0 + vsplth: => 01020102 01020102 01020102 01020102 (00000000) + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3 + vsplth: => 07080708 07080708 07080708 07080708 (00000000) + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6 + vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000) + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9 + vsplth: => 03040304 03040304 03040304 03040304 (00000000) + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12 + vsplth: => 090a090a 090a090a 090a090a 090a090a (00000000) + vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15 + vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 + vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 + vsplth: => f7f8f7f8 f7f8f7f8 f7f8f7f8 f7f8f7f8 (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 + vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 + vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 + vsplth: => f9faf9fa f9faf9fa f9faf9fa f9faf9fa (00000000) + vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 + vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000) + + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0 + vspltw: => 01020304 01020304 01020304 01020304 (00000000) + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3 + vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000) + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6 + vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000) + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9 + vspltw: => 05060708 05060708 05060708 05060708 (00000000) + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12 + vspltw: => 01020304 01020304 01020304 01020304 (00000000) + vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15 + vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 + vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 + vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 + vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 + vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 + vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000) + vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 + vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000) + + vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000) + vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000) + vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000) + vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000) + vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000) + vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000) + vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000) + vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000) + vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000) + vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000) + vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000) + vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000) + vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000) + vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000) + vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000) + vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000) + vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) + vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000) + vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000) + vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000) + vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000) + vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000) + vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000) + vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000) + vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000) + vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000) + vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000) + vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000) + vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000) + vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000) + vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000) + vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) + + vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000) + vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000) + vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000) + vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000) + vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000) + vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000) + vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000) + vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000) + vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000) + vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000) + vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000) + vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000) + vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000) + vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000) + vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000) + vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000) + vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000) + vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000) + vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000) + vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000) + vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000) + vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000) + vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000) + vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000) + vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000) + vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000) + vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000) + vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000) + vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000) + vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000) + vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000) + vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) + + vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000) + vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000) + vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000) + vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000) + vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000) + vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000) + vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000) + vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000) + vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000) + vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000) + vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000) + vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000) + vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000) + vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000) + vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000) + vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000) + vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000) + vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000) + vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000) + vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000) + vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000) + vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000) + vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000) + vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000) + vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000) + vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000) + vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000) + vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000) + vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000) + vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000) + vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000) + vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) + + vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0 + vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000) + vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14 + vsldoi: => 0e0f0102 03040506 0708090a 0b0c0e0d] (00000000) + vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0 + vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000) + vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 + vsldoi: => 0e0ff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000) + vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0 + vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000) + vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14 + vsldoi: => feff0102 03040506 0708090a 0b0c0e0d] (00000000) + vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0 + vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000) + vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 + vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000) + +All done. Tested 283 different instructions diff --git a/none/tests/ppc32/jm-vmx.vgtest b/none/tests/ppc32/jm-vmx.vgtest new file mode 100644 index 0000000000..0f32c0d2b2 --- /dev/null +++ b/none/tests/ppc32/jm-vmx.vgtest @@ -0,0 +1 @@ +prog: jm-insns -a