From: Ramana Radhakrishnan Date: Tue, 4 Jul 2017 15:18:47 +0000 (+0100) Subject: [Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3e5f4497f7fcfaa6f4e0188c3f12318d192b2dff;p=thirdparty%2Fbinutils-gdb.git [Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). regards Ramana 2017-07-04 Ramana Radhakrishnan * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 046883f5496..a89a5f5d65d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,15 @@ +2017-04-05 Ramana Radhakrishnan + + Backport from mainline + 2017-04-04 Ramana Radhakrishnan + * config/tc-arm.c (arm_regs): Add MVFR2. + (do_vmrs): Constraint for MVFR2 and armv8. + (do_vmsr): Likewise. + * testsuite/gas/arm/armv8-a+fp.d: Update. + * testsuite/gas/arm/armv8-a+fp.s: Likewise. + * testsuite/gas/arm/vfp-bad.s: Likewise. + * testsuite/gas/arm/vfp-bad.l: Likewise. + 2017-06-20 Thomas Preud'homme Backport from mainline diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 0820b96891f..be85927319c 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -9108,6 +9108,11 @@ do_vmrs (void) return; } + /* MVFR2 is only valid at ARMv8-A. */ + if (inst.operands[1].reg == 5) + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), + _(BAD_FPU)); + /* APSR_ sets isvec. All other refs to PC are illegal. */ if (!inst.operands[0].isvec && Rt == REG_PC) { @@ -9134,6 +9139,11 @@ do_vmsr (void) return; } + /* MVFR2 is only valid for ARMv8-A. */ + if (inst.operands[0].reg == 5) + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), + _(BAD_FPU)); + /* If we get through parsing the register name, we just insert the number generated into the instruction without further validation. */ inst.instruction |= (inst.operands[0].reg << 16); @@ -18795,6 +18805,7 @@ static const struct reg_entry reg_names[] = REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), + REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), /* Maverick DSP coprocessor registers. */ REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d index f77e742adc9..5a2c95ab3f0 100644 --- a/gas/testsuite/gas/arm/armv8-a+fp.d +++ b/gas/testsuite/gas/arm/armv8-a+fp.d @@ -113,3 +113,7 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1 0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30 0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31 +0[0-9a-f]+ <[^>]+> eef5 9a10 vmrs r9, mvfr2 +0[0-9a-f]+ <[^>]+> eee5 7a10 vmsr mvfr2, r7 +0[0-9a-f]+ <[^>]+> eef5 4a10 vmrs r4, mvfr2 +0[0-9a-f]+ <[^>]+> eee5 5a10 vmsr mvfr2, r5 \ No newline at end of file diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s index f7a54736a15..b98aab7b9af 100644 --- a/gas/testsuite/gas/arm/armv8-a+fp.s +++ b/gas/testsuite/gas/arm/armv8-a+fp.s @@ -114,3 +114,8 @@ vcvtb.f64.f16 d16, s1 vcvtt.f64.f16 d15, s30 vcvtb.f64.f16 d31, s31 + vmrs r9, MVFR2 + vmsr MVFR2, r7 + vmrs r4, mvfr2 + vmsr mvfr2, r5 + diff --git a/gas/testsuite/gas/arm/vfp-bad.l b/gas/testsuite/gas/arm/vfp-bad.l index 7726e63180b..a1479f484fe 100644 --- a/gas/testsuite/gas/arm/vfp-bad.l +++ b/gas/testsuite/gas/arm/vfp-bad.l @@ -7,3 +7,5 @@ [^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' [^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' [^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' +[^:]*:12: Error: selected FPU does not support instruction -- `vmrs r0,MVFR2' +[^:]*:13: Error: selected FPU does not support instruction -- `vmsr MVFR2,r2' diff --git a/gas/testsuite/gas/arm/vfp-bad.s b/gas/testsuite/gas/arm/vfp-bad.s index ac44371773f..1a446fee936 100644 --- a/gas/testsuite/gas/arm/vfp-bad.s +++ b/gas/testsuite/gas/arm/vfp-bad.s @@ -9,3 +9,5 @@ entry: fldd d0, [r0, #-8]! flds s0, [r0], #8 flds s0, [r0, #-8]! + vmrs r0, MVFR2 + vmsr MVFR2, r2 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5dfe1661fad..dc6c635360a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2017-07-05 Ramana Radhakrishnan + + Backport from mainline + 2017-07-04 Ramana Radhakrishnan + * arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr. + 2017-05-01 Michael Clark * riscv-opc.c (riscv_opcodes) : Use RA not T1 as a temporary diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 167c6685c5c..eeeea58cbd9 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -506,6 +506,8 @@ static const struct opcode32 coprocessor_opcodes[] = 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), @@ -518,6 +520,8 @@ static const struct opcode32 coprocessor_opcodes[] = 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),